stm32ral/stm32g0/peripherals/tim2_v1.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! General-purpose-timers
4//!
5//! Used by: stm32g030, stm32g031, stm32g041, stm32g071, stm32g081
6
7use crate::{RWRegister, WORegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// control register 1
12pub mod CR1 {
13
14 /// UIF status bit remapping
15 pub mod UIFREMAP {
16 /// Offset (11 bits)
17 pub const offset: u32 = 11;
18 /// Mask (1 bit: 1 << 11)
19 pub const mask: u32 = 1 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values (empty)
25 pub mod RW {}
26 }
27
28 /// Clock division
29 pub mod CKD {
30 /// Offset (8 bits)
31 pub const offset: u32 = 8;
32 /// Mask (2 bits: 0b11 << 8)
33 pub const mask: u32 = 0b11 << offset;
34 /// Read-only values (empty)
35 pub mod R {}
36 /// Write-only values (empty)
37 pub mod W {}
38 /// Read-write values
39 pub mod RW {
40
41 /// 0b00: t_DTS = t_CK_INT
42 pub const Div1: u32 = 0b00;
43
44 /// 0b01: t_DTS = 2 × t_CK_INT
45 pub const Div2: u32 = 0b01;
46
47 /// 0b10: t_DTS = 4 × t_CK_INT
48 pub const Div4: u32 = 0b10;
49 }
50 }
51
52 /// Auto-reload preload enable
53 pub mod ARPE {
54 /// Offset (7 bits)
55 pub const offset: u32 = 7;
56 /// Mask (1 bit: 1 << 7)
57 pub const mask: u32 = 1 << offset;
58 /// Read-only values (empty)
59 pub mod R {}
60 /// Write-only values (empty)
61 pub mod W {}
62 /// Read-write values
63 pub mod RW {
64
65 /// 0b0: TIMx_APRR register is not buffered
66 pub const Disabled: u32 = 0b0;
67
68 /// 0b1: TIMx_APRR register is buffered
69 pub const Enabled: u32 = 0b1;
70 }
71 }
72
73 /// Center-aligned mode selection
74 pub mod CMS {
75 /// Offset (5 bits)
76 pub const offset: u32 = 5;
77 /// Mask (2 bits: 0b11 << 5)
78 pub const mask: u32 = 0b11 << offset;
79 /// Read-only values (empty)
80 pub mod R {}
81 /// Write-only values (empty)
82 pub mod W {}
83 /// Read-write values
84 pub mod RW {
85
86 /// 0b00: The counter counts up or down depending on the direction bit
87 pub const EdgeAligned: u32 = 0b00;
88
89 /// 0b01: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
90 pub const CenterAligned1: u32 = 0b01;
91
92 /// 0b10: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
93 pub const CenterAligned2: u32 = 0b10;
94
95 /// 0b11: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
96 pub const CenterAligned3: u32 = 0b11;
97 }
98 }
99
100 /// Direction
101 pub mod DIR {
102 /// Offset (4 bits)
103 pub const offset: u32 = 4;
104 /// Mask (1 bit: 1 << 4)
105 pub const mask: u32 = 1 << offset;
106 /// Read-only values (empty)
107 pub mod R {}
108 /// Write-only values (empty)
109 pub mod W {}
110 /// Read-write values
111 pub mod RW {
112
113 /// 0b0: Counter used as upcounter
114 pub const Up: u32 = 0b0;
115
116 /// 0b1: Counter used as downcounter
117 pub const Down: u32 = 0b1;
118 }
119 }
120
121 /// One-pulse mode
122 pub mod OPM {
123 /// Offset (3 bits)
124 pub const offset: u32 = 3;
125 /// Mask (1 bit: 1 << 3)
126 pub const mask: u32 = 1 << offset;
127 /// Read-only values (empty)
128 pub mod R {}
129 /// Write-only values (empty)
130 pub mod W {}
131 /// Read-write values
132 pub mod RW {
133
134 /// 0b0: Counter is not stopped at update event
135 pub const Disabled: u32 = 0b0;
136
137 /// 0b1: Counter stops counting at the next update event (clearing the CEN bit)
138 pub const Enabled: u32 = 0b1;
139 }
140 }
141
142 /// Update request source
143 pub mod URS {
144 /// Offset (2 bits)
145 pub const offset: u32 = 2;
146 /// Mask (1 bit: 1 << 2)
147 pub const mask: u32 = 1 << offset;
148 /// Read-only values (empty)
149 pub mod R {}
150 /// Write-only values (empty)
151 pub mod W {}
152 /// Read-write values
153 pub mod RW {
154
155 /// 0b0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
156 pub const AnyEvent: u32 = 0b0;
157
158 /// 0b1: Only counter overflow/underflow generates an update interrupt or DMA request
159 pub const CounterOnly: u32 = 0b1;
160 }
161 }
162
163 /// Update disable
164 pub mod UDIS {
165 /// Offset (1 bits)
166 pub const offset: u32 = 1;
167 /// Mask (1 bit: 1 << 1)
168 pub const mask: u32 = 1 << offset;
169 /// Read-only values (empty)
170 pub mod R {}
171 /// Write-only values (empty)
172 pub mod W {}
173 /// Read-write values
174 pub mod RW {
175
176 /// 0b0: Update event enabled
177 pub const Enabled: u32 = 0b0;
178
179 /// 0b1: Update event disabled
180 pub const Disabled: u32 = 0b1;
181 }
182 }
183
184 /// Counter enable
185 pub mod CEN {
186 /// Offset (0 bits)
187 pub const offset: u32 = 0;
188 /// Mask (1 bit: 1 << 0)
189 pub const mask: u32 = 1 << offset;
190 /// Read-only values (empty)
191 pub mod R {}
192 /// Write-only values (empty)
193 pub mod W {}
194 /// Read-write values
195 pub mod RW {
196
197 /// 0b0: Counter disabled
198 pub const Disabled: u32 = 0b0;
199
200 /// 0b1: Counter enabled
201 pub const Enabled: u32 = 0b1;
202 }
203 }
204}
205
206/// control register 2
207pub mod CR2 {
208
209 /// TI1 selection
210 pub mod TI1S {
211 /// Offset (7 bits)
212 pub const offset: u32 = 7;
213 /// Mask (1 bit: 1 << 7)
214 pub const mask: u32 = 1 << offset;
215 /// Read-only values (empty)
216 pub mod R {}
217 /// Write-only values (empty)
218 pub mod W {}
219 /// Read-write values (empty)
220 pub mod RW {}
221 }
222
223 /// Master mode selection
224 pub mod MMS {
225 /// Offset (4 bits)
226 pub const offset: u32 = 4;
227 /// Mask (3 bits: 0b111 << 4)
228 pub const mask: u32 = 0b111 << offset;
229 /// Read-only values (empty)
230 pub mod R {}
231 /// Write-only values (empty)
232 pub mod W {}
233 /// Read-write values (empty)
234 pub mod RW {}
235 }
236
237 /// Capture/compare DMA selection
238 pub mod CCDS {
239 /// Offset (3 bits)
240 pub const offset: u32 = 3;
241 /// Mask (1 bit: 1 << 3)
242 pub const mask: u32 = 1 << offset;
243 /// Read-only values (empty)
244 pub mod R {}
245 /// Write-only values (empty)
246 pub mod W {}
247 /// Read-write values (empty)
248 pub mod RW {}
249 }
250}
251
252/// slave mode control register
253pub mod SMCR {
254
255 /// Trigger selection
256 pub mod TS_4_3 {
257 /// Offset (20 bits)
258 pub const offset: u32 = 20;
259 /// Mask (2 bits: 0b11 << 20)
260 pub const mask: u32 = 0b11 << offset;
261 /// Read-only values (empty)
262 pub mod R {}
263 /// Write-only values (empty)
264 pub mod W {}
265 /// Read-write values (empty)
266 pub mod RW {}
267 }
268
269 /// Slave mode selection - bit 3
270 pub mod SMS_3 {
271 /// Offset (16 bits)
272 pub const offset: u32 = 16;
273 /// Mask (1 bit: 1 << 16)
274 pub const mask: u32 = 1 << offset;
275 /// Read-only values (empty)
276 pub mod R {}
277 /// Write-only values (empty)
278 pub mod W {}
279 /// Read-write values (empty)
280 pub mod RW {}
281 }
282
283 /// External trigger polarity
284 pub mod ETP {
285 /// Offset (15 bits)
286 pub const offset: u32 = 15;
287 /// Mask (1 bit: 1 << 15)
288 pub const mask: u32 = 1 << offset;
289 /// Read-only values (empty)
290 pub mod R {}
291 /// Write-only values (empty)
292 pub mod W {}
293 /// Read-write values (empty)
294 pub mod RW {}
295 }
296
297 /// External clock enable
298 pub mod ECE {
299 /// Offset (14 bits)
300 pub const offset: u32 = 14;
301 /// Mask (1 bit: 1 << 14)
302 pub const mask: u32 = 1 << offset;
303 /// Read-only values (empty)
304 pub mod R {}
305 /// Write-only values (empty)
306 pub mod W {}
307 /// Read-write values (empty)
308 pub mod RW {}
309 }
310
311 /// External trigger prescaler
312 pub mod ETPS {
313 /// Offset (12 bits)
314 pub const offset: u32 = 12;
315 /// Mask (2 bits: 0b11 << 12)
316 pub const mask: u32 = 0b11 << offset;
317 /// Read-only values (empty)
318 pub mod R {}
319 /// Write-only values (empty)
320 pub mod W {}
321 /// Read-write values (empty)
322 pub mod RW {}
323 }
324
325 /// External trigger filter
326 pub mod ETF {
327 /// Offset (8 bits)
328 pub const offset: u32 = 8;
329 /// Mask (4 bits: 0b1111 << 8)
330 pub const mask: u32 = 0b1111 << offset;
331 /// Read-only values (empty)
332 pub mod R {}
333 /// Write-only values (empty)
334 pub mod W {}
335 /// Read-write values (empty)
336 pub mod RW {}
337 }
338
339 /// Master/Slave mode
340 pub mod MSM {
341 /// Offset (7 bits)
342 pub const offset: u32 = 7;
343 /// Mask (1 bit: 1 << 7)
344 pub const mask: u32 = 1 << offset;
345 /// Read-only values (empty)
346 pub mod R {}
347 /// Write-only values (empty)
348 pub mod W {}
349 /// Read-write values (empty)
350 pub mod RW {}
351 }
352
353 /// Trigger selection
354 pub mod TS {
355 /// Offset (4 bits)
356 pub const offset: u32 = 4;
357 /// Mask (3 bits: 0b111 << 4)
358 pub const mask: u32 = 0b111 << offset;
359 /// Read-only values (empty)
360 pub mod R {}
361 /// Write-only values (empty)
362 pub mod W {}
363 /// Read-write values (empty)
364 pub mod RW {}
365 }
366
367 /// OCREF clear selection
368 pub mod OCCS {
369 /// Offset (3 bits)
370 pub const offset: u32 = 3;
371 /// Mask (1 bit: 1 << 3)
372 pub const mask: u32 = 1 << offset;
373 /// Read-only values (empty)
374 pub mod R {}
375 /// Write-only values (empty)
376 pub mod W {}
377 /// Read-write values (empty)
378 pub mod RW {}
379 }
380
381 /// Slave mode selection
382 pub mod SMS {
383 /// Offset (0 bits)
384 pub const offset: u32 = 0;
385 /// Mask (3 bits: 0b111 << 0)
386 pub const mask: u32 = 0b111 << offset;
387 /// Read-only values (empty)
388 pub mod R {}
389 /// Write-only values (empty)
390 pub mod W {}
391 /// Read-write values (empty)
392 pub mod RW {}
393 }
394}
395
396/// DMA/Interrupt enable register
397pub mod DIER {
398
399 /// Trigger DMA request enable
400 pub mod TDE {
401 /// Offset (14 bits)
402 pub const offset: u32 = 14;
403 /// Mask (1 bit: 1 << 14)
404 pub const mask: u32 = 1 << offset;
405 /// Read-only values (empty)
406 pub mod R {}
407 /// Write-only values (empty)
408 pub mod W {}
409 /// Read-write values (empty)
410 pub mod RW {}
411 }
412
413 /// Capture/Compare 4 DMA request enable
414 pub mod CC4DE {
415 /// Offset (12 bits)
416 pub const offset: u32 = 12;
417 /// Mask (1 bit: 1 << 12)
418 pub const mask: u32 = 1 << offset;
419 /// Read-only values (empty)
420 pub mod R {}
421 /// Write-only values (empty)
422 pub mod W {}
423 /// Read-write values (empty)
424 pub mod RW {}
425 }
426
427 /// Capture/Compare 3 DMA request enable
428 pub mod CC3DE {
429 /// Offset (11 bits)
430 pub const offset: u32 = 11;
431 /// Mask (1 bit: 1 << 11)
432 pub const mask: u32 = 1 << offset;
433 /// Read-only values (empty)
434 pub mod R {}
435 /// Write-only values (empty)
436 pub mod W {}
437 /// Read-write values (empty)
438 pub mod RW {}
439 }
440
441 /// Capture/Compare 2 DMA request enable
442 pub mod CC2DE {
443 /// Offset (10 bits)
444 pub const offset: u32 = 10;
445 /// Mask (1 bit: 1 << 10)
446 pub const mask: u32 = 1 << offset;
447 /// Read-only values (empty)
448 pub mod R {}
449 /// Write-only values (empty)
450 pub mod W {}
451 /// Read-write values (empty)
452 pub mod RW {}
453 }
454
455 /// Capture/Compare 1 DMA request enable
456 pub mod CC1DE {
457 /// Offset (9 bits)
458 pub const offset: u32 = 9;
459 /// Mask (1 bit: 1 << 9)
460 pub const mask: u32 = 1 << offset;
461 /// Read-only values (empty)
462 pub mod R {}
463 /// Write-only values (empty)
464 pub mod W {}
465 /// Read-write values (empty)
466 pub mod RW {}
467 }
468
469 /// Update DMA request enable
470 pub mod UDE {
471 /// Offset (8 bits)
472 pub const offset: u32 = 8;
473 /// Mask (1 bit: 1 << 8)
474 pub const mask: u32 = 1 << offset;
475 /// Read-only values (empty)
476 pub mod R {}
477 /// Write-only values (empty)
478 pub mod W {}
479 /// Read-write values (empty)
480 pub mod RW {}
481 }
482
483 /// Trigger interrupt enable
484 pub mod TIE {
485 /// Offset (6 bits)
486 pub const offset: u32 = 6;
487 /// Mask (1 bit: 1 << 6)
488 pub const mask: u32 = 1 << offset;
489 /// Read-only values (empty)
490 pub mod R {}
491 /// Write-only values (empty)
492 pub mod W {}
493 /// Read-write values (empty)
494 pub mod RW {}
495 }
496
497 /// Capture/Compare 4 interrupt enable
498 pub mod CC4IE {
499 /// Offset (4 bits)
500 pub const offset: u32 = 4;
501 /// Mask (1 bit: 1 << 4)
502 pub const mask: u32 = 1 << offset;
503 /// Read-only values (empty)
504 pub mod R {}
505 /// Write-only values (empty)
506 pub mod W {}
507 /// Read-write values (empty)
508 pub mod RW {}
509 }
510
511 /// Capture/Compare 3 interrupt enable
512 pub mod CC3IE {
513 /// Offset (3 bits)
514 pub const offset: u32 = 3;
515 /// Mask (1 bit: 1 << 3)
516 pub const mask: u32 = 1 << offset;
517 /// Read-only values (empty)
518 pub mod R {}
519 /// Write-only values (empty)
520 pub mod W {}
521 /// Read-write values (empty)
522 pub mod RW {}
523 }
524
525 /// Capture/Compare 2 interrupt enable
526 pub mod CC2IE {
527 /// Offset (2 bits)
528 pub const offset: u32 = 2;
529 /// Mask (1 bit: 1 << 2)
530 pub const mask: u32 = 1 << offset;
531 /// Read-only values (empty)
532 pub mod R {}
533 /// Write-only values (empty)
534 pub mod W {}
535 /// Read-write values (empty)
536 pub mod RW {}
537 }
538
539 /// Capture/Compare 1 interrupt enable
540 pub mod CC1IE {
541 /// Offset (1 bits)
542 pub const offset: u32 = 1;
543 /// Mask (1 bit: 1 << 1)
544 pub const mask: u32 = 1 << offset;
545 /// Read-only values (empty)
546 pub mod R {}
547 /// Write-only values (empty)
548 pub mod W {}
549 /// Read-write values (empty)
550 pub mod RW {}
551 }
552
553 /// Update interrupt enable
554 pub mod UIE {
555 /// Offset (0 bits)
556 pub const offset: u32 = 0;
557 /// Mask (1 bit: 1 << 0)
558 pub const mask: u32 = 1 << offset;
559 /// Read-only values (empty)
560 pub mod R {}
561 /// Write-only values (empty)
562 pub mod W {}
563 /// Read-write values
564 pub mod RW {
565
566 /// 0b0: Update interrupt disabled
567 pub const Disabled: u32 = 0b0;
568
569 /// 0b1: Update interrupt enabled
570 pub const Enabled: u32 = 0b1;
571 }
572 }
573}
574
575/// status register
576pub mod SR {
577
578 /// Capture/Compare 4 overcapture flag
579 pub mod CC4OF {
580 /// Offset (12 bits)
581 pub const offset: u32 = 12;
582 /// Mask (1 bit: 1 << 12)
583 pub const mask: u32 = 1 << offset;
584 /// Read-only values (empty)
585 pub mod R {}
586 /// Write-only values (empty)
587 pub mod W {}
588 /// Read-write values (empty)
589 pub mod RW {}
590 }
591
592 /// Capture/Compare 3 overcapture flag
593 pub mod CC3OF {
594 /// Offset (11 bits)
595 pub const offset: u32 = 11;
596 /// Mask (1 bit: 1 << 11)
597 pub const mask: u32 = 1 << offset;
598 /// Read-only values (empty)
599 pub mod R {}
600 /// Write-only values (empty)
601 pub mod W {}
602 /// Read-write values (empty)
603 pub mod RW {}
604 }
605
606 /// Capture/compare 2 overcapture flag
607 pub mod CC2OF {
608 /// Offset (10 bits)
609 pub const offset: u32 = 10;
610 /// Mask (1 bit: 1 << 10)
611 pub const mask: u32 = 1 << offset;
612 /// Read-only values (empty)
613 pub mod R {}
614 /// Write-only values (empty)
615 pub mod W {}
616 /// Read-write values (empty)
617 pub mod RW {}
618 }
619
620 /// Capture/Compare 1 overcapture flag
621 pub mod CC1OF {
622 /// Offset (9 bits)
623 pub const offset: u32 = 9;
624 /// Mask (1 bit: 1 << 9)
625 pub const mask: u32 = 1 << offset;
626 /// Read-only values (empty)
627 pub mod R {}
628 /// Write-only values (empty)
629 pub mod W {}
630 /// Read-write values (empty)
631 pub mod RW {}
632 }
633
634 /// Trigger interrupt flag
635 pub mod TIF {
636 /// Offset (6 bits)
637 pub const offset: u32 = 6;
638 /// Mask (1 bit: 1 << 6)
639 pub const mask: u32 = 1 << offset;
640 /// Read-only values (empty)
641 pub mod R {}
642 /// Write-only values (empty)
643 pub mod W {}
644 /// Read-write values (empty)
645 pub mod RW {}
646 }
647
648 /// Capture/Compare 4 interrupt flag
649 pub mod CC4IF {
650 /// Offset (4 bits)
651 pub const offset: u32 = 4;
652 /// Mask (1 bit: 1 << 4)
653 pub const mask: u32 = 1 << offset;
654 /// Read-only values (empty)
655 pub mod R {}
656 /// Write-only values (empty)
657 pub mod W {}
658 /// Read-write values (empty)
659 pub mod RW {}
660 }
661
662 /// Capture/Compare 3 interrupt flag
663 pub mod CC3IF {
664 /// Offset (3 bits)
665 pub const offset: u32 = 3;
666 /// Mask (1 bit: 1 << 3)
667 pub const mask: u32 = 1 << offset;
668 /// Read-only values (empty)
669 pub mod R {}
670 /// Write-only values (empty)
671 pub mod W {}
672 /// Read-write values (empty)
673 pub mod RW {}
674 }
675
676 /// Capture/Compare 2 interrupt flag
677 pub mod CC2IF {
678 /// Offset (2 bits)
679 pub const offset: u32 = 2;
680 /// Mask (1 bit: 1 << 2)
681 pub const mask: u32 = 1 << offset;
682 /// Read-only values (empty)
683 pub mod R {}
684 /// Write-only values (empty)
685 pub mod W {}
686 /// Read-write values (empty)
687 pub mod RW {}
688 }
689
690 /// Capture/compare 1 interrupt flag
691 pub mod CC1IF {
692 /// Offset (1 bits)
693 pub const offset: u32 = 1;
694 /// Mask (1 bit: 1 << 1)
695 pub const mask: u32 = 1 << offset;
696 /// Read-only values (empty)
697 pub mod R {}
698 /// Write-only values (empty)
699 pub mod W {}
700 /// Read-write values (empty)
701 pub mod RW {}
702 }
703
704 /// Update interrupt flag
705 pub mod UIF {
706 /// Offset (0 bits)
707 pub const offset: u32 = 0;
708 /// Mask (1 bit: 1 << 0)
709 pub const mask: u32 = 1 << offset;
710 /// Read-only values (empty)
711 pub mod R {}
712 /// Write-only values (empty)
713 pub mod W {}
714 /// Read-write values
715 pub mod RW {
716
717 /// 0b0: No update occurred
718 pub const Clear: u32 = 0b0;
719
720 /// 0b1: Update interrupt pending.
721 pub const UpdatePending: u32 = 0b1;
722 }
723 }
724}
725
726/// event generation register
727pub mod EGR {
728
729 /// Trigger generation
730 pub mod TG {
731 /// Offset (6 bits)
732 pub const offset: u32 = 6;
733 /// Mask (1 bit: 1 << 6)
734 pub const mask: u32 = 1 << offset;
735 /// Read-only values (empty)
736 pub mod R {}
737 /// Write-only values (empty)
738 pub mod W {}
739 /// Read-write values (empty)
740 pub mod RW {}
741 }
742
743 /// Capture/compare 4 generation
744 pub mod CC4G {
745 /// Offset (4 bits)
746 pub const offset: u32 = 4;
747 /// Mask (1 bit: 1 << 4)
748 pub const mask: u32 = 1 << offset;
749 /// Read-only values (empty)
750 pub mod R {}
751 /// Write-only values (empty)
752 pub mod W {}
753 /// Read-write values (empty)
754 pub mod RW {}
755 }
756
757 /// Capture/compare 3 generation
758 pub mod CC3G {
759 /// Offset (3 bits)
760 pub const offset: u32 = 3;
761 /// Mask (1 bit: 1 << 3)
762 pub const mask: u32 = 1 << offset;
763 /// Read-only values (empty)
764 pub mod R {}
765 /// Write-only values (empty)
766 pub mod W {}
767 /// Read-write values (empty)
768 pub mod RW {}
769 }
770
771 /// Capture/compare 2 generation
772 pub mod CC2G {
773 /// Offset (2 bits)
774 pub const offset: u32 = 2;
775 /// Mask (1 bit: 1 << 2)
776 pub const mask: u32 = 1 << offset;
777 /// Read-only values (empty)
778 pub mod R {}
779 /// Write-only values (empty)
780 pub mod W {}
781 /// Read-write values (empty)
782 pub mod RW {}
783 }
784
785 /// Capture/compare 1 generation
786 pub mod CC1G {
787 /// Offset (1 bits)
788 pub const offset: u32 = 1;
789 /// Mask (1 bit: 1 << 1)
790 pub const mask: u32 = 1 << offset;
791 /// Read-only values (empty)
792 pub mod R {}
793 /// Write-only values (empty)
794 pub mod W {}
795 /// Read-write values (empty)
796 pub mod RW {}
797 }
798
799 /// Update generation
800 pub mod UG {
801 /// Offset (0 bits)
802 pub const offset: u32 = 0;
803 /// Mask (1 bit: 1 << 0)
804 pub const mask: u32 = 1 << offset;
805 /// Read-only values (empty)
806 pub mod R {}
807 /// Write-only values
808 pub mod W {
809
810 /// 0b1: Re-initializes the timer counter and generates an update of the registers.
811 pub const Update: u32 = 0b1;
812 }
813 /// Read-write values (empty)
814 pub mod RW {}
815 }
816}
817
818/// CCMR1_Output and CCMR1_Input
819/// CCMR1_Output: capture/compare mode register 1 (output mode)
820/// CCMR1_Input: capture/compare mode register 1 (input mode)
821pub mod CCMR1 {
822
823 /// Output Compare 2 mode - bit 3
824 pub mod OC2M_3 {
825 /// Offset (24 bits)
826 pub const offset: u32 = 24;
827 /// Mask (1 bit: 1 << 24)
828 pub const mask: u32 = 1 << offset;
829 /// Read-only values (empty)
830 pub mod R {}
831 /// Write-only values (empty)
832 pub mod W {}
833 /// Read-write values
834 pub mod RW {
835
836 /// 0b0: Normal output compare mode (modes 0-7)
837 pub const Normal: u32 = 0b0;
838
839 /// 0b1: Extended output compare mode (modes 7-15)
840 pub const Extended: u32 = 0b1;
841 }
842 }
843
844 /// Output Compare 1 mode - bit 3
845 pub mod OC1M_3 {
846 /// Offset (16 bits)
847 pub const offset: u32 = 16;
848 /// Mask (1 bit: 1 << 16)
849 pub const mask: u32 = 1 << offset;
850 /// Read-only values (empty)
851 pub mod R {}
852 /// Write-only values (empty)
853 pub mod W {}
854 pub use super::OC2M_3::RW;
855 }
856
857 /// Output compare 2 clear enable
858 pub mod OC2CE {
859 /// Offset (15 bits)
860 pub const offset: u32 = 15;
861 /// Mask (1 bit: 1 << 15)
862 pub const mask: u32 = 1 << offset;
863 /// Read-only values (empty)
864 pub mod R {}
865 /// Write-only values (empty)
866 pub mod W {}
867 /// Read-write values (empty)
868 pub mod RW {}
869 }
870
871 /// Output compare 2 mode
872 pub mod OC2M {
873 /// Offset (12 bits)
874 pub const offset: u32 = 12;
875 /// Mask (3 bits: 0b111 << 12)
876 pub const mask: u32 = 0b111 << offset;
877 /// Read-only values (empty)
878 pub mod R {}
879 /// Write-only values (empty)
880 pub mod W {}
881 /// Read-write values
882 pub mod RW {
883
884 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
885 pub const Frozen: u32 = 0b000;
886
887 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
888 pub const ActiveOnMatch: u32 = 0b001;
889
890 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
891 pub const InactiveOnMatch: u32 = 0b010;
892
893 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy
894 pub const Toggle: u32 = 0b011;
895
896 /// 0b100: OCyREF is forced low
897 pub const ForceInactive: u32 = 0b100;
898
899 /// 0b101: OCyREF is forced high
900 pub const ForceActive: u32 = 0b101;
901
902 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
903 pub const PwmMode1: u32 = 0b110;
904
905 /// 0b111: Inversely to PwmMode1
906 pub const PwmMode2: u32 = 0b111;
907 }
908 }
909
910 /// Output compare 2 preload enable
911 pub mod OC2PE {
912 /// Offset (11 bits)
913 pub const offset: u32 = 11;
914 /// Mask (1 bit: 1 << 11)
915 pub const mask: u32 = 1 << offset;
916 /// Read-only values (empty)
917 pub mod R {}
918 /// Write-only values (empty)
919 pub mod W {}
920 /// Read-write values (empty)
921 pub mod RW {}
922 }
923
924 /// Output compare 2 fast enable
925 pub mod OC2FE {
926 /// Offset (10 bits)
927 pub const offset: u32 = 10;
928 /// Mask (1 bit: 1 << 10)
929 pub const mask: u32 = 1 << offset;
930 /// Read-only values (empty)
931 pub mod R {}
932 /// Write-only values (empty)
933 pub mod W {}
934 /// Read-write values (empty)
935 pub mod RW {}
936 }
937
938 /// Capture/Compare 2 selection
939 pub mod CC2S {
940 /// Offset (8 bits)
941 pub const offset: u32 = 8;
942 /// Mask (2 bits: 0b11 << 8)
943 pub const mask: u32 = 0b11 << offset;
944 /// Read-only values (empty)
945 pub mod R {}
946 /// Write-only values (empty)
947 pub mod W {}
948 /// Read-write values (empty)
949 pub mod RW {}
950 }
951
952 /// Output compare 1 clear enable
953 pub mod OC1CE {
954 /// Offset (7 bits)
955 pub const offset: u32 = 7;
956 /// Mask (1 bit: 1 << 7)
957 pub const mask: u32 = 1 << offset;
958 /// Read-only values (empty)
959 pub mod R {}
960 /// Write-only values (empty)
961 pub mod W {}
962 /// Read-write values (empty)
963 pub mod RW {}
964 }
965
966 /// Output compare 1 mode
967 pub mod OC1M {
968 /// Offset (4 bits)
969 pub const offset: u32 = 4;
970 /// Mask (3 bits: 0b111 << 4)
971 pub const mask: u32 = 0b111 << offset;
972 /// Read-only values (empty)
973 pub mod R {}
974 /// Write-only values (empty)
975 pub mod W {}
976 /// Read-write values
977 pub mod RW {
978
979 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
980 pub const Frozen: u32 = 0b000;
981
982 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
983 pub const ActiveOnMatch: u32 = 0b001;
984
985 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
986 pub const InactiveOnMatch: u32 = 0b010;
987
988 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
989 pub const Toggle: u32 = 0b011;
990
991 /// 0b100: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
992 pub const ForceInactive: u32 = 0b100;
993
994 /// 0b101: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
995 pub const ForceActive: u32 = 0b101;
996
997 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
998 pub const PwmMode1: u32 = 0b110;
999
1000 /// 0b111: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
1001 pub const PwmMode2: u32 = 0b111;
1002 }
1003 }
1004
1005 /// Output compare 1 preload enable
1006 pub mod OC1PE {
1007 /// Offset (3 bits)
1008 pub const offset: u32 = 3;
1009 /// Mask (1 bit: 1 << 3)
1010 pub const mask: u32 = 1 << offset;
1011 /// Read-only values (empty)
1012 pub mod R {}
1013 /// Write-only values (empty)
1014 pub mod W {}
1015 /// Read-write values (empty)
1016 pub mod RW {}
1017 }
1018
1019 /// Output compare 1 fast enable
1020 pub mod OC1FE {
1021 /// Offset (2 bits)
1022 pub const offset: u32 = 2;
1023 /// Mask (1 bit: 1 << 2)
1024 pub const mask: u32 = 1 << offset;
1025 /// Read-only values (empty)
1026 pub mod R {}
1027 /// Write-only values (empty)
1028 pub mod W {}
1029 /// Read-write values (empty)
1030 pub mod RW {}
1031 }
1032
1033 /// Capture/Compare 1 selection
1034 pub mod CC1S {
1035 /// Offset (0 bits)
1036 pub const offset: u32 = 0;
1037 /// Mask (2 bits: 0b11 << 0)
1038 pub const mask: u32 = 0b11 << offset;
1039 /// Read-only values (empty)
1040 pub mod R {}
1041 /// Write-only values (empty)
1042 pub mod W {}
1043 /// Read-write values (empty)
1044 pub mod RW {}
1045 }
1046
1047 /// Input capture 2 filter
1048 pub mod IC2F {
1049 /// Offset (12 bits)
1050 pub const offset: u32 = 12;
1051 /// Mask (4 bits: 0b1111 << 12)
1052 pub const mask: u32 = 0b1111 << offset;
1053 /// Read-only values (empty)
1054 pub mod R {}
1055 /// Write-only values (empty)
1056 pub mod W {}
1057 /// Read-write values (empty)
1058 pub mod RW {}
1059 }
1060
1061 /// Input capture 2 prescaler
1062 pub mod IC2PSC {
1063 /// Offset (10 bits)
1064 pub const offset: u32 = 10;
1065 /// Mask (2 bits: 0b11 << 10)
1066 pub const mask: u32 = 0b11 << offset;
1067 /// Read-only values (empty)
1068 pub mod R {}
1069 /// Write-only values (empty)
1070 pub mod W {}
1071 /// Read-write values (empty)
1072 pub mod RW {}
1073 }
1074
1075 /// Input capture 1 filter
1076 pub mod IC1F {
1077 /// Offset (4 bits)
1078 pub const offset: u32 = 4;
1079 /// Mask (4 bits: 0b1111 << 4)
1080 pub const mask: u32 = 0b1111 << offset;
1081 /// Read-only values (empty)
1082 pub mod R {}
1083 /// Write-only values (empty)
1084 pub mod W {}
1085 /// Read-write values (empty)
1086 pub mod RW {}
1087 }
1088
1089 /// Input capture 1 prescaler
1090 pub mod IC1PSC {
1091 /// Offset (2 bits)
1092 pub const offset: u32 = 2;
1093 /// Mask (2 bits: 0b11 << 2)
1094 pub const mask: u32 = 0b11 << offset;
1095 /// Read-only values (empty)
1096 pub mod R {}
1097 /// Write-only values (empty)
1098 pub mod W {}
1099 /// Read-write values (empty)
1100 pub mod RW {}
1101 }
1102}
1103
1104/// CCMR2_Output and CCMR2_Input
1105/// CCMR2_Output: capture/compare mode register 2 (output mode)
1106/// CCMR2_Input: capture/compare mode register 2 (input mode)
1107pub mod CCMR2 {
1108
1109 /// Output Compare 4 mode - bit 3
1110 pub mod OC4M_3 {
1111 /// Offset (24 bits)
1112 pub const offset: u32 = 24;
1113 /// Mask (1 bit: 1 << 24)
1114 pub const mask: u32 = 1 << offset;
1115 /// Read-only values (empty)
1116 pub mod R {}
1117 /// Write-only values (empty)
1118 pub mod W {}
1119 /// Read-write values
1120 pub mod RW {
1121
1122 /// 0b0: Normal output compare mode (modes 0-7)
1123 pub const Normal: u32 = 0b0;
1124
1125 /// 0b1: Extended output compare mode (modes 7-15)
1126 pub const Extended: u32 = 0b1;
1127 }
1128 }
1129
1130 /// Output Compare 3 mode - bit 3
1131 pub mod OC3M_3 {
1132 /// Offset (16 bits)
1133 pub const offset: u32 = 16;
1134 /// Mask (1 bit: 1 << 16)
1135 pub const mask: u32 = 1 << offset;
1136 /// Read-only values (empty)
1137 pub mod R {}
1138 /// Write-only values (empty)
1139 pub mod W {}
1140 pub use super::OC4M_3::RW;
1141 }
1142
1143 /// Output compare 4 clear enable
1144 pub mod OC4CE {
1145 /// Offset (15 bits)
1146 pub const offset: u32 = 15;
1147 /// Mask (1 bit: 1 << 15)
1148 pub const mask: u32 = 1 << offset;
1149 /// Read-only values (empty)
1150 pub mod R {}
1151 /// Write-only values (empty)
1152 pub mod W {}
1153 /// Read-write values (empty)
1154 pub mod RW {}
1155 }
1156
1157 /// Output compare 4 mode
1158 pub mod OC4M {
1159 /// Offset (12 bits)
1160 pub const offset: u32 = 12;
1161 /// Mask (3 bits: 0b111 << 12)
1162 pub const mask: u32 = 0b111 << offset;
1163 /// Read-only values (empty)
1164 pub mod R {}
1165 /// Write-only values (empty)
1166 pub mod W {}
1167 /// Read-write values
1168 pub mod RW {
1169
1170 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1171 pub const Frozen: u32 = 0b000;
1172
1173 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
1174 pub const ActiveOnMatch: u32 = 0b001;
1175
1176 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
1177 pub const InactiveOnMatch: u32 = 0b010;
1178
1179 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
1180 pub const Toggle: u32 = 0b011;
1181
1182 /// 0b100: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
1183 pub const ForceInactive: u32 = 0b100;
1184
1185 /// 0b101: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
1186 pub const ForceActive: u32 = 0b101;
1187
1188 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
1189 pub const PwmMode1: u32 = 0b110;
1190
1191 /// 0b111: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
1192 pub const PwmMode2: u32 = 0b111;
1193 }
1194 }
1195
1196 /// Output compare 4 preload enable
1197 pub mod OC4PE {
1198 /// Offset (11 bits)
1199 pub const offset: u32 = 11;
1200 /// Mask (1 bit: 1 << 11)
1201 pub const mask: u32 = 1 << offset;
1202 /// Read-only values (empty)
1203 pub mod R {}
1204 /// Write-only values (empty)
1205 pub mod W {}
1206 /// Read-write values (empty)
1207 pub mod RW {}
1208 }
1209
1210 /// Output compare 4 fast enable
1211 pub mod OC4FE {
1212 /// Offset (10 bits)
1213 pub const offset: u32 = 10;
1214 /// Mask (1 bit: 1 << 10)
1215 pub const mask: u32 = 1 << offset;
1216 /// Read-only values (empty)
1217 pub mod R {}
1218 /// Write-only values (empty)
1219 pub mod W {}
1220 /// Read-write values (empty)
1221 pub mod RW {}
1222 }
1223
1224 /// Capture/Compare 4 selection
1225 pub mod CC4S {
1226 /// Offset (8 bits)
1227 pub const offset: u32 = 8;
1228 /// Mask (2 bits: 0b11 << 8)
1229 pub const mask: u32 = 0b11 << offset;
1230 /// Read-only values (empty)
1231 pub mod R {}
1232 /// Write-only values (empty)
1233 pub mod W {}
1234 /// Read-write values (empty)
1235 pub mod RW {}
1236 }
1237
1238 /// Output compare 3 clear enable
1239 pub mod OC3CE {
1240 /// Offset (7 bits)
1241 pub const offset: u32 = 7;
1242 /// Mask (1 bit: 1 << 7)
1243 pub const mask: u32 = 1 << offset;
1244 /// Read-only values (empty)
1245 pub mod R {}
1246 /// Write-only values (empty)
1247 pub mod W {}
1248 /// Read-write values (empty)
1249 pub mod RW {}
1250 }
1251
1252 /// Output compare 3 mode
1253 pub mod OC3M {
1254 /// Offset (4 bits)
1255 pub const offset: u32 = 4;
1256 /// Mask (3 bits: 0b111 << 4)
1257 pub const mask: u32 = 0b111 << offset;
1258 /// Read-only values (empty)
1259 pub mod R {}
1260 /// Write-only values (empty)
1261 pub mod W {}
1262 pub use super::OC4M::RW;
1263 }
1264
1265 /// Output compare 3 preload enable
1266 pub mod OC3PE {
1267 /// Offset (3 bits)
1268 pub const offset: u32 = 3;
1269 /// Mask (1 bit: 1 << 3)
1270 pub const mask: u32 = 1 << offset;
1271 /// Read-only values (empty)
1272 pub mod R {}
1273 /// Write-only values (empty)
1274 pub mod W {}
1275 /// Read-write values (empty)
1276 pub mod RW {}
1277 }
1278
1279 /// Output compare 3 fast enable
1280 pub mod OC3FE {
1281 /// Offset (2 bits)
1282 pub const offset: u32 = 2;
1283 /// Mask (1 bit: 1 << 2)
1284 pub const mask: u32 = 1 << offset;
1285 /// Read-only values (empty)
1286 pub mod R {}
1287 /// Write-only values (empty)
1288 pub mod W {}
1289 /// Read-write values (empty)
1290 pub mod RW {}
1291 }
1292
1293 /// Capture/Compare 3 selection
1294 pub mod CC3S {
1295 /// Offset (0 bits)
1296 pub const offset: u32 = 0;
1297 /// Mask (2 bits: 0b11 << 0)
1298 pub const mask: u32 = 0b11 << offset;
1299 /// Read-only values (empty)
1300 pub mod R {}
1301 /// Write-only values (empty)
1302 pub mod W {}
1303 /// Read-write values (empty)
1304 pub mod RW {}
1305 }
1306
1307 /// Input capture 4 filter
1308 pub mod IC4F {
1309 /// Offset (12 bits)
1310 pub const offset: u32 = 12;
1311 /// Mask (4 bits: 0b1111 << 12)
1312 pub const mask: u32 = 0b1111 << offset;
1313 /// Read-only values (empty)
1314 pub mod R {}
1315 /// Write-only values (empty)
1316 pub mod W {}
1317 /// Read-write values (empty)
1318 pub mod RW {}
1319 }
1320
1321 /// Input capture 4 prescaler
1322 pub mod IC4PSC {
1323 /// Offset (10 bits)
1324 pub const offset: u32 = 10;
1325 /// Mask (2 bits: 0b11 << 10)
1326 pub const mask: u32 = 0b11 << offset;
1327 /// Read-only values (empty)
1328 pub mod R {}
1329 /// Write-only values (empty)
1330 pub mod W {}
1331 /// Read-write values (empty)
1332 pub mod RW {}
1333 }
1334
1335 /// Input capture 3 filter
1336 pub mod IC3F {
1337 /// Offset (4 bits)
1338 pub const offset: u32 = 4;
1339 /// Mask (4 bits: 0b1111 << 4)
1340 pub const mask: u32 = 0b1111 << offset;
1341 /// Read-only values (empty)
1342 pub mod R {}
1343 /// Write-only values (empty)
1344 pub mod W {}
1345 /// Read-write values (empty)
1346 pub mod RW {}
1347 }
1348
1349 /// Input capture 3 prescaler
1350 pub mod IC3PSC {
1351 /// Offset (2 bits)
1352 pub const offset: u32 = 2;
1353 /// Mask (2 bits: 0b11 << 2)
1354 pub const mask: u32 = 0b11 << offset;
1355 /// Read-only values (empty)
1356 pub mod R {}
1357 /// Write-only values (empty)
1358 pub mod W {}
1359 /// Read-write values (empty)
1360 pub mod RW {}
1361 }
1362}
1363
1364/// capture/compare enable register
1365pub mod CCER {
1366
1367 /// Capture/Compare 4 output Polarity
1368 pub mod CC4NP {
1369 /// Offset (15 bits)
1370 pub const offset: u32 = 15;
1371 /// Mask (1 bit: 1 << 15)
1372 pub const mask: u32 = 1 << offset;
1373 /// Read-only values (empty)
1374 pub mod R {}
1375 /// Write-only values (empty)
1376 pub mod W {}
1377 /// Read-write values (empty)
1378 pub mod RW {}
1379 }
1380
1381 /// Capture/Compare 3 output Polarity
1382 pub mod CC4P {
1383 /// Offset (13 bits)
1384 pub const offset: u32 = 13;
1385 /// Mask (1 bit: 1 << 13)
1386 pub const mask: u32 = 1 << offset;
1387 /// Read-only values (empty)
1388 pub mod R {}
1389 /// Write-only values (empty)
1390 pub mod W {}
1391 /// Read-write values (empty)
1392 pub mod RW {}
1393 }
1394
1395 /// Capture/Compare 4 output enable
1396 pub mod CC4E {
1397 /// Offset (12 bits)
1398 pub const offset: u32 = 12;
1399 /// Mask (1 bit: 1 << 12)
1400 pub const mask: u32 = 1 << offset;
1401 /// Read-only values (empty)
1402 pub mod R {}
1403 /// Write-only values (empty)
1404 pub mod W {}
1405 /// Read-write values (empty)
1406 pub mod RW {}
1407 }
1408
1409 /// Capture/Compare 3 output Polarity
1410 pub mod CC3NP {
1411 /// Offset (11 bits)
1412 pub const offset: u32 = 11;
1413 /// Mask (1 bit: 1 << 11)
1414 pub const mask: u32 = 1 << offset;
1415 /// Read-only values (empty)
1416 pub mod R {}
1417 /// Write-only values (empty)
1418 pub mod W {}
1419 /// Read-write values (empty)
1420 pub mod RW {}
1421 }
1422
1423 /// Capture/Compare 3 output Polarity
1424 pub mod CC3P {
1425 /// Offset (9 bits)
1426 pub const offset: u32 = 9;
1427 /// Mask (1 bit: 1 << 9)
1428 pub const mask: u32 = 1 << offset;
1429 /// Read-only values (empty)
1430 pub mod R {}
1431 /// Write-only values (empty)
1432 pub mod W {}
1433 /// Read-write values (empty)
1434 pub mod RW {}
1435 }
1436
1437 /// Capture/Compare 3 output enable
1438 pub mod CC3E {
1439 /// Offset (8 bits)
1440 pub const offset: u32 = 8;
1441 /// Mask (1 bit: 1 << 8)
1442 pub const mask: u32 = 1 << offset;
1443 /// Read-only values (empty)
1444 pub mod R {}
1445 /// Write-only values (empty)
1446 pub mod W {}
1447 /// Read-write values (empty)
1448 pub mod RW {}
1449 }
1450
1451 /// Capture/Compare 2 output Polarity
1452 pub mod CC2NP {
1453 /// Offset (7 bits)
1454 pub const offset: u32 = 7;
1455 /// Mask (1 bit: 1 << 7)
1456 pub const mask: u32 = 1 << offset;
1457 /// Read-only values (empty)
1458 pub mod R {}
1459 /// Write-only values (empty)
1460 pub mod W {}
1461 /// Read-write values (empty)
1462 pub mod RW {}
1463 }
1464
1465 /// Capture/Compare 2 output Polarity
1466 pub mod CC2P {
1467 /// Offset (5 bits)
1468 pub const offset: u32 = 5;
1469 /// Mask (1 bit: 1 << 5)
1470 pub const mask: u32 = 1 << offset;
1471 /// Read-only values (empty)
1472 pub mod R {}
1473 /// Write-only values (empty)
1474 pub mod W {}
1475 /// Read-write values (empty)
1476 pub mod RW {}
1477 }
1478
1479 /// Capture/Compare 2 output enable
1480 pub mod CC2E {
1481 /// Offset (4 bits)
1482 pub const offset: u32 = 4;
1483 /// Mask (1 bit: 1 << 4)
1484 pub const mask: u32 = 1 << offset;
1485 /// Read-only values (empty)
1486 pub mod R {}
1487 /// Write-only values (empty)
1488 pub mod W {}
1489 /// Read-write values (empty)
1490 pub mod RW {}
1491 }
1492
1493 /// Capture/Compare 1 output Polarity
1494 pub mod CC1NP {
1495 /// Offset (3 bits)
1496 pub const offset: u32 = 3;
1497 /// Mask (1 bit: 1 << 3)
1498 pub const mask: u32 = 1 << offset;
1499 /// Read-only values (empty)
1500 pub mod R {}
1501 /// Write-only values (empty)
1502 pub mod W {}
1503 /// Read-write values (empty)
1504 pub mod RW {}
1505 }
1506
1507 /// Capture/Compare 1 output Polarity
1508 pub mod CC1P {
1509 /// Offset (1 bits)
1510 pub const offset: u32 = 1;
1511 /// Mask (1 bit: 1 << 1)
1512 pub const mask: u32 = 1 << offset;
1513 /// Read-only values (empty)
1514 pub mod R {}
1515 /// Write-only values (empty)
1516 pub mod W {}
1517 /// Read-write values (empty)
1518 pub mod RW {}
1519 }
1520
1521 /// Capture/Compare 1 output enable
1522 pub mod CC1E {
1523 /// Offset (0 bits)
1524 pub const offset: u32 = 0;
1525 /// Mask (1 bit: 1 << 0)
1526 pub const mask: u32 = 1 << offset;
1527 /// Read-only values (empty)
1528 pub mod R {}
1529 /// Write-only values (empty)
1530 pub mod W {}
1531 /// Read-write values (empty)
1532 pub mod RW {}
1533 }
1534}
1535
1536/// counter
1537pub mod CNT {
1538
1539 /// High counter value (TIM2 only)
1540 pub mod CNT_H {
1541 /// Offset (16 bits)
1542 pub const offset: u32 = 16;
1543 /// Mask (16 bits: 0xffff << 16)
1544 pub const mask: u32 = 0xffff << offset;
1545 /// Read-only values (empty)
1546 pub mod R {}
1547 /// Write-only values (empty)
1548 pub mod W {}
1549 /// Read-write values (empty)
1550 pub mod RW {}
1551 }
1552
1553 /// Low counter value
1554 pub mod CNT_L {
1555 /// Offset (0 bits)
1556 pub const offset: u32 = 0;
1557 /// Mask (16 bits: 0xffff << 0)
1558 pub const mask: u32 = 0xffff << offset;
1559 /// Read-only values (empty)
1560 pub mod R {}
1561 /// Write-only values (empty)
1562 pub mod W {}
1563 /// Read-write values (empty)
1564 pub mod RW {}
1565 }
1566}
1567
1568/// prescaler
1569pub mod PSC {
1570
1571 /// Prescaler value
1572 pub mod PSC {
1573 /// Offset (0 bits)
1574 pub const offset: u32 = 0;
1575 /// Mask (16 bits: 0xffff << 0)
1576 pub const mask: u32 = 0xffff << offset;
1577 /// Read-only values (empty)
1578 pub mod R {}
1579 /// Write-only values (empty)
1580 pub mod W {}
1581 /// Read-write values (empty)
1582 pub mod RW {}
1583 }
1584}
1585
1586/// auto-reload register
1587pub mod ARR {
1588
1589 /// High Auto-reload value (TIM2 only)
1590 pub mod ARR_H {
1591 /// Offset (16 bits)
1592 pub const offset: u32 = 16;
1593 /// Mask (16 bits: 0xffff << 16)
1594 pub const mask: u32 = 0xffff << offset;
1595 /// Read-only values (empty)
1596 pub mod R {}
1597 /// Write-only values (empty)
1598 pub mod W {}
1599 /// Read-write values (empty)
1600 pub mod RW {}
1601 }
1602
1603 /// Low Auto-reload value
1604 pub mod ARR_L {
1605 /// Offset (0 bits)
1606 pub const offset: u32 = 0;
1607 /// Mask (16 bits: 0xffff << 0)
1608 pub const mask: u32 = 0xffff << offset;
1609 /// Read-only values (empty)
1610 pub mod R {}
1611 /// Write-only values (empty)
1612 pub mod W {}
1613 /// Read-write values (empty)
1614 pub mod RW {}
1615 }
1616}
1617
1618/// capture/compare register 1
1619pub mod CCR1 {
1620
1621 /// High Capture/Compare 1 value (TIM2 only)
1622 pub mod CCR1_H {
1623 /// Offset (16 bits)
1624 pub const offset: u32 = 16;
1625 /// Mask (16 bits: 0xffff << 16)
1626 pub const mask: u32 = 0xffff << offset;
1627 /// Read-only values (empty)
1628 pub mod R {}
1629 /// Write-only values (empty)
1630 pub mod W {}
1631 /// Read-write values (empty)
1632 pub mod RW {}
1633 }
1634
1635 /// Low Capture/Compare 1 value
1636 pub mod CCR1_L {
1637 /// Offset (0 bits)
1638 pub const offset: u32 = 0;
1639 /// Mask (16 bits: 0xffff << 0)
1640 pub const mask: u32 = 0xffff << offset;
1641 /// Read-only values (empty)
1642 pub mod R {}
1643 /// Write-only values (empty)
1644 pub mod W {}
1645 /// Read-write values (empty)
1646 pub mod RW {}
1647 }
1648}
1649
1650/// capture/compare register 2
1651pub mod CCR2 {
1652
1653 /// High Capture/Compare 2 value (TIM2 only)
1654 pub mod CCR2_H {
1655 /// Offset (16 bits)
1656 pub const offset: u32 = 16;
1657 /// Mask (16 bits: 0xffff << 16)
1658 pub const mask: u32 = 0xffff << offset;
1659 /// Read-only values (empty)
1660 pub mod R {}
1661 /// Write-only values (empty)
1662 pub mod W {}
1663 /// Read-write values (empty)
1664 pub mod RW {}
1665 }
1666
1667 /// Low Capture/Compare 2 value
1668 pub mod CCR2_L {
1669 /// Offset (0 bits)
1670 pub const offset: u32 = 0;
1671 /// Mask (16 bits: 0xffff << 0)
1672 pub const mask: u32 = 0xffff << offset;
1673 /// Read-only values (empty)
1674 pub mod R {}
1675 /// Write-only values (empty)
1676 pub mod W {}
1677 /// Read-write values (empty)
1678 pub mod RW {}
1679 }
1680}
1681
1682/// capture/compare register 3
1683pub mod CCR3 {
1684
1685 /// High Capture/Compare value (TIM2 only)
1686 pub mod CCR3_H {
1687 /// Offset (16 bits)
1688 pub const offset: u32 = 16;
1689 /// Mask (16 bits: 0xffff << 16)
1690 pub const mask: u32 = 0xffff << offset;
1691 /// Read-only values (empty)
1692 pub mod R {}
1693 /// Write-only values (empty)
1694 pub mod W {}
1695 /// Read-write values (empty)
1696 pub mod RW {}
1697 }
1698
1699 /// Low Capture/Compare value
1700 pub mod CCR3_L {
1701 /// Offset (0 bits)
1702 pub const offset: u32 = 0;
1703 /// Mask (16 bits: 0xffff << 0)
1704 pub const mask: u32 = 0xffff << offset;
1705 /// Read-only values (empty)
1706 pub mod R {}
1707 /// Write-only values (empty)
1708 pub mod W {}
1709 /// Read-write values (empty)
1710 pub mod RW {}
1711 }
1712}
1713
1714/// capture/compare register 4
1715pub mod CCR4 {
1716
1717 /// High Capture/Compare value (TIM2 only)
1718 pub mod CCR4_H {
1719 /// Offset (16 bits)
1720 pub const offset: u32 = 16;
1721 /// Mask (16 bits: 0xffff << 16)
1722 pub const mask: u32 = 0xffff << offset;
1723 /// Read-only values (empty)
1724 pub mod R {}
1725 /// Write-only values (empty)
1726 pub mod W {}
1727 /// Read-write values (empty)
1728 pub mod RW {}
1729 }
1730
1731 /// Low Capture/Compare value
1732 pub mod CCR4_L {
1733 /// Offset (0 bits)
1734 pub const offset: u32 = 0;
1735 /// Mask (16 bits: 0xffff << 0)
1736 pub const mask: u32 = 0xffff << offset;
1737 /// Read-only values (empty)
1738 pub mod R {}
1739 /// Write-only values (empty)
1740 pub mod W {}
1741 /// Read-write values (empty)
1742 pub mod RW {}
1743 }
1744}
1745
1746/// DMA control register
1747pub mod DCR {
1748
1749 /// DMA burst length
1750 pub mod DBL {
1751 /// Offset (8 bits)
1752 pub const offset: u32 = 8;
1753 /// Mask (5 bits: 0b11111 << 8)
1754 pub const mask: u32 = 0b11111 << offset;
1755 /// Read-only values (empty)
1756 pub mod R {}
1757 /// Write-only values (empty)
1758 pub mod W {}
1759 /// Read-write values (empty)
1760 pub mod RW {}
1761 }
1762
1763 /// DMA base address
1764 pub mod DBA {
1765 /// Offset (0 bits)
1766 pub const offset: u32 = 0;
1767 /// Mask (5 bits: 0b11111 << 0)
1768 pub const mask: u32 = 0b11111 << offset;
1769 /// Read-only values (empty)
1770 pub mod R {}
1771 /// Write-only values (empty)
1772 pub mod W {}
1773 /// Read-write values (empty)
1774 pub mod RW {}
1775 }
1776}
1777
1778/// DMA address for full transfer
1779pub mod DMAR {
1780
1781 /// DMA register for burst accesses
1782 pub mod DMAB {
1783 /// Offset (0 bits)
1784 pub const offset: u32 = 0;
1785 /// Mask (16 bits: 0xffff << 0)
1786 pub const mask: u32 = 0xffff << offset;
1787 /// Read-only values (empty)
1788 pub mod R {}
1789 /// Write-only values (empty)
1790 pub mod W {}
1791 /// Read-write values (empty)
1792 pub mod RW {}
1793 }
1794}
1795
1796/// TIM option register
1797pub mod OR1 {
1798
1799 /// IOCREF_CLR
1800 pub mod IOCREF_CLR {
1801 /// Offset (0 bits)
1802 pub const offset: u32 = 0;
1803 /// Mask (1 bit: 1 << 0)
1804 pub const mask: u32 = 1 << offset;
1805 /// Read-only values (empty)
1806 pub mod R {}
1807 /// Write-only values (empty)
1808 pub mod W {}
1809 /// Read-write values (empty)
1810 pub mod RW {}
1811 }
1812}
1813
1814/// TIM alternate function option register 1
1815pub mod AF1 {
1816
1817 /// External trigger source selection
1818 pub mod ETRSEL {
1819 /// Offset (14 bits)
1820 pub const offset: u32 = 14;
1821 /// Mask (4 bits: 0b1111 << 14)
1822 pub const mask: u32 = 0b1111 << offset;
1823 /// Read-only values (empty)
1824 pub mod R {}
1825 /// Write-only values (empty)
1826 pub mod W {}
1827 /// Read-write values (empty)
1828 pub mod RW {}
1829 }
1830}
1831
1832/// TIM alternate function option register 1
1833pub mod TISEL {
1834
1835 /// TI1SEL
1836 pub mod TI1SEL {
1837 /// Offset (0 bits)
1838 pub const offset: u32 = 0;
1839 /// Mask (4 bits: 0b1111 << 0)
1840 pub const mask: u32 = 0b1111 << offset;
1841 /// Read-only values (empty)
1842 pub mod R {}
1843 /// Write-only values (empty)
1844 pub mod W {}
1845 /// Read-write values (empty)
1846 pub mod RW {}
1847 }
1848
1849 /// TI2SEL
1850 pub mod TI2SEL {
1851 /// Offset (8 bits)
1852 pub const offset: u32 = 8;
1853 /// Mask (4 bits: 0b1111 << 8)
1854 pub const mask: u32 = 0b1111 << offset;
1855 /// Read-only values (empty)
1856 pub mod R {}
1857 /// Write-only values (empty)
1858 pub mod W {}
1859 /// Read-write values (empty)
1860 pub mod RW {}
1861 }
1862}
1863#[repr(C)]
1864pub struct RegisterBlock {
1865 /// control register 1
1866 pub CR1: RWRegister<u32>,
1867
1868 /// control register 2
1869 pub CR2: RWRegister<u32>,
1870
1871 /// slave mode control register
1872 pub SMCR: RWRegister<u32>,
1873
1874 /// DMA/Interrupt enable register
1875 pub DIER: RWRegister<u32>,
1876
1877 /// status register
1878 pub SR: RWRegister<u32>,
1879
1880 /// event generation register
1881 pub EGR: WORegister<u32>,
1882
1883 /// CCMR1_Output and CCMR1_Input
1884 /// CCMR1_Output: capture/compare mode register 1 (output mode)
1885 /// CCMR1_Input: capture/compare mode register 1 (input mode)
1886 pub CCMR1: RWRegister<u32>,
1887
1888 /// CCMR2_Output and CCMR2_Input
1889 /// CCMR2_Output: capture/compare mode register 2 (output mode)
1890 /// CCMR2_Input: capture/compare mode register 2 (input mode)
1891 pub CCMR2: RWRegister<u32>,
1892
1893 /// capture/compare enable register
1894 pub CCER: RWRegister<u32>,
1895
1896 /// counter
1897 pub CNT: RWRegister<u32>,
1898
1899 /// prescaler
1900 pub PSC: RWRegister<u32>,
1901
1902 /// auto-reload register
1903 pub ARR: RWRegister<u32>,
1904
1905 _reserved1: [u8; 4],
1906
1907 /// capture/compare register 1
1908 pub CCR1: RWRegister<u32>,
1909
1910 /// capture/compare register 2
1911 pub CCR2: RWRegister<u32>,
1912
1913 /// capture/compare register 3
1914 pub CCR3: RWRegister<u32>,
1915
1916 /// capture/compare register 4
1917 pub CCR4: RWRegister<u32>,
1918
1919 _reserved2: [u8; 4],
1920
1921 /// DMA control register
1922 pub DCR: RWRegister<u32>,
1923
1924 /// DMA address for full transfer
1925 pub DMAR: RWRegister<u32>,
1926
1927 /// TIM option register
1928 pub OR1: RWRegister<u32>,
1929
1930 _reserved3: [u8; 12],
1931
1932 /// TIM alternate function option register 1
1933 pub AF1: RWRegister<u32>,
1934
1935 _reserved4: [u8; 4],
1936
1937 /// TIM alternate function option register 1
1938 pub TISEL: RWRegister<u32>,
1939}
1940pub struct ResetValues {
1941 pub CR1: u32,
1942 pub CR2: u32,
1943 pub SMCR: u32,
1944 pub DIER: u32,
1945 pub SR: u32,
1946 pub EGR: u32,
1947 pub CCMR1: u32,
1948 pub CCMR2: u32,
1949 pub CCER: u32,
1950 pub CNT: u32,
1951 pub PSC: u32,
1952 pub ARR: u32,
1953 pub CCR1: u32,
1954 pub CCR2: u32,
1955 pub CCR3: u32,
1956 pub CCR4: u32,
1957 pub DCR: u32,
1958 pub DMAR: u32,
1959 pub OR1: u32,
1960 pub AF1: u32,
1961 pub TISEL: u32,
1962}
1963#[cfg(not(feature = "nosync"))]
1964pub struct Instance {
1965 pub(crate) addr: u32,
1966 pub(crate) _marker: PhantomData<*const RegisterBlock>,
1967}
1968#[cfg(not(feature = "nosync"))]
1969impl ::core::ops::Deref for Instance {
1970 type Target = RegisterBlock;
1971 #[inline(always)]
1972 fn deref(&self) -> &RegisterBlock {
1973 unsafe { &*(self.addr as *const _) }
1974 }
1975}
1976#[cfg(feature = "rtic")]
1977unsafe impl Send for Instance {}