stm32ral/stm32g0/peripherals/tamp_v1.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Tamper and backup registers
4//!
5//! Used by: stm32g030, stm32g031, stm32g041
6
7use crate::{RORegister, RWRegister, WORegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// control register 1
12pub mod CR1 {
13
14 /// TAMP1E
15 pub mod TAMP1E {
16 /// Offset (0 bits)
17 pub const offset: u32 = 0;
18 /// Mask (1 bit: 1 << 0)
19 pub const mask: u32 = 1 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values (empty)
25 pub mod RW {}
26 }
27
28 /// TAMP2E
29 pub mod TAMP2E {
30 /// Offset (1 bits)
31 pub const offset: u32 = 1;
32 /// Mask (1 bit: 1 << 1)
33 pub const mask: u32 = 1 << offset;
34 /// Read-only values (empty)
35 pub mod R {}
36 /// Write-only values (empty)
37 pub mod W {}
38 /// Read-write values (empty)
39 pub mod RW {}
40 }
41
42 /// ITAMP1E
43 pub mod ITAMP1E {
44 /// Offset (16 bits)
45 pub const offset: u32 = 16;
46 /// Mask (1 bit: 1 << 16)
47 pub const mask: u32 = 1 << offset;
48 /// Read-only values (empty)
49 pub mod R {}
50 /// Write-only values (empty)
51 pub mod W {}
52 /// Read-write values (empty)
53 pub mod RW {}
54 }
55
56 /// ITAMP3E
57 pub mod ITAMP3E {
58 /// Offset (18 bits)
59 pub const offset: u32 = 18;
60 /// Mask (1 bit: 1 << 18)
61 pub const mask: u32 = 1 << offset;
62 /// Read-only values (empty)
63 pub mod R {}
64 /// Write-only values (empty)
65 pub mod W {}
66 /// Read-write values (empty)
67 pub mod RW {}
68 }
69
70 /// ITAMP4E
71 pub mod ITAMP4E {
72 /// Offset (19 bits)
73 pub const offset: u32 = 19;
74 /// Mask (1 bit: 1 << 19)
75 pub const mask: u32 = 1 << offset;
76 /// Read-only values (empty)
77 pub mod R {}
78 /// Write-only values (empty)
79 pub mod W {}
80 /// Read-write values (empty)
81 pub mod RW {}
82 }
83
84 /// ITAMP5E
85 pub mod ITAMP5E {
86 /// Offset (20 bits)
87 pub const offset: u32 = 20;
88 /// Mask (1 bit: 1 << 20)
89 pub const mask: u32 = 1 << offset;
90 /// Read-only values (empty)
91 pub mod R {}
92 /// Write-only values (empty)
93 pub mod W {}
94 /// Read-write values (empty)
95 pub mod RW {}
96 }
97
98 /// ITAMP6E
99 pub mod ITAMP6E {
100 /// Offset (21 bits)
101 pub const offset: u32 = 21;
102 /// Mask (1 bit: 1 << 21)
103 pub const mask: u32 = 1 << offset;
104 /// Read-only values (empty)
105 pub mod R {}
106 /// Write-only values (empty)
107 pub mod W {}
108 /// Read-write values (empty)
109 pub mod RW {}
110 }
111}
112
113/// control register 2
114pub mod CR2 {
115
116 /// TAMP1NOER
117 pub mod TAMP1NOER {
118 /// Offset (0 bits)
119 pub const offset: u32 = 0;
120 /// Mask (1 bit: 1 << 0)
121 pub const mask: u32 = 1 << offset;
122 /// Read-only values (empty)
123 pub mod R {}
124 /// Write-only values (empty)
125 pub mod W {}
126 /// Read-write values (empty)
127 pub mod RW {}
128 }
129
130 /// TAMP2NOER
131 pub mod TAMP2NOER {
132 /// Offset (1 bits)
133 pub const offset: u32 = 1;
134 /// Mask (1 bit: 1 << 1)
135 pub const mask: u32 = 1 << offset;
136 /// Read-only values (empty)
137 pub mod R {}
138 /// Write-only values (empty)
139 pub mod W {}
140 /// Read-write values (empty)
141 pub mod RW {}
142 }
143
144 /// TAMP1MSK
145 pub mod TAMP1MSK {
146 /// Offset (16 bits)
147 pub const offset: u32 = 16;
148 /// Mask (1 bit: 1 << 16)
149 pub const mask: u32 = 1 << offset;
150 /// Read-only values (empty)
151 pub mod R {}
152 /// Write-only values (empty)
153 pub mod W {}
154 /// Read-write values (empty)
155 pub mod RW {}
156 }
157
158 /// TAMP2MSK
159 pub mod TAMP2MSK {
160 /// Offset (17 bits)
161 pub const offset: u32 = 17;
162 /// Mask (1 bit: 1 << 17)
163 pub const mask: u32 = 1 << offset;
164 /// Read-only values (empty)
165 pub mod R {}
166 /// Write-only values (empty)
167 pub mod W {}
168 /// Read-write values (empty)
169 pub mod RW {}
170 }
171
172 /// TAMP1TRG
173 pub mod TAMP1TRG {
174 /// Offset (24 bits)
175 pub const offset: u32 = 24;
176 /// Mask (1 bit: 1 << 24)
177 pub const mask: u32 = 1 << offset;
178 /// Read-only values (empty)
179 pub mod R {}
180 /// Write-only values (empty)
181 pub mod W {}
182 /// Read-write values (empty)
183 pub mod RW {}
184 }
185
186 /// TAMP2TRG
187 pub mod TAMP2TRG {
188 /// Offset (25 bits)
189 pub const offset: u32 = 25;
190 /// Mask (1 bit: 1 << 25)
191 pub const mask: u32 = 1 << offset;
192 /// Read-only values (empty)
193 pub mod R {}
194 /// Write-only values (empty)
195 pub mod W {}
196 /// Read-write values (empty)
197 pub mod RW {}
198 }
199}
200
201/// TAMP filter control register
202pub mod FLTCR {
203
204 /// TAMPFREQ
205 pub mod TAMPFREQ {
206 /// Offset (0 bits)
207 pub const offset: u32 = 0;
208 /// Mask (3 bits: 0b111 << 0)
209 pub const mask: u32 = 0b111 << offset;
210 /// Read-only values (empty)
211 pub mod R {}
212 /// Write-only values (empty)
213 pub mod W {}
214 /// Read-write values (empty)
215 pub mod RW {}
216 }
217
218 /// TAMPFLT
219 pub mod TAMPFLT {
220 /// Offset (3 bits)
221 pub const offset: u32 = 3;
222 /// Mask (2 bits: 0b11 << 3)
223 pub const mask: u32 = 0b11 << offset;
224 /// Read-only values (empty)
225 pub mod R {}
226 /// Write-only values (empty)
227 pub mod W {}
228 /// Read-write values (empty)
229 pub mod RW {}
230 }
231
232 /// TAMPPRCH
233 pub mod TAMPPRCH {
234 /// Offset (5 bits)
235 pub const offset: u32 = 5;
236 /// Mask (2 bits: 0b11 << 5)
237 pub const mask: u32 = 0b11 << offset;
238 /// Read-only values (empty)
239 pub mod R {}
240 /// Write-only values (empty)
241 pub mod W {}
242 /// Read-write values (empty)
243 pub mod RW {}
244 }
245
246 /// TAMPPUDIS
247 pub mod TAMPPUDIS {
248 /// Offset (7 bits)
249 pub const offset: u32 = 7;
250 /// Mask (1 bit: 1 << 7)
251 pub const mask: u32 = 1 << offset;
252 /// Read-only values (empty)
253 pub mod R {}
254 /// Write-only values (empty)
255 pub mod W {}
256 /// Read-write values (empty)
257 pub mod RW {}
258 }
259}
260
261/// TAMP interrupt enable register
262pub mod IER {
263
264 /// TAMP1IE
265 pub mod TAMP1IE {
266 /// Offset (0 bits)
267 pub const offset: u32 = 0;
268 /// Mask (1 bit: 1 << 0)
269 pub const mask: u32 = 1 << offset;
270 /// Read-only values (empty)
271 pub mod R {}
272 /// Write-only values (empty)
273 pub mod W {}
274 /// Read-write values (empty)
275 pub mod RW {}
276 }
277
278 /// TAMP2IE
279 pub mod TAMP2IE {
280 /// Offset (1 bits)
281 pub const offset: u32 = 1;
282 /// Mask (1 bit: 1 << 1)
283 pub const mask: u32 = 1 << offset;
284 /// Read-only values (empty)
285 pub mod R {}
286 /// Write-only values (empty)
287 pub mod W {}
288 /// Read-write values (empty)
289 pub mod RW {}
290 }
291
292 /// ITAMP1IE
293 pub mod ITAMP1IE {
294 /// Offset (16 bits)
295 pub const offset: u32 = 16;
296 /// Mask (1 bit: 1 << 16)
297 pub const mask: u32 = 1 << offset;
298 /// Read-only values (empty)
299 pub mod R {}
300 /// Write-only values (empty)
301 pub mod W {}
302 /// Read-write values (empty)
303 pub mod RW {}
304 }
305
306 /// ITAMP3IE
307 pub mod ITAMP3IE {
308 /// Offset (18 bits)
309 pub const offset: u32 = 18;
310 /// Mask (1 bit: 1 << 18)
311 pub const mask: u32 = 1 << offset;
312 /// Read-only values (empty)
313 pub mod R {}
314 /// Write-only values (empty)
315 pub mod W {}
316 /// Read-write values (empty)
317 pub mod RW {}
318 }
319
320 /// ITAMP4IE
321 pub mod ITAMP4IE {
322 /// Offset (19 bits)
323 pub const offset: u32 = 19;
324 /// Mask (1 bit: 1 << 19)
325 pub const mask: u32 = 1 << offset;
326 /// Read-only values (empty)
327 pub mod R {}
328 /// Write-only values (empty)
329 pub mod W {}
330 /// Read-write values (empty)
331 pub mod RW {}
332 }
333
334 /// ITAMP5IE
335 pub mod ITAMP5IE {
336 /// Offset (20 bits)
337 pub const offset: u32 = 20;
338 /// Mask (1 bit: 1 << 20)
339 pub const mask: u32 = 1 << offset;
340 /// Read-only values (empty)
341 pub mod R {}
342 /// Write-only values (empty)
343 pub mod W {}
344 /// Read-write values (empty)
345 pub mod RW {}
346 }
347
348 /// ITAMP6IE
349 pub mod ITAMP6IE {
350 /// Offset (21 bits)
351 pub const offset: u32 = 21;
352 /// Mask (1 bit: 1 << 21)
353 pub const mask: u32 = 1 << offset;
354 /// Read-only values (empty)
355 pub mod R {}
356 /// Write-only values (empty)
357 pub mod W {}
358 /// Read-write values (empty)
359 pub mod RW {}
360 }
361}
362
363/// TAMP status register
364pub mod SR {
365
366 /// TAMP1F
367 pub mod TAMP1F {
368 /// Offset (0 bits)
369 pub const offset: u32 = 0;
370 /// Mask (1 bit: 1 << 0)
371 pub const mask: u32 = 1 << offset;
372 /// Read-only values (empty)
373 pub mod R {}
374 /// Write-only values (empty)
375 pub mod W {}
376 /// Read-write values (empty)
377 pub mod RW {}
378 }
379
380 /// TAMP2F
381 pub mod TAMP2F {
382 /// Offset (1 bits)
383 pub const offset: u32 = 1;
384 /// Mask (1 bit: 1 << 1)
385 pub const mask: u32 = 1 << offset;
386 /// Read-only values (empty)
387 pub mod R {}
388 /// Write-only values (empty)
389 pub mod W {}
390 /// Read-write values (empty)
391 pub mod RW {}
392 }
393
394 /// ITAMP1F
395 pub mod ITAMP1F {
396 /// Offset (16 bits)
397 pub const offset: u32 = 16;
398 /// Mask (1 bit: 1 << 16)
399 pub const mask: u32 = 1 << offset;
400 /// Read-only values (empty)
401 pub mod R {}
402 /// Write-only values (empty)
403 pub mod W {}
404 /// Read-write values (empty)
405 pub mod RW {}
406 }
407
408 /// ITAMP3F
409 pub mod ITAMP3F {
410 /// Offset (18 bits)
411 pub const offset: u32 = 18;
412 /// Mask (1 bit: 1 << 18)
413 pub const mask: u32 = 1 << offset;
414 /// Read-only values (empty)
415 pub mod R {}
416 /// Write-only values (empty)
417 pub mod W {}
418 /// Read-write values (empty)
419 pub mod RW {}
420 }
421
422 /// ITAMP4F
423 pub mod ITAMP4F {
424 /// Offset (19 bits)
425 pub const offset: u32 = 19;
426 /// Mask (1 bit: 1 << 19)
427 pub const mask: u32 = 1 << offset;
428 /// Read-only values (empty)
429 pub mod R {}
430 /// Write-only values (empty)
431 pub mod W {}
432 /// Read-write values (empty)
433 pub mod RW {}
434 }
435
436 /// ITAMP5F
437 pub mod ITAMP5F {
438 /// Offset (20 bits)
439 pub const offset: u32 = 20;
440 /// Mask (1 bit: 1 << 20)
441 pub const mask: u32 = 1 << offset;
442 /// Read-only values (empty)
443 pub mod R {}
444 /// Write-only values (empty)
445 pub mod W {}
446 /// Read-write values (empty)
447 pub mod RW {}
448 }
449
450 /// ITAMP6F
451 pub mod ITAMP6F {
452 /// Offset (21 bits)
453 pub const offset: u32 = 21;
454 /// Mask (1 bit: 1 << 21)
455 pub const mask: u32 = 1 << offset;
456 /// Read-only values (empty)
457 pub mod R {}
458 /// Write-only values (empty)
459 pub mod W {}
460 /// Read-write values (empty)
461 pub mod RW {}
462 }
463
464 /// ITAMP7F
465 pub mod ITAMP7F {
466 /// Offset (22 bits)
467 pub const offset: u32 = 22;
468 /// Mask (1 bit: 1 << 22)
469 pub const mask: u32 = 1 << offset;
470 /// Read-only values (empty)
471 pub mod R {}
472 /// Write-only values (empty)
473 pub mod W {}
474 /// Read-write values (empty)
475 pub mod RW {}
476 }
477}
478
479/// TAMP masked interrupt status register
480pub mod MISR {
481
482 /// TAMP1MF:
483 pub mod TAMP1MF {
484 /// Offset (0 bits)
485 pub const offset: u32 = 0;
486 /// Mask (1 bit: 1 << 0)
487 pub const mask: u32 = 1 << offset;
488 /// Read-only values (empty)
489 pub mod R {}
490 /// Write-only values (empty)
491 pub mod W {}
492 /// Read-write values (empty)
493 pub mod RW {}
494 }
495
496 /// TAMP2MF
497 pub mod TAMP2MF {
498 /// Offset (1 bits)
499 pub const offset: u32 = 1;
500 /// Mask (1 bit: 1 << 1)
501 pub const mask: u32 = 1 << offset;
502 /// Read-only values (empty)
503 pub mod R {}
504 /// Write-only values (empty)
505 pub mod W {}
506 /// Read-write values (empty)
507 pub mod RW {}
508 }
509
510 /// ITAMP1MF
511 pub mod ITAMP1MF {
512 /// Offset (16 bits)
513 pub const offset: u32 = 16;
514 /// Mask (1 bit: 1 << 16)
515 pub const mask: u32 = 1 << offset;
516 /// Read-only values (empty)
517 pub mod R {}
518 /// Write-only values (empty)
519 pub mod W {}
520 /// Read-write values (empty)
521 pub mod RW {}
522 }
523
524 /// ITAMP3MF
525 pub mod ITAMP3MF {
526 /// Offset (18 bits)
527 pub const offset: u32 = 18;
528 /// Mask (1 bit: 1 << 18)
529 pub const mask: u32 = 1 << offset;
530 /// Read-only values (empty)
531 pub mod R {}
532 /// Write-only values (empty)
533 pub mod W {}
534 /// Read-write values (empty)
535 pub mod RW {}
536 }
537
538 /// ITAMP4MF
539 pub mod ITAMP4MF {
540 /// Offset (19 bits)
541 pub const offset: u32 = 19;
542 /// Mask (1 bit: 1 << 19)
543 pub const mask: u32 = 1 << offset;
544 /// Read-only values (empty)
545 pub mod R {}
546 /// Write-only values (empty)
547 pub mod W {}
548 /// Read-write values (empty)
549 pub mod RW {}
550 }
551
552 /// ITAMP5MF
553 pub mod ITAMP5MF {
554 /// Offset (20 bits)
555 pub const offset: u32 = 20;
556 /// Mask (1 bit: 1 << 20)
557 pub const mask: u32 = 1 << offset;
558 /// Read-only values (empty)
559 pub mod R {}
560 /// Write-only values (empty)
561 pub mod W {}
562 /// Read-write values (empty)
563 pub mod RW {}
564 }
565
566 /// ITAMP6MF
567 pub mod ITAMP6MF {
568 /// Offset (21 bits)
569 pub const offset: u32 = 21;
570 /// Mask (1 bit: 1 << 21)
571 pub const mask: u32 = 1 << offset;
572 /// Read-only values (empty)
573 pub mod R {}
574 /// Write-only values (empty)
575 pub mod W {}
576 /// Read-write values (empty)
577 pub mod RW {}
578 }
579}
580
581/// TAMP status clear register
582pub mod SCR {
583
584 /// CTAMP1F
585 pub mod CTAMP1F {
586 /// Offset (0 bits)
587 pub const offset: u32 = 0;
588 /// Mask (1 bit: 1 << 0)
589 pub const mask: u32 = 1 << offset;
590 /// Read-only values (empty)
591 pub mod R {}
592 /// Write-only values (empty)
593 pub mod W {}
594 /// Read-write values (empty)
595 pub mod RW {}
596 }
597
598 /// CTAMP2F
599 pub mod CTAMP2F {
600 /// Offset (1 bits)
601 pub const offset: u32 = 1;
602 /// Mask (1 bit: 1 << 1)
603 pub const mask: u32 = 1 << offset;
604 /// Read-only values (empty)
605 pub mod R {}
606 /// Write-only values (empty)
607 pub mod W {}
608 /// Read-write values (empty)
609 pub mod RW {}
610 }
611
612 /// CITAMP1F
613 pub mod CITAMP1F {
614 /// Offset (16 bits)
615 pub const offset: u32 = 16;
616 /// Mask (1 bit: 1 << 16)
617 pub const mask: u32 = 1 << offset;
618 /// Read-only values (empty)
619 pub mod R {}
620 /// Write-only values (empty)
621 pub mod W {}
622 /// Read-write values (empty)
623 pub mod RW {}
624 }
625
626 /// CITAMP3F
627 pub mod CITAMP3F {
628 /// Offset (18 bits)
629 pub const offset: u32 = 18;
630 /// Mask (1 bit: 1 << 18)
631 pub const mask: u32 = 1 << offset;
632 /// Read-only values (empty)
633 pub mod R {}
634 /// Write-only values (empty)
635 pub mod W {}
636 /// Read-write values (empty)
637 pub mod RW {}
638 }
639
640 /// CITAMP4F
641 pub mod CITAMP4F {
642 /// Offset (19 bits)
643 pub const offset: u32 = 19;
644 /// Mask (1 bit: 1 << 19)
645 pub const mask: u32 = 1 << offset;
646 /// Read-only values (empty)
647 pub mod R {}
648 /// Write-only values (empty)
649 pub mod W {}
650 /// Read-write values (empty)
651 pub mod RW {}
652 }
653
654 /// CITAMP5F
655 pub mod CITAMP5F {
656 /// Offset (20 bits)
657 pub const offset: u32 = 20;
658 /// Mask (1 bit: 1 << 20)
659 pub const mask: u32 = 1 << offset;
660 /// Read-only values (empty)
661 pub mod R {}
662 /// Write-only values (empty)
663 pub mod W {}
664 /// Read-write values (empty)
665 pub mod RW {}
666 }
667
668 /// CITAMP6F
669 pub mod CITAMP6F {
670 /// Offset (21 bits)
671 pub const offset: u32 = 21;
672 /// Mask (1 bit: 1 << 21)
673 pub const mask: u32 = 1 << offset;
674 /// Read-only values (empty)
675 pub mod R {}
676 /// Write-only values (empty)
677 pub mod W {}
678 /// Read-write values (empty)
679 pub mod RW {}
680 }
681
682 /// CITAMP7F
683 pub mod CITAMP7F {
684 /// Offset (22 bits)
685 pub const offset: u32 = 22;
686 /// Mask (1 bit: 1 << 22)
687 pub const mask: u32 = 1 << offset;
688 /// Read-only values (empty)
689 pub mod R {}
690 /// Write-only values (empty)
691 pub mod W {}
692 /// Read-write values (empty)
693 pub mod RW {}
694 }
695}
696
697/// TAMP backup register
698pub mod BKP0R {
699
700 /// BKP
701 pub mod BKP {
702 /// Offset (0 bits)
703 pub const offset: u32 = 0;
704 /// Mask (32 bits: 0xffffffff << 0)
705 pub const mask: u32 = 0xffffffff << offset;
706 /// Read-only values (empty)
707 pub mod R {}
708 /// Write-only values (empty)
709 pub mod W {}
710 /// Read-write values (empty)
711 pub mod RW {}
712 }
713}
714
715/// TAMP backup register
716pub mod BKP1R {
717 pub use super::BKP0R::BKP;
718}
719
720/// TAMP backup register
721pub mod BKP2R {
722 pub use super::BKP0R::BKP;
723}
724
725/// TAMP backup register
726pub mod BKP3R {
727 pub use super::BKP0R::BKP;
728}
729
730/// TAMP backup register
731pub mod BKP4R {
732 pub use super::BKP0R::BKP;
733}
734#[repr(C)]
735pub struct RegisterBlock {
736 /// control register 1
737 pub CR1: RWRegister<u32>,
738
739 /// control register 2
740 pub CR2: RWRegister<u32>,
741
742 _reserved1: [u8; 4],
743
744 /// TAMP filter control register
745 pub FLTCR: RWRegister<u32>,
746
747 _reserved2: [u8; 28],
748
749 /// TAMP interrupt enable register
750 pub IER: RWRegister<u32>,
751
752 /// TAMP status register
753 pub SR: RORegister<u32>,
754
755 /// TAMP masked interrupt status register
756 pub MISR: RORegister<u32>,
757
758 _reserved3: [u8; 4],
759
760 /// TAMP status clear register
761 pub SCR: WORegister<u32>,
762
763 _reserved4: [u8; 192],
764
765 /// TAMP backup register
766 pub BKP0R: RWRegister<u32>,
767
768 /// TAMP backup register
769 pub BKP1R: RWRegister<u32>,
770
771 /// TAMP backup register
772 pub BKP2R: RWRegister<u32>,
773
774 /// TAMP backup register
775 pub BKP3R: RWRegister<u32>,
776
777 /// TAMP backup register
778 pub BKP4R: RWRegister<u32>,
779}
780pub struct ResetValues {
781 pub CR1: u32,
782 pub CR2: u32,
783 pub FLTCR: u32,
784 pub IER: u32,
785 pub SR: u32,
786 pub MISR: u32,
787 pub SCR: u32,
788 pub BKP0R: u32,
789 pub BKP1R: u32,
790 pub BKP2R: u32,
791 pub BKP3R: u32,
792 pub BKP4R: u32,
793}
794#[cfg(not(feature = "nosync"))]
795pub struct Instance {
796 pub(crate) addr: u32,
797 pub(crate) _marker: PhantomData<*const RegisterBlock>,
798}
799#[cfg(not(feature = "nosync"))]
800impl ::core::ops::Deref for Instance {
801 type Target = RegisterBlock;
802 #[inline(always)]
803 fn deref(&self) -> &RegisterBlock {
804 unsafe { &*(self.addr as *const _) }
805 }
806}
807#[cfg(feature = "rtic")]
808unsafe impl Send for Instance {}