stm32ral/stm32g0/peripherals/pwr_v2.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Power control
4//!
5//! Used by: stm32g070, stm32g071, stm32g07x, stm32g081
6
7use crate::{RORegister, RWRegister, WORegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// Power control register 1
12pub mod CR1 {
13
14 /// Low-power run
15 pub mod LPR {
16 /// Offset (14 bits)
17 pub const offset: u32 = 14;
18 /// Mask (1 bit: 1 << 14)
19 pub const mask: u32 = 1 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values (empty)
25 pub mod RW {}
26 }
27
28 /// Voltage scaling range selection
29 pub mod VOS {
30 /// Offset (9 bits)
31 pub const offset: u32 = 9;
32 /// Mask (2 bits: 0b11 << 9)
33 pub const mask: u32 = 0b11 << offset;
34 /// Read-only values (empty)
35 pub mod R {}
36 /// Write-only values (empty)
37 pub mod W {}
38 /// Read-write values (empty)
39 pub mod RW {}
40 }
41
42 /// Disable backup domain write protection
43 pub mod DBP {
44 /// Offset (8 bits)
45 pub const offset: u32 = 8;
46 /// Mask (1 bit: 1 << 8)
47 pub const mask: u32 = 1 << offset;
48 /// Read-only values (empty)
49 pub mod R {}
50 /// Write-only values (empty)
51 pub mod W {}
52 /// Read-write values (empty)
53 pub mod RW {}
54 }
55
56 /// Flash memory powered down during Low-power sleep mode
57 pub mod FPD_LPSLP {
58 /// Offset (5 bits)
59 pub const offset: u32 = 5;
60 /// Mask (1 bit: 1 << 5)
61 pub const mask: u32 = 1 << offset;
62 /// Read-only values (empty)
63 pub mod R {}
64 /// Write-only values (empty)
65 pub mod W {}
66 /// Read-write values (empty)
67 pub mod RW {}
68 }
69
70 /// Flash memory powered down during Low-power run mode
71 pub mod FPD_LPRUN {
72 /// Offset (4 bits)
73 pub const offset: u32 = 4;
74 /// Mask (1 bit: 1 << 4)
75 pub const mask: u32 = 1 << offset;
76 /// Read-only values (empty)
77 pub mod R {}
78 /// Write-only values (empty)
79 pub mod W {}
80 /// Read-write values (empty)
81 pub mod RW {}
82 }
83
84 /// Flash memory powered down during Stop mode
85 pub mod FPD_STOP {
86 /// Offset (3 bits)
87 pub const offset: u32 = 3;
88 /// Mask (1 bit: 1 << 3)
89 pub const mask: u32 = 1 << offset;
90 /// Read-only values (empty)
91 pub mod R {}
92 /// Write-only values (empty)
93 pub mod W {}
94 /// Read-write values (empty)
95 pub mod RW {}
96 }
97
98 /// Low-power mode selection
99 pub mod LPMS {
100 /// Offset (0 bits)
101 pub const offset: u32 = 0;
102 /// Mask (3 bits: 0b111 << 0)
103 pub const mask: u32 = 0b111 << offset;
104 /// Read-only values (empty)
105 pub mod R {}
106 /// Write-only values (empty)
107 pub mod W {}
108 /// Read-write values (empty)
109 pub mod RW {}
110 }
111}
112
113/// Power control register 2
114pub mod CR2 {
115
116 /// Power voltage detector enable
117 pub mod PVDE {
118 /// Offset (0 bits)
119 pub const offset: u32 = 0;
120 /// Mask (1 bit: 1 << 0)
121 pub const mask: u32 = 1 << offset;
122 /// Read-only values (empty)
123 pub mod R {}
124 /// Write-only values (empty)
125 pub mod W {}
126 /// Read-write values (empty)
127 pub mod RW {}
128 }
129
130 /// Power voltage detector falling threshold selection
131 pub mod PVDFT {
132 /// Offset (1 bits)
133 pub const offset: u32 = 1;
134 /// Mask (3 bits: 0b111 << 1)
135 pub const mask: u32 = 0b111 << offset;
136 /// Read-only values (empty)
137 pub mod R {}
138 /// Write-only values (empty)
139 pub mod W {}
140 /// Read-write values (empty)
141 pub mod RW {}
142 }
143
144 /// Power voltage detector rising threshold selection
145 pub mod PVDRT {
146 /// Offset (4 bits)
147 pub const offset: u32 = 4;
148 /// Mask (3 bits: 0b111 << 4)
149 pub const mask: u32 = 0b111 << offset;
150 /// Read-only values (empty)
151 pub mod R {}
152 /// Write-only values (empty)
153 pub mod W {}
154 /// Read-write values (empty)
155 pub mod RW {}
156 }
157}
158
159/// Power control register 3
160pub mod CR3 {
161
162 /// Enable Wakeup pin WKUP1
163 pub mod EWUP1 {
164 /// Offset (0 bits)
165 pub const offset: u32 = 0;
166 /// Mask (1 bit: 1 << 0)
167 pub const mask: u32 = 1 << offset;
168 /// Read-only values (empty)
169 pub mod R {}
170 /// Write-only values (empty)
171 pub mod W {}
172 /// Read-write values (empty)
173 pub mod RW {}
174 }
175
176 /// Enable Wakeup pin WKUP2
177 pub mod EWUP2 {
178 /// Offset (1 bits)
179 pub const offset: u32 = 1;
180 /// Mask (1 bit: 1 << 1)
181 pub const mask: u32 = 1 << offset;
182 /// Read-only values (empty)
183 pub mod R {}
184 /// Write-only values (empty)
185 pub mod W {}
186 /// Read-write values (empty)
187 pub mod RW {}
188 }
189
190 /// Enable Wakeup pin WKUP4
191 pub mod EWUP4 {
192 /// Offset (3 bits)
193 pub const offset: u32 = 3;
194 /// Mask (1 bit: 1 << 3)
195 pub const mask: u32 = 1 << offset;
196 /// Read-only values (empty)
197 pub mod R {}
198 /// Write-only values (empty)
199 pub mod W {}
200 /// Read-write values (empty)
201 pub mod RW {}
202 }
203
204 /// Enable WKUP5 wakeup pin
205 pub mod EWUP5 {
206 /// Offset (4 bits)
207 pub const offset: u32 = 4;
208 /// Mask (1 bit: 1 << 4)
209 pub const mask: u32 = 1 << offset;
210 /// Read-only values (empty)
211 pub mod R {}
212 /// Write-only values (empty)
213 pub mod W {}
214 /// Read-write values (empty)
215 pub mod RW {}
216 }
217
218 /// Enable WKUP6 wakeup pin
219 pub mod EWUP6 {
220 /// Offset (5 bits)
221 pub const offset: u32 = 5;
222 /// Mask (1 bit: 1 << 5)
223 pub const mask: u32 = 1 << offset;
224 /// Read-only values (empty)
225 pub mod R {}
226 /// Write-only values (empty)
227 pub mod W {}
228 /// Read-write values (empty)
229 pub mod RW {}
230 }
231
232 /// SRAM retention in Standby mode
233 pub mod RRS {
234 /// Offset (8 bits)
235 pub const offset: u32 = 8;
236 /// Mask (1 bit: 1 << 8)
237 pub const mask: u32 = 1 << offset;
238 /// Read-only values (empty)
239 pub mod R {}
240 /// Write-only values (empty)
241 pub mod W {}
242 /// Read-write values (empty)
243 pub mod RW {}
244 }
245
246 /// Enable the periodical sampling mode for PDR detection
247 pub mod ULPEN {
248 /// Offset (9 bits)
249 pub const offset: u32 = 9;
250 /// Mask (1 bit: 1 << 9)
251 pub const mask: u32 = 1 << offset;
252 /// Read-only values (empty)
253 pub mod R {}
254 /// Write-only values (empty)
255 pub mod W {}
256 /// Read-write values (empty)
257 pub mod RW {}
258 }
259
260 /// Apply pull-up and pull-down configuration
261 pub mod APC {
262 /// Offset (10 bits)
263 pub const offset: u32 = 10;
264 /// Mask (1 bit: 1 << 10)
265 pub const mask: u32 = 1 << offset;
266 /// Read-only values (empty)
267 pub mod R {}
268 /// Write-only values (empty)
269 pub mod W {}
270 /// Read-write values (empty)
271 pub mod RW {}
272 }
273
274 /// Enable internal wakeup line
275 pub mod EIWUL {
276 /// Offset (15 bits)
277 pub const offset: u32 = 15;
278 /// Mask (1 bit: 1 << 15)
279 pub const mask: u32 = 1 << offset;
280 /// Read-only values (empty)
281 pub mod R {}
282 /// Write-only values (empty)
283 pub mod W {}
284 /// Read-write values (empty)
285 pub mod RW {}
286 }
287}
288
289/// Power control register 4
290pub mod CR4 {
291
292 /// Wakeup pin WKUP1 polarity
293 pub mod WP1 {
294 /// Offset (0 bits)
295 pub const offset: u32 = 0;
296 /// Mask (1 bit: 1 << 0)
297 pub const mask: u32 = 1 << offset;
298 /// Read-only values (empty)
299 pub mod R {}
300 /// Write-only values (empty)
301 pub mod W {}
302 /// Read-write values (empty)
303 pub mod RW {}
304 }
305
306 /// Wakeup pin WKUP2 polarity
307 pub mod WP2 {
308 /// Offset (1 bits)
309 pub const offset: u32 = 1;
310 /// Mask (1 bit: 1 << 1)
311 pub const mask: u32 = 1 << offset;
312 /// Read-only values (empty)
313 pub mod R {}
314 /// Write-only values (empty)
315 pub mod W {}
316 /// Read-write values (empty)
317 pub mod RW {}
318 }
319
320 /// Wakeup pin WKUP4 polarity
321 pub mod WP4 {
322 /// Offset (3 bits)
323 pub const offset: u32 = 3;
324 /// Mask (1 bit: 1 << 3)
325 pub const mask: u32 = 1 << offset;
326 /// Read-only values (empty)
327 pub mod R {}
328 /// Write-only values (empty)
329 pub mod W {}
330 /// Read-write values (empty)
331 pub mod RW {}
332 }
333
334 /// Wakeup pin WKUP5 polarity
335 pub mod WP5 {
336 /// Offset (4 bits)
337 pub const offset: u32 = 4;
338 /// Mask (1 bit: 1 << 4)
339 pub const mask: u32 = 1 << offset;
340 /// Read-only values (empty)
341 pub mod R {}
342 /// Write-only values (empty)
343 pub mod W {}
344 /// Read-write values (empty)
345 pub mod RW {}
346 }
347
348 /// WKUP6 wakeup pin polarity
349 pub mod WP6 {
350 /// Offset (5 bits)
351 pub const offset: u32 = 5;
352 /// Mask (1 bit: 1 << 5)
353 pub const mask: u32 = 1 << offset;
354 /// Read-only values (empty)
355 pub mod R {}
356 /// Write-only values (empty)
357 pub mod W {}
358 /// Read-write values (empty)
359 pub mod RW {}
360 }
361
362 /// VBAT battery charging enable
363 pub mod VBE {
364 /// Offset (8 bits)
365 pub const offset: u32 = 8;
366 /// Mask (1 bit: 1 << 8)
367 pub const mask: u32 = 1 << offset;
368 /// Read-only values (empty)
369 pub mod R {}
370 /// Write-only values (empty)
371 pub mod W {}
372 /// Read-write values (empty)
373 pub mod RW {}
374 }
375
376 /// VBAT battery charging resistor selection
377 pub mod VBRS {
378 /// Offset (9 bits)
379 pub const offset: u32 = 9;
380 /// Mask (1 bit: 1 << 9)
381 pub const mask: u32 = 1 << offset;
382 /// Read-only values (empty)
383 pub mod R {}
384 /// Write-only values (empty)
385 pub mod W {}
386 /// Read-write values (empty)
387 pub mod RW {}
388 }
389}
390
391/// Power status register 1
392pub mod SR1 {
393
394 /// Wakeup flag 1
395 pub mod WUF1 {
396 /// Offset (0 bits)
397 pub const offset: u32 = 0;
398 /// Mask (1 bit: 1 << 0)
399 pub const mask: u32 = 1 << offset;
400 /// Read-only values (empty)
401 pub mod R {}
402 /// Write-only values (empty)
403 pub mod W {}
404 /// Read-write values (empty)
405 pub mod RW {}
406 }
407
408 /// Wakeup flag 2
409 pub mod WUF2 {
410 /// Offset (1 bits)
411 pub const offset: u32 = 1;
412 /// Mask (1 bit: 1 << 1)
413 pub const mask: u32 = 1 << offset;
414 /// Read-only values (empty)
415 pub mod R {}
416 /// Write-only values (empty)
417 pub mod W {}
418 /// Read-write values (empty)
419 pub mod RW {}
420 }
421
422 /// Wakeup flag 4
423 pub mod WUF4 {
424 /// Offset (3 bits)
425 pub const offset: u32 = 3;
426 /// Mask (1 bit: 1 << 3)
427 pub const mask: u32 = 1 << offset;
428 /// Read-only values (empty)
429 pub mod R {}
430 /// Write-only values (empty)
431 pub mod W {}
432 /// Read-write values (empty)
433 pub mod RW {}
434 }
435
436 /// Wakeup flag 5
437 pub mod WUF5 {
438 /// Offset (4 bits)
439 pub const offset: u32 = 4;
440 /// Mask (1 bit: 1 << 4)
441 pub const mask: u32 = 1 << offset;
442 /// Read-only values (empty)
443 pub mod R {}
444 /// Write-only values (empty)
445 pub mod W {}
446 /// Read-write values (empty)
447 pub mod RW {}
448 }
449
450 /// Wakeup flag 6
451 pub mod WUF6 {
452 /// Offset (5 bits)
453 pub const offset: u32 = 5;
454 /// Mask (1 bit: 1 << 5)
455 pub const mask: u32 = 1 << offset;
456 /// Read-only values (empty)
457 pub mod R {}
458 /// Write-only values (empty)
459 pub mod W {}
460 /// Read-write values (empty)
461 pub mod RW {}
462 }
463
464 /// Standby flag
465 pub mod SBF {
466 /// Offset (8 bits)
467 pub const offset: u32 = 8;
468 /// Mask (1 bit: 1 << 8)
469 pub const mask: u32 = 1 << offset;
470 /// Read-only values (empty)
471 pub mod R {}
472 /// Write-only values (empty)
473 pub mod W {}
474 /// Read-write values (empty)
475 pub mod RW {}
476 }
477
478 /// Wakeup flag internal
479 pub mod WUFI {
480 /// Offset (15 bits)
481 pub const offset: u32 = 15;
482 /// Mask (1 bit: 1 << 15)
483 pub const mask: u32 = 1 << offset;
484 /// Read-only values (empty)
485 pub mod R {}
486 /// Write-only values (empty)
487 pub mod W {}
488 /// Read-write values (empty)
489 pub mod RW {}
490 }
491}
492
493/// Power status register 2
494pub mod SR2 {
495
496 /// Power voltage detector output
497 pub mod PVDO {
498 /// Offset (11 bits)
499 pub const offset: u32 = 11;
500 /// Mask (1 bit: 1 << 11)
501 pub const mask: u32 = 1 << offset;
502 /// Read-only values (empty)
503 pub mod R {}
504 /// Write-only values (empty)
505 pub mod W {}
506 /// Read-write values (empty)
507 pub mod RW {}
508 }
509
510 /// Voltage scaling flag
511 pub mod VOSF {
512 /// Offset (10 bits)
513 pub const offset: u32 = 10;
514 /// Mask (1 bit: 1 << 10)
515 pub const mask: u32 = 1 << offset;
516 /// Read-only values (empty)
517 pub mod R {}
518 /// Write-only values (empty)
519 pub mod W {}
520 /// Read-write values (empty)
521 pub mod RW {}
522 }
523
524 /// Low-power regulator flag
525 pub mod REGLPF {
526 /// Offset (9 bits)
527 pub const offset: u32 = 9;
528 /// Mask (1 bit: 1 << 9)
529 pub const mask: u32 = 1 << offset;
530 /// Read-only values (empty)
531 pub mod R {}
532 /// Write-only values (empty)
533 pub mod W {}
534 /// Read-write values (empty)
535 pub mod RW {}
536 }
537
538 /// Low-power regulator started
539 pub mod REGLPS {
540 /// Offset (8 bits)
541 pub const offset: u32 = 8;
542 /// Mask (1 bit: 1 << 8)
543 pub const mask: u32 = 1 << offset;
544 /// Read-only values (empty)
545 pub mod R {}
546 /// Write-only values (empty)
547 pub mod W {}
548 /// Read-write values (empty)
549 pub mod RW {}
550 }
551
552 /// Flash ready flag
553 pub mod FLASH_RDY {
554 /// Offset (7 bits)
555 pub const offset: u32 = 7;
556 /// Mask (1 bit: 1 << 7)
557 pub const mask: u32 = 1 << offset;
558 /// Read-only values (empty)
559 pub mod R {}
560 /// Write-only values (empty)
561 pub mod W {}
562 /// Read-write values (empty)
563 pub mod RW {}
564 }
565}
566
567/// Power status clear register
568pub mod SCR {
569
570 /// Clear standby flag
571 pub mod CSBF {
572 /// Offset (8 bits)
573 pub const offset: u32 = 8;
574 /// Mask (1 bit: 1 << 8)
575 pub const mask: u32 = 1 << offset;
576 /// Read-only values (empty)
577 pub mod R {}
578 /// Write-only values (empty)
579 pub mod W {}
580 /// Read-write values (empty)
581 pub mod RW {}
582 }
583
584 /// Clear wakeup flag 6
585 pub mod CWUF6 {
586 /// Offset (5 bits)
587 pub const offset: u32 = 5;
588 /// Mask (1 bit: 1 << 5)
589 pub const mask: u32 = 1 << offset;
590 /// Read-only values (empty)
591 pub mod R {}
592 /// Write-only values (empty)
593 pub mod W {}
594 /// Read-write values (empty)
595 pub mod RW {}
596 }
597
598 /// Clear wakeup flag 5
599 pub mod CWUF5 {
600 /// Offset (4 bits)
601 pub const offset: u32 = 4;
602 /// Mask (1 bit: 1 << 4)
603 pub const mask: u32 = 1 << offset;
604 /// Read-only values (empty)
605 pub mod R {}
606 /// Write-only values (empty)
607 pub mod W {}
608 /// Read-write values (empty)
609 pub mod RW {}
610 }
611
612 /// Clear wakeup flag 4
613 pub mod CWUF4 {
614 /// Offset (3 bits)
615 pub const offset: u32 = 3;
616 /// Mask (1 bit: 1 << 3)
617 pub const mask: u32 = 1 << offset;
618 /// Read-only values (empty)
619 pub mod R {}
620 /// Write-only values (empty)
621 pub mod W {}
622 /// Read-write values (empty)
623 pub mod RW {}
624 }
625
626 /// Clear wakeup flag 2
627 pub mod CWUF2 {
628 /// Offset (1 bits)
629 pub const offset: u32 = 1;
630 /// Mask (1 bit: 1 << 1)
631 pub const mask: u32 = 1 << offset;
632 /// Read-only values (empty)
633 pub mod R {}
634 /// Write-only values (empty)
635 pub mod W {}
636 /// Read-write values (empty)
637 pub mod RW {}
638 }
639
640 /// Clear wakeup flag 1
641 pub mod CWUF1 {
642 /// Offset (0 bits)
643 pub const offset: u32 = 0;
644 /// Mask (1 bit: 1 << 0)
645 pub const mask: u32 = 1 << offset;
646 /// Read-only values (empty)
647 pub mod R {}
648 /// Write-only values (empty)
649 pub mod W {}
650 /// Read-write values (empty)
651 pub mod RW {}
652 }
653}
654
655/// Power Port A pull-up control register
656pub mod PUCRA {
657
658 /// Port A pull-up bit y (y=0..15)
659 pub mod PU15 {
660 /// Offset (15 bits)
661 pub const offset: u32 = 15;
662 /// Mask (1 bit: 1 << 15)
663 pub const mask: u32 = 1 << offset;
664 /// Read-only values (empty)
665 pub mod R {}
666 /// Write-only values (empty)
667 pub mod W {}
668 /// Read-write values (empty)
669 pub mod RW {}
670 }
671
672 /// Port A pull-up bit y (y=0..15)
673 pub mod PU14 {
674 /// Offset (14 bits)
675 pub const offset: u32 = 14;
676 /// Mask (1 bit: 1 << 14)
677 pub const mask: u32 = 1 << offset;
678 /// Read-only values (empty)
679 pub mod R {}
680 /// Write-only values (empty)
681 pub mod W {}
682 /// Read-write values (empty)
683 pub mod RW {}
684 }
685
686 /// Port A pull-up bit y (y=0..15)
687 pub mod PU13 {
688 /// Offset (13 bits)
689 pub const offset: u32 = 13;
690 /// Mask (1 bit: 1 << 13)
691 pub const mask: u32 = 1 << offset;
692 /// Read-only values (empty)
693 pub mod R {}
694 /// Write-only values (empty)
695 pub mod W {}
696 /// Read-write values (empty)
697 pub mod RW {}
698 }
699
700 /// Port A pull-up bit y (y=0..15)
701 pub mod PU12 {
702 /// Offset (12 bits)
703 pub const offset: u32 = 12;
704 /// Mask (1 bit: 1 << 12)
705 pub const mask: u32 = 1 << offset;
706 /// Read-only values (empty)
707 pub mod R {}
708 /// Write-only values (empty)
709 pub mod W {}
710 /// Read-write values (empty)
711 pub mod RW {}
712 }
713
714 /// Port A pull-up bit y (y=0..15)
715 pub mod PU11 {
716 /// Offset (11 bits)
717 pub const offset: u32 = 11;
718 /// Mask (1 bit: 1 << 11)
719 pub const mask: u32 = 1 << offset;
720 /// Read-only values (empty)
721 pub mod R {}
722 /// Write-only values (empty)
723 pub mod W {}
724 /// Read-write values (empty)
725 pub mod RW {}
726 }
727
728 /// Port A pull-up bit y (y=0..15)
729 pub mod PU10 {
730 /// Offset (10 bits)
731 pub const offset: u32 = 10;
732 /// Mask (1 bit: 1 << 10)
733 pub const mask: u32 = 1 << offset;
734 /// Read-only values (empty)
735 pub mod R {}
736 /// Write-only values (empty)
737 pub mod W {}
738 /// Read-write values (empty)
739 pub mod RW {}
740 }
741
742 /// Port A pull-up bit y (y=0..15)
743 pub mod PU9 {
744 /// Offset (9 bits)
745 pub const offset: u32 = 9;
746 /// Mask (1 bit: 1 << 9)
747 pub const mask: u32 = 1 << offset;
748 /// Read-only values (empty)
749 pub mod R {}
750 /// Write-only values (empty)
751 pub mod W {}
752 /// Read-write values (empty)
753 pub mod RW {}
754 }
755
756 /// Port A pull-up bit y (y=0..15)
757 pub mod PU8 {
758 /// Offset (8 bits)
759 pub const offset: u32 = 8;
760 /// Mask (1 bit: 1 << 8)
761 pub const mask: u32 = 1 << offset;
762 /// Read-only values (empty)
763 pub mod R {}
764 /// Write-only values (empty)
765 pub mod W {}
766 /// Read-write values (empty)
767 pub mod RW {}
768 }
769
770 /// Port A pull-up bit y (y=0..15)
771 pub mod PU7 {
772 /// Offset (7 bits)
773 pub const offset: u32 = 7;
774 /// Mask (1 bit: 1 << 7)
775 pub const mask: u32 = 1 << offset;
776 /// Read-only values (empty)
777 pub mod R {}
778 /// Write-only values (empty)
779 pub mod W {}
780 /// Read-write values (empty)
781 pub mod RW {}
782 }
783
784 /// Port A pull-up bit y (y=0..15)
785 pub mod PU6 {
786 /// Offset (6 bits)
787 pub const offset: u32 = 6;
788 /// Mask (1 bit: 1 << 6)
789 pub const mask: u32 = 1 << offset;
790 /// Read-only values (empty)
791 pub mod R {}
792 /// Write-only values (empty)
793 pub mod W {}
794 /// Read-write values (empty)
795 pub mod RW {}
796 }
797
798 /// Port A pull-up bit y (y=0..15)
799 pub mod PU5 {
800 /// Offset (5 bits)
801 pub const offset: u32 = 5;
802 /// Mask (1 bit: 1 << 5)
803 pub const mask: u32 = 1 << offset;
804 /// Read-only values (empty)
805 pub mod R {}
806 /// Write-only values (empty)
807 pub mod W {}
808 /// Read-write values (empty)
809 pub mod RW {}
810 }
811
812 /// Port A pull-up bit y (y=0..15)
813 pub mod PU4 {
814 /// Offset (4 bits)
815 pub const offset: u32 = 4;
816 /// Mask (1 bit: 1 << 4)
817 pub const mask: u32 = 1 << offset;
818 /// Read-only values (empty)
819 pub mod R {}
820 /// Write-only values (empty)
821 pub mod W {}
822 /// Read-write values (empty)
823 pub mod RW {}
824 }
825
826 /// Port A pull-up bit y (y=0..15)
827 pub mod PU3 {
828 /// Offset (3 bits)
829 pub const offset: u32 = 3;
830 /// Mask (1 bit: 1 << 3)
831 pub const mask: u32 = 1 << offset;
832 /// Read-only values (empty)
833 pub mod R {}
834 /// Write-only values (empty)
835 pub mod W {}
836 /// Read-write values (empty)
837 pub mod RW {}
838 }
839
840 /// Port A pull-up bit y (y=0..15)
841 pub mod PU2 {
842 /// Offset (2 bits)
843 pub const offset: u32 = 2;
844 /// Mask (1 bit: 1 << 2)
845 pub const mask: u32 = 1 << offset;
846 /// Read-only values (empty)
847 pub mod R {}
848 /// Write-only values (empty)
849 pub mod W {}
850 /// Read-write values (empty)
851 pub mod RW {}
852 }
853
854 /// Port A pull-up bit y (y=0..15)
855 pub mod PU1 {
856 /// Offset (1 bits)
857 pub const offset: u32 = 1;
858 /// Mask (1 bit: 1 << 1)
859 pub const mask: u32 = 1 << offset;
860 /// Read-only values (empty)
861 pub mod R {}
862 /// Write-only values (empty)
863 pub mod W {}
864 /// Read-write values (empty)
865 pub mod RW {}
866 }
867
868 /// Port A pull-up bit y (y=0..15)
869 pub mod PU0 {
870 /// Offset (0 bits)
871 pub const offset: u32 = 0;
872 /// Mask (1 bit: 1 << 0)
873 pub const mask: u32 = 1 << offset;
874 /// Read-only values (empty)
875 pub mod R {}
876 /// Write-only values (empty)
877 pub mod W {}
878 /// Read-write values (empty)
879 pub mod RW {}
880 }
881}
882
883/// Power Port A pull-down control register
884pub mod PDCRA {
885
886 /// Port A pull-down bit y (y=0..15)
887 pub mod PD15 {
888 /// Offset (15 bits)
889 pub const offset: u32 = 15;
890 /// Mask (1 bit: 1 << 15)
891 pub const mask: u32 = 1 << offset;
892 /// Read-only values (empty)
893 pub mod R {}
894 /// Write-only values (empty)
895 pub mod W {}
896 /// Read-write values (empty)
897 pub mod RW {}
898 }
899
900 /// Port A pull-down bit y (y=0..15)
901 pub mod PD14 {
902 /// Offset (14 bits)
903 pub const offset: u32 = 14;
904 /// Mask (1 bit: 1 << 14)
905 pub const mask: u32 = 1 << offset;
906 /// Read-only values (empty)
907 pub mod R {}
908 /// Write-only values (empty)
909 pub mod W {}
910 /// Read-write values (empty)
911 pub mod RW {}
912 }
913
914 /// Port A pull-down bit y (y=0..15)
915 pub mod PD13 {
916 /// Offset (13 bits)
917 pub const offset: u32 = 13;
918 /// Mask (1 bit: 1 << 13)
919 pub const mask: u32 = 1 << offset;
920 /// Read-only values (empty)
921 pub mod R {}
922 /// Write-only values (empty)
923 pub mod W {}
924 /// Read-write values (empty)
925 pub mod RW {}
926 }
927
928 /// Port A pull-down bit y (y=0..15)
929 pub mod PD12 {
930 /// Offset (12 bits)
931 pub const offset: u32 = 12;
932 /// Mask (1 bit: 1 << 12)
933 pub const mask: u32 = 1 << offset;
934 /// Read-only values (empty)
935 pub mod R {}
936 /// Write-only values (empty)
937 pub mod W {}
938 /// Read-write values (empty)
939 pub mod RW {}
940 }
941
942 /// Port A pull-down bit y (y=0..15)
943 pub mod PD11 {
944 /// Offset (11 bits)
945 pub const offset: u32 = 11;
946 /// Mask (1 bit: 1 << 11)
947 pub const mask: u32 = 1 << offset;
948 /// Read-only values (empty)
949 pub mod R {}
950 /// Write-only values (empty)
951 pub mod W {}
952 /// Read-write values (empty)
953 pub mod RW {}
954 }
955
956 /// Port A pull-down bit y (y=0..15)
957 pub mod PD10 {
958 /// Offset (10 bits)
959 pub const offset: u32 = 10;
960 /// Mask (1 bit: 1 << 10)
961 pub const mask: u32 = 1 << offset;
962 /// Read-only values (empty)
963 pub mod R {}
964 /// Write-only values (empty)
965 pub mod W {}
966 /// Read-write values (empty)
967 pub mod RW {}
968 }
969
970 /// Port A pull-down bit y (y=0..15)
971 pub mod PD9 {
972 /// Offset (9 bits)
973 pub const offset: u32 = 9;
974 /// Mask (1 bit: 1 << 9)
975 pub const mask: u32 = 1 << offset;
976 /// Read-only values (empty)
977 pub mod R {}
978 /// Write-only values (empty)
979 pub mod W {}
980 /// Read-write values (empty)
981 pub mod RW {}
982 }
983
984 /// Port A pull-down bit y (y=0..15)
985 pub mod PD8 {
986 /// Offset (8 bits)
987 pub const offset: u32 = 8;
988 /// Mask (1 bit: 1 << 8)
989 pub const mask: u32 = 1 << offset;
990 /// Read-only values (empty)
991 pub mod R {}
992 /// Write-only values (empty)
993 pub mod W {}
994 /// Read-write values (empty)
995 pub mod RW {}
996 }
997
998 /// Port A pull-down bit y (y=0..15)
999 pub mod PD7 {
1000 /// Offset (7 bits)
1001 pub const offset: u32 = 7;
1002 /// Mask (1 bit: 1 << 7)
1003 pub const mask: u32 = 1 << offset;
1004 /// Read-only values (empty)
1005 pub mod R {}
1006 /// Write-only values (empty)
1007 pub mod W {}
1008 /// Read-write values (empty)
1009 pub mod RW {}
1010 }
1011
1012 /// Port A pull-down bit y (y=0..15)
1013 pub mod PD6 {
1014 /// Offset (6 bits)
1015 pub const offset: u32 = 6;
1016 /// Mask (1 bit: 1 << 6)
1017 pub const mask: u32 = 1 << offset;
1018 /// Read-only values (empty)
1019 pub mod R {}
1020 /// Write-only values (empty)
1021 pub mod W {}
1022 /// Read-write values (empty)
1023 pub mod RW {}
1024 }
1025
1026 /// Port A pull-down bit y (y=0..15)
1027 pub mod PD5 {
1028 /// Offset (5 bits)
1029 pub const offset: u32 = 5;
1030 /// Mask (1 bit: 1 << 5)
1031 pub const mask: u32 = 1 << offset;
1032 /// Read-only values (empty)
1033 pub mod R {}
1034 /// Write-only values (empty)
1035 pub mod W {}
1036 /// Read-write values (empty)
1037 pub mod RW {}
1038 }
1039
1040 /// Port A pull-down bit y (y=0..15)
1041 pub mod PD4 {
1042 /// Offset (4 bits)
1043 pub const offset: u32 = 4;
1044 /// Mask (1 bit: 1 << 4)
1045 pub const mask: u32 = 1 << offset;
1046 /// Read-only values (empty)
1047 pub mod R {}
1048 /// Write-only values (empty)
1049 pub mod W {}
1050 /// Read-write values (empty)
1051 pub mod RW {}
1052 }
1053
1054 /// Port A pull-down bit y (y=0..15)
1055 pub mod PD3 {
1056 /// Offset (3 bits)
1057 pub const offset: u32 = 3;
1058 /// Mask (1 bit: 1 << 3)
1059 pub const mask: u32 = 1 << offset;
1060 /// Read-only values (empty)
1061 pub mod R {}
1062 /// Write-only values (empty)
1063 pub mod W {}
1064 /// Read-write values (empty)
1065 pub mod RW {}
1066 }
1067
1068 /// Port A pull-down bit y (y=0..15)
1069 pub mod PD2 {
1070 /// Offset (2 bits)
1071 pub const offset: u32 = 2;
1072 /// Mask (1 bit: 1 << 2)
1073 pub const mask: u32 = 1 << offset;
1074 /// Read-only values (empty)
1075 pub mod R {}
1076 /// Write-only values (empty)
1077 pub mod W {}
1078 /// Read-write values (empty)
1079 pub mod RW {}
1080 }
1081
1082 /// Port A pull-down bit y (y=0..15)
1083 pub mod PD1 {
1084 /// Offset (1 bits)
1085 pub const offset: u32 = 1;
1086 /// Mask (1 bit: 1 << 1)
1087 pub const mask: u32 = 1 << offset;
1088 /// Read-only values (empty)
1089 pub mod R {}
1090 /// Write-only values (empty)
1091 pub mod W {}
1092 /// Read-write values (empty)
1093 pub mod RW {}
1094 }
1095
1096 /// Port A pull-down bit y (y=0..15)
1097 pub mod PD0 {
1098 /// Offset (0 bits)
1099 pub const offset: u32 = 0;
1100 /// Mask (1 bit: 1 << 0)
1101 pub const mask: u32 = 1 << offset;
1102 /// Read-only values (empty)
1103 pub mod R {}
1104 /// Write-only values (empty)
1105 pub mod W {}
1106 /// Read-write values (empty)
1107 pub mod RW {}
1108 }
1109}
1110
1111/// Power Port B pull-up control register
1112pub mod PUCRB {
1113 pub use super::PUCRA::PU0;
1114 pub use super::PUCRA::PU1;
1115 pub use super::PUCRA::PU10;
1116 pub use super::PUCRA::PU11;
1117 pub use super::PUCRA::PU12;
1118 pub use super::PUCRA::PU13;
1119 pub use super::PUCRA::PU14;
1120 pub use super::PUCRA::PU15;
1121 pub use super::PUCRA::PU2;
1122 pub use super::PUCRA::PU3;
1123 pub use super::PUCRA::PU4;
1124 pub use super::PUCRA::PU5;
1125 pub use super::PUCRA::PU6;
1126 pub use super::PUCRA::PU7;
1127 pub use super::PUCRA::PU8;
1128 pub use super::PUCRA::PU9;
1129}
1130
1131/// Power Port B pull-down control register
1132pub mod PDCRB {
1133 pub use super::PDCRA::PD0;
1134 pub use super::PDCRA::PD1;
1135 pub use super::PDCRA::PD10;
1136 pub use super::PDCRA::PD11;
1137 pub use super::PDCRA::PD12;
1138 pub use super::PDCRA::PD13;
1139 pub use super::PDCRA::PD14;
1140 pub use super::PDCRA::PD15;
1141 pub use super::PDCRA::PD2;
1142 pub use super::PDCRA::PD3;
1143 pub use super::PDCRA::PD4;
1144 pub use super::PDCRA::PD5;
1145 pub use super::PDCRA::PD6;
1146 pub use super::PDCRA::PD7;
1147 pub use super::PDCRA::PD8;
1148 pub use super::PDCRA::PD9;
1149}
1150
1151/// Power Port C pull-up control register
1152pub mod PUCRC {
1153 pub use super::PUCRA::PU0;
1154 pub use super::PUCRA::PU1;
1155 pub use super::PUCRA::PU10;
1156 pub use super::PUCRA::PU11;
1157 pub use super::PUCRA::PU12;
1158 pub use super::PUCRA::PU13;
1159 pub use super::PUCRA::PU14;
1160 pub use super::PUCRA::PU15;
1161 pub use super::PUCRA::PU2;
1162 pub use super::PUCRA::PU3;
1163 pub use super::PUCRA::PU4;
1164 pub use super::PUCRA::PU5;
1165 pub use super::PUCRA::PU6;
1166 pub use super::PUCRA::PU7;
1167 pub use super::PUCRA::PU8;
1168 pub use super::PUCRA::PU9;
1169}
1170
1171/// Power Port C pull-down control register
1172pub mod PDCRC {
1173 pub use super::PDCRA::PD0;
1174 pub use super::PDCRA::PD1;
1175 pub use super::PDCRA::PD10;
1176 pub use super::PDCRA::PD11;
1177 pub use super::PDCRA::PD12;
1178 pub use super::PDCRA::PD13;
1179 pub use super::PDCRA::PD14;
1180 pub use super::PDCRA::PD15;
1181 pub use super::PDCRA::PD2;
1182 pub use super::PDCRA::PD3;
1183 pub use super::PDCRA::PD4;
1184 pub use super::PDCRA::PD5;
1185 pub use super::PDCRA::PD6;
1186 pub use super::PDCRA::PD7;
1187 pub use super::PDCRA::PD8;
1188 pub use super::PDCRA::PD9;
1189}
1190
1191/// Power Port D pull-up control register
1192pub mod PUCRD {
1193
1194 /// Port D pull-up bit y (y=0..15)
1195 pub mod PU9 {
1196 /// Offset (9 bits)
1197 pub const offset: u32 = 9;
1198 /// Mask (1 bit: 1 << 9)
1199 pub const mask: u32 = 1 << offset;
1200 /// Read-only values (empty)
1201 pub mod R {}
1202 /// Write-only values (empty)
1203 pub mod W {}
1204 /// Read-write values (empty)
1205 pub mod RW {}
1206 }
1207
1208 /// Port D pull-up bit y (y=0..15)
1209 pub mod PU8 {
1210 /// Offset (8 bits)
1211 pub const offset: u32 = 8;
1212 /// Mask (1 bit: 1 << 8)
1213 pub const mask: u32 = 1 << offset;
1214 /// Read-only values (empty)
1215 pub mod R {}
1216 /// Write-only values (empty)
1217 pub mod W {}
1218 /// Read-write values (empty)
1219 pub mod RW {}
1220 }
1221
1222 /// Port D pull-up bit y (y=0..15)
1223 pub mod PU6 {
1224 /// Offset (6 bits)
1225 pub const offset: u32 = 6;
1226 /// Mask (1 bit: 1 << 6)
1227 pub const mask: u32 = 1 << offset;
1228 /// Read-only values (empty)
1229 pub mod R {}
1230 /// Write-only values (empty)
1231 pub mod W {}
1232 /// Read-write values (empty)
1233 pub mod RW {}
1234 }
1235
1236 /// Port D pull-up bit y (y=0..15)
1237 pub mod PU5 {
1238 /// Offset (5 bits)
1239 pub const offset: u32 = 5;
1240 /// Mask (1 bit: 1 << 5)
1241 pub const mask: u32 = 1 << offset;
1242 /// Read-only values (empty)
1243 pub mod R {}
1244 /// Write-only values (empty)
1245 pub mod W {}
1246 /// Read-write values (empty)
1247 pub mod RW {}
1248 }
1249
1250 /// Port D pull-up bit y (y=0..15)
1251 pub mod PU4 {
1252 /// Offset (4 bits)
1253 pub const offset: u32 = 4;
1254 /// Mask (1 bit: 1 << 4)
1255 pub const mask: u32 = 1 << offset;
1256 /// Read-only values (empty)
1257 pub mod R {}
1258 /// Write-only values (empty)
1259 pub mod W {}
1260 /// Read-write values (empty)
1261 pub mod RW {}
1262 }
1263
1264 /// Port D pull-up bit y (y=0..15)
1265 pub mod PU3 {
1266 /// Offset (3 bits)
1267 pub const offset: u32 = 3;
1268 /// Mask (1 bit: 1 << 3)
1269 pub const mask: u32 = 1 << offset;
1270 /// Read-only values (empty)
1271 pub mod R {}
1272 /// Write-only values (empty)
1273 pub mod W {}
1274 /// Read-write values (empty)
1275 pub mod RW {}
1276 }
1277
1278 /// Port D pull-up bit y (y=0..15)
1279 pub mod PU2 {
1280 /// Offset (2 bits)
1281 pub const offset: u32 = 2;
1282 /// Mask (1 bit: 1 << 2)
1283 pub const mask: u32 = 1 << offset;
1284 /// Read-only values (empty)
1285 pub mod R {}
1286 /// Write-only values (empty)
1287 pub mod W {}
1288 /// Read-write values (empty)
1289 pub mod RW {}
1290 }
1291
1292 /// Port D pull-up bit y (y=0..15)
1293 pub mod PU1 {
1294 /// Offset (1 bits)
1295 pub const offset: u32 = 1;
1296 /// Mask (1 bit: 1 << 1)
1297 pub const mask: u32 = 1 << offset;
1298 /// Read-only values (empty)
1299 pub mod R {}
1300 /// Write-only values (empty)
1301 pub mod W {}
1302 /// Read-write values (empty)
1303 pub mod RW {}
1304 }
1305
1306 /// Port D pull-up bit y (y=0..15)
1307 pub mod PU0 {
1308 /// Offset (0 bits)
1309 pub const offset: u32 = 0;
1310 /// Mask (1 bit: 1 << 0)
1311 pub const mask: u32 = 1 << offset;
1312 /// Read-only values (empty)
1313 pub mod R {}
1314 /// Write-only values (empty)
1315 pub mod W {}
1316 /// Read-write values (empty)
1317 pub mod RW {}
1318 }
1319}
1320
1321/// Power Port D pull-down control register
1322pub mod PDCRD {
1323
1324 /// Port D pull-down bit y (y=0..15)
1325 pub mod PD9 {
1326 /// Offset (9 bits)
1327 pub const offset: u32 = 9;
1328 /// Mask (1 bit: 1 << 9)
1329 pub const mask: u32 = 1 << offset;
1330 /// Read-only values (empty)
1331 pub mod R {}
1332 /// Write-only values (empty)
1333 pub mod W {}
1334 /// Read-write values (empty)
1335 pub mod RW {}
1336 }
1337
1338 /// Port D pull-down bit y (y=0..15)
1339 pub mod PD8 {
1340 /// Offset (8 bits)
1341 pub const offset: u32 = 8;
1342 /// Mask (1 bit: 1 << 8)
1343 pub const mask: u32 = 1 << offset;
1344 /// Read-only values (empty)
1345 pub mod R {}
1346 /// Write-only values (empty)
1347 pub mod W {}
1348 /// Read-write values (empty)
1349 pub mod RW {}
1350 }
1351
1352 /// Port D pull-down bit y (y=0..15)
1353 pub mod PD6 {
1354 /// Offset (6 bits)
1355 pub const offset: u32 = 6;
1356 /// Mask (1 bit: 1 << 6)
1357 pub const mask: u32 = 1 << offset;
1358 /// Read-only values (empty)
1359 pub mod R {}
1360 /// Write-only values (empty)
1361 pub mod W {}
1362 /// Read-write values (empty)
1363 pub mod RW {}
1364 }
1365
1366 /// Port D pull-down bit y (y=0..15)
1367 pub mod PD5 {
1368 /// Offset (5 bits)
1369 pub const offset: u32 = 5;
1370 /// Mask (1 bit: 1 << 5)
1371 pub const mask: u32 = 1 << offset;
1372 /// Read-only values (empty)
1373 pub mod R {}
1374 /// Write-only values (empty)
1375 pub mod W {}
1376 /// Read-write values (empty)
1377 pub mod RW {}
1378 }
1379
1380 /// Port D pull-down bit y (y=0..15)
1381 pub mod PD4 {
1382 /// Offset (4 bits)
1383 pub const offset: u32 = 4;
1384 /// Mask (1 bit: 1 << 4)
1385 pub const mask: u32 = 1 << offset;
1386 /// Read-only values (empty)
1387 pub mod R {}
1388 /// Write-only values (empty)
1389 pub mod W {}
1390 /// Read-write values (empty)
1391 pub mod RW {}
1392 }
1393
1394 /// Port D pull-down bit y (y=0..15)
1395 pub mod PD3 {
1396 /// Offset (3 bits)
1397 pub const offset: u32 = 3;
1398 /// Mask (1 bit: 1 << 3)
1399 pub const mask: u32 = 1 << offset;
1400 /// Read-only values (empty)
1401 pub mod R {}
1402 /// Write-only values (empty)
1403 pub mod W {}
1404 /// Read-write values (empty)
1405 pub mod RW {}
1406 }
1407
1408 /// Port D pull-down bit y (y=0..15)
1409 pub mod PD2 {
1410 /// Offset (2 bits)
1411 pub const offset: u32 = 2;
1412 /// Mask (1 bit: 1 << 2)
1413 pub const mask: u32 = 1 << offset;
1414 /// Read-only values (empty)
1415 pub mod R {}
1416 /// Write-only values (empty)
1417 pub mod W {}
1418 /// Read-write values (empty)
1419 pub mod RW {}
1420 }
1421
1422 /// Port D pull-down bit y (y=0..15)
1423 pub mod PD1 {
1424 /// Offset (1 bits)
1425 pub const offset: u32 = 1;
1426 /// Mask (1 bit: 1 << 1)
1427 pub const mask: u32 = 1 << offset;
1428 /// Read-only values (empty)
1429 pub mod R {}
1430 /// Write-only values (empty)
1431 pub mod W {}
1432 /// Read-write values (empty)
1433 pub mod RW {}
1434 }
1435
1436 /// Port D pull-down bit y (y=0..15)
1437 pub mod PD0 {
1438 /// Offset (0 bits)
1439 pub const offset: u32 = 0;
1440 /// Mask (1 bit: 1 << 0)
1441 pub const mask: u32 = 1 << offset;
1442 /// Read-only values (empty)
1443 pub mod R {}
1444 /// Write-only values (empty)
1445 pub mod W {}
1446 /// Read-write values (empty)
1447 pub mod RW {}
1448 }
1449}
1450
1451/// Power Port F pull-up control register
1452pub mod PUCRF {
1453
1454 /// Port F pull-up bit y (y=0..15)
1455 pub mod PU2 {
1456 /// Offset (2 bits)
1457 pub const offset: u32 = 2;
1458 /// Mask (1 bit: 1 << 2)
1459 pub const mask: u32 = 1 << offset;
1460 /// Read-only values (empty)
1461 pub mod R {}
1462 /// Write-only values (empty)
1463 pub mod W {}
1464 /// Read-write values (empty)
1465 pub mod RW {}
1466 }
1467
1468 /// Port F pull-up bit y (y=0..15)
1469 pub mod PU1 {
1470 /// Offset (1 bits)
1471 pub const offset: u32 = 1;
1472 /// Mask (1 bit: 1 << 1)
1473 pub const mask: u32 = 1 << offset;
1474 /// Read-only values (empty)
1475 pub mod R {}
1476 /// Write-only values (empty)
1477 pub mod W {}
1478 /// Read-write values (empty)
1479 pub mod RW {}
1480 }
1481
1482 /// Port F pull-up bit y (y=0..15)
1483 pub mod PU0 {
1484 /// Offset (0 bits)
1485 pub const offset: u32 = 0;
1486 /// Mask (1 bit: 1 << 0)
1487 pub const mask: u32 = 1 << offset;
1488 /// Read-only values (empty)
1489 pub mod R {}
1490 /// Write-only values (empty)
1491 pub mod W {}
1492 /// Read-write values (empty)
1493 pub mod RW {}
1494 }
1495}
1496
1497/// Power Port F pull-down control register
1498pub mod PDCRF {
1499
1500 /// Port F pull-down bit y (y=0..15)
1501 pub mod PD2 {
1502 /// Offset (2 bits)
1503 pub const offset: u32 = 2;
1504 /// Mask (1 bit: 1 << 2)
1505 pub const mask: u32 = 1 << offset;
1506 /// Read-only values (empty)
1507 pub mod R {}
1508 /// Write-only values (empty)
1509 pub mod W {}
1510 /// Read-write values (empty)
1511 pub mod RW {}
1512 }
1513
1514 /// Port F pull-down bit y (y=0..15)
1515 pub mod PD1 {
1516 /// Offset (1 bits)
1517 pub const offset: u32 = 1;
1518 /// Mask (1 bit: 1 << 1)
1519 pub const mask: u32 = 1 << offset;
1520 /// Read-only values (empty)
1521 pub mod R {}
1522 /// Write-only values (empty)
1523 pub mod W {}
1524 /// Read-write values (empty)
1525 pub mod RW {}
1526 }
1527
1528 /// Port F pull-down bit y (y=0..15)
1529 pub mod PD0 {
1530 /// Offset (0 bits)
1531 pub const offset: u32 = 0;
1532 /// Mask (1 bit: 1 << 0)
1533 pub const mask: u32 = 1 << offset;
1534 /// Read-only values (empty)
1535 pub mod R {}
1536 /// Write-only values (empty)
1537 pub mod W {}
1538 /// Read-write values (empty)
1539 pub mod RW {}
1540 }
1541}
1542#[repr(C)]
1543pub struct RegisterBlock {
1544 /// Power control register 1
1545 pub CR1: RWRegister<u32>,
1546
1547 /// Power control register 2
1548 pub CR2: RWRegister<u32>,
1549
1550 /// Power control register 3
1551 pub CR3: RWRegister<u32>,
1552
1553 /// Power control register 4
1554 pub CR4: RWRegister<u32>,
1555
1556 /// Power status register 1
1557 pub SR1: RORegister<u32>,
1558
1559 /// Power status register 2
1560 pub SR2: RORegister<u32>,
1561
1562 /// Power status clear register
1563 pub SCR: WORegister<u32>,
1564
1565 _reserved1: [u8; 4],
1566
1567 /// Power Port A pull-up control register
1568 pub PUCRA: RWRegister<u32>,
1569
1570 /// Power Port A pull-down control register
1571 pub PDCRA: RWRegister<u32>,
1572
1573 /// Power Port B pull-up control register
1574 pub PUCRB: RWRegister<u32>,
1575
1576 /// Power Port B pull-down control register
1577 pub PDCRB: RWRegister<u32>,
1578
1579 /// Power Port C pull-up control register
1580 pub PUCRC: RWRegister<u32>,
1581
1582 /// Power Port C pull-down control register
1583 pub PDCRC: RWRegister<u32>,
1584
1585 /// Power Port D pull-up control register
1586 pub PUCRD: RWRegister<u32>,
1587
1588 /// Power Port D pull-down control register
1589 pub PDCRD: RWRegister<u32>,
1590
1591 _reserved2: [u8; 8],
1592
1593 /// Power Port F pull-up control register
1594 pub PUCRF: RWRegister<u32>,
1595
1596 /// Power Port F pull-down control register
1597 pub PDCRF: RWRegister<u32>,
1598}
1599pub struct ResetValues {
1600 pub CR1: u32,
1601 pub CR2: u32,
1602 pub CR3: u32,
1603 pub CR4: u32,
1604 pub SR1: u32,
1605 pub SR2: u32,
1606 pub SCR: u32,
1607 pub PUCRA: u32,
1608 pub PDCRA: u32,
1609 pub PUCRB: u32,
1610 pub PDCRB: u32,
1611 pub PUCRC: u32,
1612 pub PDCRC: u32,
1613 pub PUCRD: u32,
1614 pub PDCRD: u32,
1615 pub PUCRF: u32,
1616 pub PDCRF: u32,
1617}
1618#[cfg(not(feature = "nosync"))]
1619pub struct Instance {
1620 pub(crate) addr: u32,
1621 pub(crate) _marker: PhantomData<*const RegisterBlock>,
1622}
1623#[cfg(not(feature = "nosync"))]
1624impl ::core::ops::Deref for Instance {
1625 type Target = RegisterBlock;
1626 #[inline(always)]
1627 fn deref(&self) -> &RegisterBlock {
1628 unsafe { &*(self.addr as *const _) }
1629 }
1630}
1631#[cfg(feature = "rtic")]
1632unsafe impl Send for Instance {}