stm32ral/stm32g0/peripherals/fpu.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Floting point unit
4//!
5//! Used by: stm32g030, stm32g031, stm32g041
6
7use crate::RWRegister;
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// Floating-point context control register
12pub mod FPCCR {
13
14 /// LSPACT
15 pub mod LSPACT {
16 /// Offset (0 bits)
17 pub const offset: u32 = 0;
18 /// Mask (1 bit: 1 << 0)
19 pub const mask: u32 = 1 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values (empty)
25 pub mod RW {}
26 }
27
28 /// USER
29 pub mod USER {
30 /// Offset (1 bits)
31 pub const offset: u32 = 1;
32 /// Mask (1 bit: 1 << 1)
33 pub const mask: u32 = 1 << offset;
34 /// Read-only values (empty)
35 pub mod R {}
36 /// Write-only values (empty)
37 pub mod W {}
38 /// Read-write values (empty)
39 pub mod RW {}
40 }
41
42 /// THREAD
43 pub mod THREAD {
44 /// Offset (3 bits)
45 pub const offset: u32 = 3;
46 /// Mask (1 bit: 1 << 3)
47 pub const mask: u32 = 1 << offset;
48 /// Read-only values (empty)
49 pub mod R {}
50 /// Write-only values (empty)
51 pub mod W {}
52 /// Read-write values (empty)
53 pub mod RW {}
54 }
55
56 /// HFRDY
57 pub mod HFRDY {
58 /// Offset (4 bits)
59 pub const offset: u32 = 4;
60 /// Mask (1 bit: 1 << 4)
61 pub const mask: u32 = 1 << offset;
62 /// Read-only values (empty)
63 pub mod R {}
64 /// Write-only values (empty)
65 pub mod W {}
66 /// Read-write values (empty)
67 pub mod RW {}
68 }
69
70 /// MMRDY
71 pub mod MMRDY {
72 /// Offset (5 bits)
73 pub const offset: u32 = 5;
74 /// Mask (1 bit: 1 << 5)
75 pub const mask: u32 = 1 << offset;
76 /// Read-only values (empty)
77 pub mod R {}
78 /// Write-only values (empty)
79 pub mod W {}
80 /// Read-write values (empty)
81 pub mod RW {}
82 }
83
84 /// BFRDY
85 pub mod BFRDY {
86 /// Offset (6 bits)
87 pub const offset: u32 = 6;
88 /// Mask (1 bit: 1 << 6)
89 pub const mask: u32 = 1 << offset;
90 /// Read-only values (empty)
91 pub mod R {}
92 /// Write-only values (empty)
93 pub mod W {}
94 /// Read-write values (empty)
95 pub mod RW {}
96 }
97
98 /// MONRDY
99 pub mod MONRDY {
100 /// Offset (8 bits)
101 pub const offset: u32 = 8;
102 /// Mask (1 bit: 1 << 8)
103 pub const mask: u32 = 1 << offset;
104 /// Read-only values (empty)
105 pub mod R {}
106 /// Write-only values (empty)
107 pub mod W {}
108 /// Read-write values (empty)
109 pub mod RW {}
110 }
111
112 /// LSPEN
113 pub mod LSPEN {
114 /// Offset (30 bits)
115 pub const offset: u32 = 30;
116 /// Mask (1 bit: 1 << 30)
117 pub const mask: u32 = 1 << offset;
118 /// Read-only values (empty)
119 pub mod R {}
120 /// Write-only values (empty)
121 pub mod W {}
122 /// Read-write values (empty)
123 pub mod RW {}
124 }
125
126 /// ASPEN
127 pub mod ASPEN {
128 /// Offset (31 bits)
129 pub const offset: u32 = 31;
130 /// Mask (1 bit: 1 << 31)
131 pub const mask: u32 = 1 << offset;
132 /// Read-only values (empty)
133 pub mod R {}
134 /// Write-only values (empty)
135 pub mod W {}
136 /// Read-write values (empty)
137 pub mod RW {}
138 }
139}
140
141/// Floating-point context address register
142pub mod FPCAR {
143
144 /// Location of unpopulated floating-point
145 pub mod ADDRESS {
146 /// Offset (3 bits)
147 pub const offset: u32 = 3;
148 /// Mask (29 bits: 0x1fffffff << 3)
149 pub const mask: u32 = 0x1fffffff << offset;
150 /// Read-only values (empty)
151 pub mod R {}
152 /// Write-only values (empty)
153 pub mod W {}
154 /// Read-write values (empty)
155 pub mod RW {}
156 }
157}
158
159/// Floating-point status control register
160pub mod FPSCR {
161
162 /// Invalid operation cumulative exception bit
163 pub mod IOC {
164 /// Offset (0 bits)
165 pub const offset: u32 = 0;
166 /// Mask (1 bit: 1 << 0)
167 pub const mask: u32 = 1 << offset;
168 /// Read-only values (empty)
169 pub mod R {}
170 /// Write-only values (empty)
171 pub mod W {}
172 /// Read-write values (empty)
173 pub mod RW {}
174 }
175
176 /// Division by zero cumulative exception bit.
177 pub mod DZC {
178 /// Offset (1 bits)
179 pub const offset: u32 = 1;
180 /// Mask (1 bit: 1 << 1)
181 pub const mask: u32 = 1 << offset;
182 /// Read-only values (empty)
183 pub mod R {}
184 /// Write-only values (empty)
185 pub mod W {}
186 /// Read-write values (empty)
187 pub mod RW {}
188 }
189
190 /// Overflow cumulative exception bit
191 pub mod OFC {
192 /// Offset (2 bits)
193 pub const offset: u32 = 2;
194 /// Mask (1 bit: 1 << 2)
195 pub const mask: u32 = 1 << offset;
196 /// Read-only values (empty)
197 pub mod R {}
198 /// Write-only values (empty)
199 pub mod W {}
200 /// Read-write values (empty)
201 pub mod RW {}
202 }
203
204 /// Underflow cumulative exception bit
205 pub mod UFC {
206 /// Offset (3 bits)
207 pub const offset: u32 = 3;
208 /// Mask (1 bit: 1 << 3)
209 pub const mask: u32 = 1 << offset;
210 /// Read-only values (empty)
211 pub mod R {}
212 /// Write-only values (empty)
213 pub mod W {}
214 /// Read-write values (empty)
215 pub mod RW {}
216 }
217
218 /// Inexact cumulative exception bit
219 pub mod IXC {
220 /// Offset (4 bits)
221 pub const offset: u32 = 4;
222 /// Mask (1 bit: 1 << 4)
223 pub const mask: u32 = 1 << offset;
224 /// Read-only values (empty)
225 pub mod R {}
226 /// Write-only values (empty)
227 pub mod W {}
228 /// Read-write values (empty)
229 pub mod RW {}
230 }
231
232 /// Input denormal cumulative exception bit.
233 pub mod IDC {
234 /// Offset (7 bits)
235 pub const offset: u32 = 7;
236 /// Mask (1 bit: 1 << 7)
237 pub const mask: u32 = 1 << offset;
238 /// Read-only values (empty)
239 pub mod R {}
240 /// Write-only values (empty)
241 pub mod W {}
242 /// Read-write values (empty)
243 pub mod RW {}
244 }
245
246 /// Rounding Mode control field
247 pub mod RMode {
248 /// Offset (22 bits)
249 pub const offset: u32 = 22;
250 /// Mask (2 bits: 0b11 << 22)
251 pub const mask: u32 = 0b11 << offset;
252 /// Read-only values (empty)
253 pub mod R {}
254 /// Write-only values (empty)
255 pub mod W {}
256 /// Read-write values (empty)
257 pub mod RW {}
258 }
259
260 /// Flush-to-zero mode control bit:
261 pub mod FZ {
262 /// Offset (24 bits)
263 pub const offset: u32 = 24;
264 /// Mask (1 bit: 1 << 24)
265 pub const mask: u32 = 1 << offset;
266 /// Read-only values (empty)
267 pub mod R {}
268 /// Write-only values (empty)
269 pub mod W {}
270 /// Read-write values (empty)
271 pub mod RW {}
272 }
273
274 /// Default NaN mode control bit
275 pub mod DN {
276 /// Offset (25 bits)
277 pub const offset: u32 = 25;
278 /// Mask (1 bit: 1 << 25)
279 pub const mask: u32 = 1 << offset;
280 /// Read-only values (empty)
281 pub mod R {}
282 /// Write-only values (empty)
283 pub mod W {}
284 /// Read-write values (empty)
285 pub mod RW {}
286 }
287
288 /// Alternative half-precision control bit
289 pub mod AHP {
290 /// Offset (26 bits)
291 pub const offset: u32 = 26;
292 /// Mask (1 bit: 1 << 26)
293 pub const mask: u32 = 1 << offset;
294 /// Read-only values (empty)
295 pub mod R {}
296 /// Write-only values (empty)
297 pub mod W {}
298 /// Read-write values (empty)
299 pub mod RW {}
300 }
301
302 /// Overflow condition code flag
303 pub mod V {
304 /// Offset (28 bits)
305 pub const offset: u32 = 28;
306 /// Mask (1 bit: 1 << 28)
307 pub const mask: u32 = 1 << offset;
308 /// Read-only values (empty)
309 pub mod R {}
310 /// Write-only values (empty)
311 pub mod W {}
312 /// Read-write values (empty)
313 pub mod RW {}
314 }
315
316 /// Carry condition code flag
317 pub mod C {
318 /// Offset (29 bits)
319 pub const offset: u32 = 29;
320 /// Mask (1 bit: 1 << 29)
321 pub const mask: u32 = 1 << offset;
322 /// Read-only values (empty)
323 pub mod R {}
324 /// Write-only values (empty)
325 pub mod W {}
326 /// Read-write values (empty)
327 pub mod RW {}
328 }
329
330 /// Zero condition code flag
331 pub mod Z {
332 /// Offset (30 bits)
333 pub const offset: u32 = 30;
334 /// Mask (1 bit: 1 << 30)
335 pub const mask: u32 = 1 << offset;
336 /// Read-only values (empty)
337 pub mod R {}
338 /// Write-only values (empty)
339 pub mod W {}
340 /// Read-write values (empty)
341 pub mod RW {}
342 }
343
344 /// Negative condition code flag
345 pub mod N {
346 /// Offset (31 bits)
347 pub const offset: u32 = 31;
348 /// Mask (1 bit: 1 << 31)
349 pub const mask: u32 = 1 << offset;
350 /// Read-only values (empty)
351 pub mod R {}
352 /// Write-only values (empty)
353 pub mod W {}
354 /// Read-write values (empty)
355 pub mod RW {}
356 }
357}
358#[repr(C)]
359pub struct RegisterBlock {
360 /// Floating-point context control register
361 pub FPCCR: RWRegister<u32>,
362
363 /// Floating-point context address register
364 pub FPCAR: RWRegister<u32>,
365
366 /// Floating-point status control register
367 pub FPSCR: RWRegister<u32>,
368}
369pub struct ResetValues {
370 pub FPCCR: u32,
371 pub FPCAR: u32,
372 pub FPSCR: u32,
373}
374#[cfg(not(feature = "nosync"))]
375pub struct Instance {
376 pub(crate) addr: u32,
377 pub(crate) _marker: PhantomData<*const RegisterBlock>,
378}
379#[cfg(not(feature = "nosync"))]
380impl ::core::ops::Deref for Instance {
381 type Target = RegisterBlock;
382 #[inline(always)]
383 fn deref(&self) -> &RegisterBlock {
384 unsafe { &*(self.addr as *const _) }
385 }
386}
387#[cfg(feature = "rtic")]
388unsafe impl Send for Instance {}