stm32ral/stm32f7/peripherals/tim5.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! General purpose timers
4//!
5//! Used by: stm32f730, stm32f745, stm32f750, stm32f765, stm32f7x2, stm32f7x3, stm32f7x6, stm32f7x7, stm32f7x9
6
7use crate::{RWRegister, WORegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// control register 1
12pub mod CR1 {
13
14 /// Clock division
15 pub mod CKD {
16 /// Offset (8 bits)
17 pub const offset: u32 = 8;
18 /// Mask (2 bits: 0b11 << 8)
19 pub const mask: u32 = 0b11 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values
25 pub mod RW {
26
27 /// 0b00: t_DTS = t_CK_INT
28 pub const Div1: u32 = 0b00;
29
30 /// 0b01: t_DTS = 2 × t_CK_INT
31 pub const Div2: u32 = 0b01;
32
33 /// 0b10: t_DTS = 4 × t_CK_INT
34 pub const Div4: u32 = 0b10;
35 }
36 }
37
38 /// Auto-reload preload enable
39 pub mod ARPE {
40 /// Offset (7 bits)
41 pub const offset: u32 = 7;
42 /// Mask (1 bit: 1 << 7)
43 pub const mask: u32 = 1 << offset;
44 /// Read-only values (empty)
45 pub mod R {}
46 /// Write-only values (empty)
47 pub mod W {}
48 /// Read-write values
49 pub mod RW {
50
51 /// 0b0: TIMx_APRR register is not buffered
52 pub const Disabled: u32 = 0b0;
53
54 /// 0b1: TIMx_APRR register is buffered
55 pub const Enabled: u32 = 0b1;
56 }
57 }
58
59 /// Center-aligned mode selection
60 pub mod CMS {
61 /// Offset (5 bits)
62 pub const offset: u32 = 5;
63 /// Mask (2 bits: 0b11 << 5)
64 pub const mask: u32 = 0b11 << offset;
65 /// Read-only values (empty)
66 pub mod R {}
67 /// Write-only values (empty)
68 pub mod W {}
69 /// Read-write values
70 pub mod RW {
71
72 /// 0b00: The counter counts up or down depending on the direction bit
73 pub const EdgeAligned: u32 = 0b00;
74
75 /// 0b01: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
76 pub const CenterAligned1: u32 = 0b01;
77
78 /// 0b10: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
79 pub const CenterAligned2: u32 = 0b10;
80
81 /// 0b11: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
82 pub const CenterAligned3: u32 = 0b11;
83 }
84 }
85
86 /// Direction
87 pub mod DIR {
88 /// Offset (4 bits)
89 pub const offset: u32 = 4;
90 /// Mask (1 bit: 1 << 4)
91 pub const mask: u32 = 1 << offset;
92 /// Read-only values (empty)
93 pub mod R {}
94 /// Write-only values (empty)
95 pub mod W {}
96 /// Read-write values
97 pub mod RW {
98
99 /// 0b0: Counter used as upcounter
100 pub const Up: u32 = 0b0;
101
102 /// 0b1: Counter used as downcounter
103 pub const Down: u32 = 0b1;
104 }
105 }
106
107 /// One-pulse mode
108 pub mod OPM {
109 /// Offset (3 bits)
110 pub const offset: u32 = 3;
111 /// Mask (1 bit: 1 << 3)
112 pub const mask: u32 = 1 << offset;
113 /// Read-only values (empty)
114 pub mod R {}
115 /// Write-only values (empty)
116 pub mod W {}
117 /// Read-write values
118 pub mod RW {
119
120 /// 0b0: Counter is not stopped at update event
121 pub const Disabled: u32 = 0b0;
122
123 /// 0b1: Counter stops counting at the next update event (clearing the CEN bit)
124 pub const Enabled: u32 = 0b1;
125 }
126 }
127
128 /// Update request source
129 pub mod URS {
130 /// Offset (2 bits)
131 pub const offset: u32 = 2;
132 /// Mask (1 bit: 1 << 2)
133 pub const mask: u32 = 1 << offset;
134 /// Read-only values (empty)
135 pub mod R {}
136 /// Write-only values (empty)
137 pub mod W {}
138 /// Read-write values
139 pub mod RW {
140
141 /// 0b0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
142 pub const AnyEvent: u32 = 0b0;
143
144 /// 0b1: Only counter overflow/underflow generates an update interrupt or DMA request
145 pub const CounterOnly: u32 = 0b1;
146 }
147 }
148
149 /// Update disable
150 pub mod UDIS {
151 /// Offset (1 bits)
152 pub const offset: u32 = 1;
153 /// Mask (1 bit: 1 << 1)
154 pub const mask: u32 = 1 << offset;
155 /// Read-only values (empty)
156 pub mod R {}
157 /// Write-only values (empty)
158 pub mod W {}
159 /// Read-write values
160 pub mod RW {
161
162 /// 0b0: Update event enabled
163 pub const Enabled: u32 = 0b0;
164
165 /// 0b1: Update event disabled
166 pub const Disabled: u32 = 0b1;
167 }
168 }
169
170 /// Counter enable
171 pub mod CEN {
172 /// Offset (0 bits)
173 pub const offset: u32 = 0;
174 /// Mask (1 bit: 1 << 0)
175 pub const mask: u32 = 1 << offset;
176 /// Read-only values (empty)
177 pub mod R {}
178 /// Write-only values (empty)
179 pub mod W {}
180 /// Read-write values
181 pub mod RW {
182
183 /// 0b0: Counter disabled
184 pub const Disabled: u32 = 0b0;
185
186 /// 0b1: Counter enabled
187 pub const Enabled: u32 = 0b1;
188 }
189 }
190
191 /// UIF status bit remapping
192 pub mod UIFREMAP {
193 /// Offset (11 bits)
194 pub const offset: u32 = 11;
195 /// Mask (1 bit: 1 << 11)
196 pub const mask: u32 = 1 << offset;
197 /// Read-only values (empty)
198 pub mod R {}
199 /// Write-only values (empty)
200 pub mod W {}
201 /// Read-write values (empty)
202 pub mod RW {}
203 }
204}
205
206/// control register 2
207pub mod CR2 {
208
209 /// TI1 selection
210 pub mod TI1S {
211 /// Offset (7 bits)
212 pub const offset: u32 = 7;
213 /// Mask (1 bit: 1 << 7)
214 pub const mask: u32 = 1 << offset;
215 /// Read-only values (empty)
216 pub mod R {}
217 /// Write-only values (empty)
218 pub mod W {}
219 /// Read-write values
220 pub mod RW {
221
222 /// 0b0: The TIMx_CH1 pin is connected to TI1 input
223 pub const Normal: u32 = 0b0;
224
225 /// 0b1: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
226 pub const XOR: u32 = 0b1;
227 }
228 }
229
230 /// Master mode selection
231 pub mod MMS {
232 /// Offset (4 bits)
233 pub const offset: u32 = 4;
234 /// Mask (3 bits: 0b111 << 4)
235 pub const mask: u32 = 0b111 << offset;
236 /// Read-only values (empty)
237 pub mod R {}
238 /// Write-only values (empty)
239 pub mod W {}
240 /// Read-write values
241 pub mod RW {
242
243 /// 0b000: The UG bit from the TIMx_EGR register is used as trigger output
244 pub const Reset: u32 = 0b000;
245
246 /// 0b001: The counter enable signal, CNT_EN, is used as trigger output
247 pub const Enable: u32 = 0b001;
248
249 /// 0b010: The update event is selected as trigger output
250 pub const Update: u32 = 0b010;
251
252 /// 0b011: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
253 pub const ComparePulse: u32 = 0b011;
254
255 /// 0b100: OC1REF signal is used as trigger output
256 pub const CompareOC1: u32 = 0b100;
257
258 /// 0b101: OC2REF signal is used as trigger output
259 pub const CompareOC2: u32 = 0b101;
260
261 /// 0b110: OC3REF signal is used as trigger output
262 pub const CompareOC3: u32 = 0b110;
263
264 /// 0b111: OC4REF signal is used as trigger output
265 pub const CompareOC4: u32 = 0b111;
266 }
267 }
268
269 /// Capture/compare DMA selection
270 pub mod CCDS {
271 /// Offset (3 bits)
272 pub const offset: u32 = 3;
273 /// Mask (1 bit: 1 << 3)
274 pub const mask: u32 = 1 << offset;
275 /// Read-only values (empty)
276 pub mod R {}
277 /// Write-only values (empty)
278 pub mod W {}
279 /// Read-write values
280 pub mod RW {
281
282 /// 0b0: CCx DMA request sent when CCx event occurs
283 pub const OnCompare: u32 = 0b0;
284
285 /// 0b1: CCx DMA request sent when update event occurs
286 pub const OnUpdate: u32 = 0b1;
287 }
288 }
289}
290
291/// slave mode control register
292pub mod SMCR {
293
294 /// Slave mode selection
295 pub mod SMS {
296 /// Offset (0 bits)
297 pub const offset: u32 = 0;
298 /// Mask (3 bits: 0b111 << 0)
299 pub const mask: u32 = 0b111 << offset;
300 /// Read-only values (empty)
301 pub mod R {}
302 /// Write-only values (empty)
303 pub mod W {}
304 /// Read-write values
305 pub mod RW {
306
307 /// 0b000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
308 pub const Disabled: u32 = 0b000;
309
310 /// 0b001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
311 pub const Encoder_Mode_1: u32 = 0b001;
312
313 /// 0b010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
314 pub const Encoder_Mode_2: u32 = 0b010;
315
316 /// 0b011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
317 pub const Encoder_Mode_3: u32 = 0b011;
318
319 /// 0b100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
320 pub const Reset_Mode: u32 = 0b100;
321
322 /// 0b101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
323 pub const Gated_Mode: u32 = 0b101;
324
325 /// 0b110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
326 pub const Trigger_Mode: u32 = 0b110;
327
328 /// 0b111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
329 pub const Ext_Clock_Mode: u32 = 0b111;
330 }
331 }
332
333 /// Trigger selection
334 pub mod TS {
335 /// Offset (4 bits)
336 pub const offset: u32 = 4;
337 /// Mask (3 bits: 0b111 << 4)
338 pub const mask: u32 = 0b111 << offset;
339 /// Read-only values (empty)
340 pub mod R {}
341 /// Write-only values (empty)
342 pub mod W {}
343 /// Read-write values
344 pub mod RW {
345
346 /// 0b000: Internal Trigger 0 (ITR0)
347 pub const ITR0: u32 = 0b000;
348
349 /// 0b001: Internal Trigger 1 (ITR1)
350 pub const ITR1: u32 = 0b001;
351
352 /// 0b010: Internal Trigger 2 (ITR2)
353 pub const ITR2: u32 = 0b010;
354
355 /// 0b100: TI1 Edge Detector (TI1F_ED)
356 pub const TI1F_ED: u32 = 0b100;
357
358 /// 0b101: Filtered Timer Input 1 (TI1FP1)
359 pub const TI1FP1: u32 = 0b101;
360
361 /// 0b110: Filtered Timer Input 2 (TI2FP2)
362 pub const TI2FP2: u32 = 0b110;
363
364 /// 0b111: External Trigger input (ETRF)
365 pub const ETRF: u32 = 0b111;
366 }
367 }
368
369 /// Master/Slave mode
370 pub mod MSM {
371 /// Offset (7 bits)
372 pub const offset: u32 = 7;
373 /// Mask (1 bit: 1 << 7)
374 pub const mask: u32 = 1 << offset;
375 /// Read-only values (empty)
376 pub mod R {}
377 /// Write-only values (empty)
378 pub mod W {}
379 /// Read-write values
380 pub mod RW {
381
382 /// 0b0: No action
383 pub const NoSync: u32 = 0b0;
384
385 /// 0b1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
386 pub const Sync: u32 = 0b1;
387 }
388 }
389
390 /// External trigger filter
391 pub mod ETF {
392 /// Offset (8 bits)
393 pub const offset: u32 = 8;
394 /// Mask (4 bits: 0b1111 << 8)
395 pub const mask: u32 = 0b1111 << offset;
396 /// Read-only values (empty)
397 pub mod R {}
398 /// Write-only values (empty)
399 pub mod W {}
400 /// Read-write values
401 pub mod RW {
402
403 /// 0b0000: No filter, sampling is done at fDTS
404 pub const NoFilter: u32 = 0b0000;
405
406 /// 0b0001: fSAMPLING=fCK_INT, N=2
407 pub const FCK_INT_N2: u32 = 0b0001;
408
409 /// 0b0010: fSAMPLING=fCK_INT, N=4
410 pub const FCK_INT_N4: u32 = 0b0010;
411
412 /// 0b0011: fSAMPLING=fCK_INT, N=8
413 pub const FCK_INT_N8: u32 = 0b0011;
414
415 /// 0b0100: fSAMPLING=fDTS/2, N=6
416 pub const FDTS_Div2_N6: u32 = 0b0100;
417
418 /// 0b0101: fSAMPLING=fDTS/2, N=8
419 pub const FDTS_Div2_N8: u32 = 0b0101;
420
421 /// 0b0110: fSAMPLING=fDTS/4, N=6
422 pub const FDTS_Div4_N6: u32 = 0b0110;
423
424 /// 0b0111: fSAMPLING=fDTS/4, N=8
425 pub const FDTS_Div4_N8: u32 = 0b0111;
426
427 /// 0b1000: fSAMPLING=fDTS/8, N=6
428 pub const FDTS_Div8_N6: u32 = 0b1000;
429
430 /// 0b1001: fSAMPLING=fDTS/8, N=8
431 pub const FDTS_Div8_N8: u32 = 0b1001;
432
433 /// 0b1010: fSAMPLING=fDTS/16, N=5
434 pub const FDTS_Div16_N5: u32 = 0b1010;
435
436 /// 0b1011: fSAMPLING=fDTS/16, N=6
437 pub const FDTS_Div16_N6: u32 = 0b1011;
438
439 /// 0b1100: fSAMPLING=fDTS/16, N=8
440 pub const FDTS_Div16_N8: u32 = 0b1100;
441
442 /// 0b1101: fSAMPLING=fDTS/32, N=5
443 pub const FDTS_Div32_N5: u32 = 0b1101;
444
445 /// 0b1110: fSAMPLING=fDTS/32, N=6
446 pub const FDTS_Div32_N6: u32 = 0b1110;
447
448 /// 0b1111: fSAMPLING=fDTS/32, N=8
449 pub const FDTS_Div32_N8: u32 = 0b1111;
450 }
451 }
452
453 /// External trigger prescaler
454 pub mod ETPS {
455 /// Offset (12 bits)
456 pub const offset: u32 = 12;
457 /// Mask (2 bits: 0b11 << 12)
458 pub const mask: u32 = 0b11 << offset;
459 /// Read-only values (empty)
460 pub mod R {}
461 /// Write-only values (empty)
462 pub mod W {}
463 /// Read-write values
464 pub mod RW {
465
466 /// 0b00: Prescaler OFF
467 pub const Div1: u32 = 0b00;
468
469 /// 0b01: ETRP frequency divided by 2
470 pub const Div2: u32 = 0b01;
471
472 /// 0b10: ETRP frequency divided by 4
473 pub const Div4: u32 = 0b10;
474
475 /// 0b11: ETRP frequency divided by 8
476 pub const Div8: u32 = 0b11;
477 }
478 }
479
480 /// External clock enable
481 pub mod ECE {
482 /// Offset (14 bits)
483 pub const offset: u32 = 14;
484 /// Mask (1 bit: 1 << 14)
485 pub const mask: u32 = 1 << offset;
486 /// Read-only values (empty)
487 pub mod R {}
488 /// Write-only values (empty)
489 pub mod W {}
490 /// Read-write values
491 pub mod RW {
492
493 /// 0b0: External clock mode 2 disabled
494 pub const Disabled: u32 = 0b0;
495
496 /// 0b1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
497 pub const Enabled: u32 = 0b1;
498 }
499 }
500
501 /// External trigger polarity
502 pub mod ETP {
503 /// Offset (15 bits)
504 pub const offset: u32 = 15;
505 /// Mask (1 bit: 1 << 15)
506 pub const mask: u32 = 1 << offset;
507 /// Read-only values (empty)
508 pub mod R {}
509 /// Write-only values (empty)
510 pub mod W {}
511 /// Read-write values
512 pub mod RW {
513
514 /// 0b0: ETR is noninverted, active at high level or rising edge
515 pub const NotInverted: u32 = 0b0;
516
517 /// 0b1: ETR is inverted, active at low level or falling edge
518 pub const Inverted: u32 = 0b1;
519 }
520 }
521
522 /// Slave model selection - bit\[3\]
523 pub mod SMS_3 {
524 /// Offset (16 bits)
525 pub const offset: u32 = 16;
526 /// Mask (1 bit: 1 << 16)
527 pub const mask: u32 = 1 << offset;
528 /// Read-only values (empty)
529 pub mod R {}
530 /// Write-only values (empty)
531 pub mod W {}
532 /// Read-write values (empty)
533 pub mod RW {}
534 }
535}
536
537/// DMA/Interrupt enable register
538pub mod DIER {
539
540 /// Trigger DMA request enable
541 pub mod TDE {
542 /// Offset (14 bits)
543 pub const offset: u32 = 14;
544 /// Mask (1 bit: 1 << 14)
545 pub const mask: u32 = 1 << offset;
546 /// Read-only values (empty)
547 pub mod R {}
548 /// Write-only values (empty)
549 pub mod W {}
550 /// Read-write values
551 pub mod RW {
552
553 /// 0b0: Trigger DMA request disabled
554 pub const Disabled: u32 = 0b0;
555
556 /// 0b1: Trigger DMA request enabled
557 pub const Enabled: u32 = 0b1;
558 }
559 }
560
561 /// Capture/Compare 4 DMA request enable
562 pub mod CC4DE {
563 /// Offset (12 bits)
564 pub const offset: u32 = 12;
565 /// Mask (1 bit: 1 << 12)
566 pub const mask: u32 = 1 << offset;
567 /// Read-only values (empty)
568 pub mod R {}
569 /// Write-only values (empty)
570 pub mod W {}
571 /// Read-write values
572 pub mod RW {
573
574 /// 0b0: CCx DMA request disabled
575 pub const Disabled: u32 = 0b0;
576
577 /// 0b1: CCx DMA request enabled
578 pub const Enabled: u32 = 0b1;
579 }
580 }
581
582 /// Capture/Compare 3 DMA request enable
583 pub mod CC3DE {
584 /// Offset (11 bits)
585 pub const offset: u32 = 11;
586 /// Mask (1 bit: 1 << 11)
587 pub const mask: u32 = 1 << offset;
588 /// Read-only values (empty)
589 pub mod R {}
590 /// Write-only values (empty)
591 pub mod W {}
592 pub use super::CC4DE::RW;
593 }
594
595 /// Capture/Compare 2 DMA request enable
596 pub mod CC2DE {
597 /// Offset (10 bits)
598 pub const offset: u32 = 10;
599 /// Mask (1 bit: 1 << 10)
600 pub const mask: u32 = 1 << offset;
601 /// Read-only values (empty)
602 pub mod R {}
603 /// Write-only values (empty)
604 pub mod W {}
605 pub use super::CC4DE::RW;
606 }
607
608 /// Capture/Compare 1 DMA request enable
609 pub mod CC1DE {
610 /// Offset (9 bits)
611 pub const offset: u32 = 9;
612 /// Mask (1 bit: 1 << 9)
613 pub const mask: u32 = 1 << offset;
614 /// Read-only values (empty)
615 pub mod R {}
616 /// Write-only values (empty)
617 pub mod W {}
618 pub use super::CC4DE::RW;
619 }
620
621 /// Update DMA request enable
622 pub mod UDE {
623 /// Offset (8 bits)
624 pub const offset: u32 = 8;
625 /// Mask (1 bit: 1 << 8)
626 pub const mask: u32 = 1 << offset;
627 /// Read-only values (empty)
628 pub mod R {}
629 /// Write-only values (empty)
630 pub mod W {}
631 /// Read-write values
632 pub mod RW {
633
634 /// 0b0: Update DMA request disabled
635 pub const Disabled: u32 = 0b0;
636
637 /// 0b1: Update DMA request enabled
638 pub const Enabled: u32 = 0b1;
639 }
640 }
641
642 /// Trigger interrupt enable
643 pub mod TIE {
644 /// Offset (6 bits)
645 pub const offset: u32 = 6;
646 /// Mask (1 bit: 1 << 6)
647 pub const mask: u32 = 1 << offset;
648 /// Read-only values (empty)
649 pub mod R {}
650 /// Write-only values (empty)
651 pub mod W {}
652 /// Read-write values
653 pub mod RW {
654
655 /// 0b0: Trigger interrupt disabled
656 pub const Disabled: u32 = 0b0;
657
658 /// 0b1: Trigger interrupt enabled
659 pub const Enabled: u32 = 0b1;
660 }
661 }
662
663 /// Capture/Compare 4 interrupt enable
664 pub mod CC4IE {
665 /// Offset (4 bits)
666 pub const offset: u32 = 4;
667 /// Mask (1 bit: 1 << 4)
668 pub const mask: u32 = 1 << offset;
669 /// Read-only values (empty)
670 pub mod R {}
671 /// Write-only values (empty)
672 pub mod W {}
673 /// Read-write values
674 pub mod RW {
675
676 /// 0b0: CCx interrupt disabled
677 pub const Disabled: u32 = 0b0;
678
679 /// 0b1: CCx interrupt enabled
680 pub const Enabled: u32 = 0b1;
681 }
682 }
683
684 /// Capture/Compare 3 interrupt enable
685 pub mod CC3IE {
686 /// Offset (3 bits)
687 pub const offset: u32 = 3;
688 /// Mask (1 bit: 1 << 3)
689 pub const mask: u32 = 1 << offset;
690 /// Read-only values (empty)
691 pub mod R {}
692 /// Write-only values (empty)
693 pub mod W {}
694 pub use super::CC4IE::RW;
695 }
696
697 /// Capture/Compare 2 interrupt enable
698 pub mod CC2IE {
699 /// Offset (2 bits)
700 pub const offset: u32 = 2;
701 /// Mask (1 bit: 1 << 2)
702 pub const mask: u32 = 1 << offset;
703 /// Read-only values (empty)
704 pub mod R {}
705 /// Write-only values (empty)
706 pub mod W {}
707 pub use super::CC4IE::RW;
708 }
709
710 /// Capture/Compare 1 interrupt enable
711 pub mod CC1IE {
712 /// Offset (1 bits)
713 pub const offset: u32 = 1;
714 /// Mask (1 bit: 1 << 1)
715 pub const mask: u32 = 1 << offset;
716 /// Read-only values (empty)
717 pub mod R {}
718 /// Write-only values (empty)
719 pub mod W {}
720 pub use super::CC4IE::RW;
721 }
722
723 /// Update interrupt enable
724 pub mod UIE {
725 /// Offset (0 bits)
726 pub const offset: u32 = 0;
727 /// Mask (1 bit: 1 << 0)
728 pub const mask: u32 = 1 << offset;
729 /// Read-only values (empty)
730 pub mod R {}
731 /// Write-only values (empty)
732 pub mod W {}
733 /// Read-write values
734 pub mod RW {
735
736 /// 0b0: Update interrupt disabled
737 pub const Disabled: u32 = 0b0;
738
739 /// 0b1: Update interrupt enabled
740 pub const Enabled: u32 = 0b1;
741 }
742 }
743}
744
745/// status register
746pub mod SR {
747
748 /// Capture/Compare 4 overcapture flag
749 pub mod CC4OF {
750 /// Offset (12 bits)
751 pub const offset: u32 = 12;
752 /// Mask (1 bit: 1 << 12)
753 pub const mask: u32 = 1 << offset;
754 /// Read-only values
755 pub mod R {
756
757 /// 0b1: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
758 pub const Overcapture: u32 = 0b1;
759 }
760 /// Write-only values
761 pub mod W {
762
763 /// 0b0: Clear flag
764 pub const Clear: u32 = 0b0;
765 }
766 /// Read-write values (empty)
767 pub mod RW {}
768 }
769
770 /// Capture/Compare 3 overcapture flag
771 pub mod CC3OF {
772 /// Offset (11 bits)
773 pub const offset: u32 = 11;
774 /// Mask (1 bit: 1 << 11)
775 pub const mask: u32 = 1 << offset;
776 pub use super::CC4OF::R;
777 pub use super::CC4OF::W;
778 /// Read-write values (empty)
779 pub mod RW {}
780 }
781
782 /// Capture/compare 2 overcapture flag
783 pub mod CC2OF {
784 /// Offset (10 bits)
785 pub const offset: u32 = 10;
786 /// Mask (1 bit: 1 << 10)
787 pub const mask: u32 = 1 << offset;
788 pub use super::CC4OF::R;
789 pub use super::CC4OF::W;
790 /// Read-write values (empty)
791 pub mod RW {}
792 }
793
794 /// Capture/Compare 1 overcapture flag
795 pub mod CC1OF {
796 /// Offset (9 bits)
797 pub const offset: u32 = 9;
798 /// Mask (1 bit: 1 << 9)
799 pub const mask: u32 = 1 << offset;
800 pub use super::CC4OF::R;
801 pub use super::CC4OF::W;
802 /// Read-write values (empty)
803 pub mod RW {}
804 }
805
806 /// Trigger interrupt flag
807 pub mod TIF {
808 /// Offset (6 bits)
809 pub const offset: u32 = 6;
810 /// Mask (1 bit: 1 << 6)
811 pub const mask: u32 = 1 << offset;
812 /// Read-only values
813 pub mod R {
814
815 /// 0b0: No trigger event occurred
816 pub const NoTrigger: u32 = 0b0;
817
818 /// 0b1: Trigger interrupt pending
819 pub const Trigger: u32 = 0b1;
820 }
821 pub use super::CC4OF::W;
822 /// Read-write values (empty)
823 pub mod RW {}
824 }
825
826 /// Capture/Compare 4 interrupt flag
827 pub mod CC4IF {
828 /// Offset (4 bits)
829 pub const offset: u32 = 4;
830 /// Mask (1 bit: 1 << 4)
831 pub const mask: u32 = 1 << offset;
832 /// Read-only values
833 pub mod R {
834
835 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
836 pub const Match: u32 = 0b1;
837 }
838 pub use super::CC4OF::W;
839 /// Read-write values (empty)
840 pub mod RW {}
841 }
842
843 /// Capture/Compare 3 interrupt flag
844 pub mod CC3IF {
845 /// Offset (3 bits)
846 pub const offset: u32 = 3;
847 /// Mask (1 bit: 1 << 3)
848 pub const mask: u32 = 1 << offset;
849 /// Read-only values
850 pub mod R {
851
852 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
853 pub const Match: u32 = 0b1;
854 }
855 pub use super::CC4OF::W;
856 /// Read-write values (empty)
857 pub mod RW {}
858 }
859
860 /// Capture/Compare 2 interrupt flag
861 pub mod CC2IF {
862 /// Offset (2 bits)
863 pub const offset: u32 = 2;
864 /// Mask (1 bit: 1 << 2)
865 pub const mask: u32 = 1 << offset;
866 /// Read-only values
867 pub mod R {
868
869 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
870 pub const Match: u32 = 0b1;
871 }
872 pub use super::CC4OF::W;
873 /// Read-write values (empty)
874 pub mod RW {}
875 }
876
877 /// Capture/compare 1 interrupt flag
878 pub mod CC1IF {
879 /// Offset (1 bits)
880 pub const offset: u32 = 1;
881 /// Mask (1 bit: 1 << 1)
882 pub const mask: u32 = 1 << offset;
883 /// Read-only values
884 pub mod R {
885
886 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
887 pub const Match: u32 = 0b1;
888 }
889 pub use super::CC4OF::W;
890 /// Read-write values (empty)
891 pub mod RW {}
892 }
893
894 /// Update interrupt flag
895 pub mod UIF {
896 /// Offset (0 bits)
897 pub const offset: u32 = 0;
898 /// Mask (1 bit: 1 << 0)
899 pub const mask: u32 = 1 << offset;
900 /// Read-only values (empty)
901 pub mod R {}
902 /// Write-only values (empty)
903 pub mod W {}
904 /// Read-write values
905 pub mod RW {
906
907 /// 0b0: No update occurred
908 pub const Clear: u32 = 0b0;
909
910 /// 0b1: Update interrupt pending.
911 pub const UpdatePending: u32 = 0b1;
912 }
913 }
914}
915
916/// event generation register
917pub mod EGR {
918
919 /// Trigger generation
920 pub mod TG {
921 /// Offset (6 bits)
922 pub const offset: u32 = 6;
923 /// Mask (1 bit: 1 << 6)
924 pub const mask: u32 = 1 << offset;
925 /// Read-only values (empty)
926 pub mod R {}
927 /// Write-only values
928 pub mod W {
929
930 /// 0b1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
931 pub const Trigger: u32 = 0b1;
932 }
933 /// Read-write values (empty)
934 pub mod RW {}
935 }
936
937 /// Capture/compare 4 generation
938 pub mod CC4G {
939 /// Offset (4 bits)
940 pub const offset: u32 = 4;
941 /// Mask (1 bit: 1 << 4)
942 pub const mask: u32 = 1 << offset;
943 /// Read-only values (empty)
944 pub mod R {}
945 /// Write-only values
946 pub mod W {
947
948 /// 0b1: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
949 pub const Trigger: u32 = 0b1;
950 }
951 /// Read-write values (empty)
952 pub mod RW {}
953 }
954
955 /// Capture/compare 3 generation
956 pub mod CC3G {
957 /// Offset (3 bits)
958 pub const offset: u32 = 3;
959 /// Mask (1 bit: 1 << 3)
960 pub const mask: u32 = 1 << offset;
961 /// Read-only values (empty)
962 pub mod R {}
963 pub use super::CC4G::W;
964 /// Read-write values (empty)
965 pub mod RW {}
966 }
967
968 /// Capture/compare 2 generation
969 pub mod CC2G {
970 /// Offset (2 bits)
971 pub const offset: u32 = 2;
972 /// Mask (1 bit: 1 << 2)
973 pub const mask: u32 = 1 << offset;
974 /// Read-only values (empty)
975 pub mod R {}
976 pub use super::CC4G::W;
977 /// Read-write values (empty)
978 pub mod RW {}
979 }
980
981 /// Capture/compare 1 generation
982 pub mod CC1G {
983 /// Offset (1 bits)
984 pub const offset: u32 = 1;
985 /// Mask (1 bit: 1 << 1)
986 pub const mask: u32 = 1 << offset;
987 /// Read-only values (empty)
988 pub mod R {}
989 pub use super::CC4G::W;
990 /// Read-write values (empty)
991 pub mod RW {}
992 }
993
994 /// Update generation
995 pub mod UG {
996 /// Offset (0 bits)
997 pub const offset: u32 = 0;
998 /// Mask (1 bit: 1 << 0)
999 pub const mask: u32 = 1 << offset;
1000 /// Read-only values (empty)
1001 pub mod R {}
1002 /// Write-only values
1003 pub mod W {
1004
1005 /// 0b1: Re-initializes the timer counter and generates an update of the registers.
1006 pub const Update: u32 = 0b1;
1007 }
1008 /// Read-write values (empty)
1009 pub mod RW {}
1010 }
1011}
1012
1013/// CCMR1_Output and CCMR1_Input
1014/// CCMR1_Output: capture/compare mode register 1 (output mode)
1015/// CCMR1_Input: capture/compare mode register 1 (input mode)
1016pub mod CCMR1 {
1017
1018 /// OC2CE
1019 pub mod OC2CE {
1020 /// Offset (15 bits)
1021 pub const offset: u32 = 15;
1022 /// Mask (1 bit: 1 << 15)
1023 pub const mask: u32 = 1 << offset;
1024 /// Read-only values (empty)
1025 pub mod R {}
1026 /// Write-only values (empty)
1027 pub mod W {}
1028 /// Read-write values (empty)
1029 pub mod RW {}
1030 }
1031
1032 /// OC2M
1033 pub mod OC2M {
1034 /// Offset (12 bits)
1035 pub const offset: u32 = 12;
1036 /// Mask (3 bits: 0b111 << 12)
1037 pub const mask: u32 = 0b111 << offset;
1038 /// Read-only values (empty)
1039 pub mod R {}
1040 /// Write-only values (empty)
1041 pub mod W {}
1042 /// Read-write values
1043 pub mod RW {
1044
1045 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1046 pub const Frozen: u32 = 0b000;
1047
1048 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
1049 pub const ActiveOnMatch: u32 = 0b001;
1050
1051 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
1052 pub const InactiveOnMatch: u32 = 0b010;
1053
1054 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
1055 pub const Toggle: u32 = 0b011;
1056
1057 /// 0b100: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
1058 pub const ForceInactive: u32 = 0b100;
1059
1060 /// 0b101: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
1061 pub const ForceActive: u32 = 0b101;
1062
1063 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
1064 pub const PwmMode1: u32 = 0b110;
1065
1066 /// 0b111: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
1067 pub const PwmMode2: u32 = 0b111;
1068 }
1069 }
1070
1071 /// OC2PE
1072 pub mod OC2PE {
1073 /// Offset (11 bits)
1074 pub const offset: u32 = 11;
1075 /// Mask (1 bit: 1 << 11)
1076 pub const mask: u32 = 1 << offset;
1077 /// Read-only values (empty)
1078 pub mod R {}
1079 /// Write-only values (empty)
1080 pub mod W {}
1081 /// Read-write values
1082 pub mod RW {
1083
1084 /// 0b0: Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately
1085 pub const Disabled: u32 = 0b0;
1086
1087 /// 0b1: Preload register on CCR2 enabled. Preload value is loaded into active register on each update event
1088 pub const Enabled: u32 = 0b1;
1089 }
1090 }
1091
1092 /// OC2FE
1093 pub mod OC2FE {
1094 /// Offset (10 bits)
1095 pub const offset: u32 = 10;
1096 /// Mask (1 bit: 1 << 10)
1097 pub const mask: u32 = 1 << offset;
1098 /// Read-only values (empty)
1099 pub mod R {}
1100 /// Write-only values (empty)
1101 pub mod W {}
1102 /// Read-write values (empty)
1103 pub mod RW {}
1104 }
1105
1106 /// CC2S
1107 pub mod CC2S {
1108 /// Offset (8 bits)
1109 pub const offset: u32 = 8;
1110 /// Mask (2 bits: 0b11 << 8)
1111 pub const mask: u32 = 0b11 << offset;
1112 /// Read-only values (empty)
1113 pub mod R {}
1114 /// Write-only values (empty)
1115 pub mod W {}
1116 /// Read-write values
1117 pub mod RW {
1118
1119 /// 0b00: CC2 channel is configured as output
1120 pub const Output: u32 = 0b00;
1121 }
1122 }
1123
1124 /// OC1CE
1125 pub mod OC1CE {
1126 /// Offset (7 bits)
1127 pub const offset: u32 = 7;
1128 /// Mask (1 bit: 1 << 7)
1129 pub const mask: u32 = 1 << offset;
1130 /// Read-only values (empty)
1131 pub mod R {}
1132 /// Write-only values (empty)
1133 pub mod W {}
1134 /// Read-write values (empty)
1135 pub mod RW {}
1136 }
1137
1138 /// OC1M
1139 pub mod OC1M {
1140 /// Offset (4 bits)
1141 pub const offset: u32 = 4;
1142 /// Mask (3 bits: 0b111 << 4)
1143 pub const mask: u32 = 0b111 << offset;
1144 /// Read-only values (empty)
1145 pub mod R {}
1146 /// Write-only values (empty)
1147 pub mod W {}
1148 pub use super::OC2M::RW;
1149 }
1150
1151 /// OC1PE
1152 pub mod OC1PE {
1153 /// Offset (3 bits)
1154 pub const offset: u32 = 3;
1155 /// Mask (1 bit: 1 << 3)
1156 pub const mask: u32 = 1 << offset;
1157 /// Read-only values (empty)
1158 pub mod R {}
1159 /// Write-only values (empty)
1160 pub mod W {}
1161 /// Read-write values
1162 pub mod RW {
1163
1164 /// 0b0: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1165 pub const Disabled: u32 = 0b0;
1166
1167 /// 0b1: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
1168 pub const Enabled: u32 = 0b1;
1169 }
1170 }
1171
1172 /// OC1FE
1173 pub mod OC1FE {
1174 /// Offset (2 bits)
1175 pub const offset: u32 = 2;
1176 /// Mask (1 bit: 1 << 2)
1177 pub const mask: u32 = 1 << offset;
1178 /// Read-only values (empty)
1179 pub mod R {}
1180 /// Write-only values (empty)
1181 pub mod W {}
1182 /// Read-write values (empty)
1183 pub mod RW {}
1184 }
1185
1186 /// CC1S
1187 pub mod CC1S {
1188 /// Offset (0 bits)
1189 pub const offset: u32 = 0;
1190 /// Mask (2 bits: 0b11 << 0)
1191 pub const mask: u32 = 0b11 << offset;
1192 /// Read-only values (empty)
1193 pub mod R {}
1194 /// Write-only values (empty)
1195 pub mod W {}
1196 /// Read-write values
1197 pub mod RW {
1198
1199 /// 0b00: CC1 channel is configured as output
1200 pub const Output: u32 = 0b00;
1201 }
1202 }
1203
1204 /// Output Compare 2 mode - bit 3
1205 pub mod OC2M_3 {
1206 /// Offset (24 bits)
1207 pub const offset: u32 = 24;
1208 /// Mask (1 bit: 1 << 24)
1209 pub const mask: u32 = 1 << offset;
1210 /// Read-only values (empty)
1211 pub mod R {}
1212 /// Write-only values (empty)
1213 pub mod W {}
1214 /// Read-write values
1215 pub mod RW {
1216
1217 /// 0b0: Normal output compare mode (modes 0-7)
1218 pub const Normal: u32 = 0b0;
1219
1220 /// 0b1: Extended output compare mode (modes 7-15)
1221 pub const Extended: u32 = 0b1;
1222 }
1223 }
1224
1225 /// Output Compare 1 mode - bit 3
1226 pub mod OC1M_3 {
1227 /// Offset (16 bits)
1228 pub const offset: u32 = 16;
1229 /// Mask (1 bit: 1 << 16)
1230 pub const mask: u32 = 1 << offset;
1231 /// Read-only values (empty)
1232 pub mod R {}
1233 /// Write-only values (empty)
1234 pub mod W {}
1235 pub use super::OC2M_3::RW;
1236 }
1237
1238 /// Input capture 2 filter
1239 pub mod IC2F {
1240 /// Offset (12 bits)
1241 pub const offset: u32 = 12;
1242 /// Mask (4 bits: 0b1111 << 12)
1243 pub const mask: u32 = 0b1111 << offset;
1244 /// Read-only values (empty)
1245 pub mod R {}
1246 /// Write-only values (empty)
1247 pub mod W {}
1248 /// Read-write values (empty)
1249 pub mod RW {}
1250 }
1251
1252 /// Input capture 2 prescaler
1253 pub mod IC2PSC {
1254 /// Offset (10 bits)
1255 pub const offset: u32 = 10;
1256 /// Mask (2 bits: 0b11 << 10)
1257 pub const mask: u32 = 0b11 << offset;
1258 /// Read-only values (empty)
1259 pub mod R {}
1260 /// Write-only values (empty)
1261 pub mod W {}
1262 /// Read-write values (empty)
1263 pub mod RW {}
1264 }
1265
1266 /// Input capture 1 filter
1267 pub mod IC1F {
1268 /// Offset (4 bits)
1269 pub const offset: u32 = 4;
1270 /// Mask (4 bits: 0b1111 << 4)
1271 pub const mask: u32 = 0b1111 << offset;
1272 /// Read-only values (empty)
1273 pub mod R {}
1274 /// Write-only values (empty)
1275 pub mod W {}
1276 /// Read-write values
1277 pub mod RW {
1278
1279 /// 0b0000: No filter, sampling is done at fDTS
1280 pub const NoFilter: u32 = 0b0000;
1281
1282 /// 0b0001: fSAMPLING=fCK_INT, N=2
1283 pub const FCK_INT_N2: u32 = 0b0001;
1284
1285 /// 0b0010: fSAMPLING=fCK_INT, N=4
1286 pub const FCK_INT_N4: u32 = 0b0010;
1287
1288 /// 0b0011: fSAMPLING=fCK_INT, N=8
1289 pub const FCK_INT_N8: u32 = 0b0011;
1290
1291 /// 0b0100: fSAMPLING=fDTS/2, N=6
1292 pub const FDTS_Div2_N6: u32 = 0b0100;
1293
1294 /// 0b0101: fSAMPLING=fDTS/2, N=8
1295 pub const FDTS_Div2_N8: u32 = 0b0101;
1296
1297 /// 0b0110: fSAMPLING=fDTS/4, N=6
1298 pub const FDTS_Div4_N6: u32 = 0b0110;
1299
1300 /// 0b0111: fSAMPLING=fDTS/4, N=8
1301 pub const FDTS_Div4_N8: u32 = 0b0111;
1302
1303 /// 0b1000: fSAMPLING=fDTS/8, N=6
1304 pub const FDTS_Div8_N6: u32 = 0b1000;
1305
1306 /// 0b1001: fSAMPLING=fDTS/8, N=8
1307 pub const FDTS_Div8_N8: u32 = 0b1001;
1308
1309 /// 0b1010: fSAMPLING=fDTS/16, N=5
1310 pub const FDTS_Div16_N5: u32 = 0b1010;
1311
1312 /// 0b1011: fSAMPLING=fDTS/16, N=6
1313 pub const FDTS_Div16_N6: u32 = 0b1011;
1314
1315 /// 0b1100: fSAMPLING=fDTS/16, N=8
1316 pub const FDTS_Div16_N8: u32 = 0b1100;
1317
1318 /// 0b1101: fSAMPLING=fDTS/32, N=5
1319 pub const FDTS_Div32_N5: u32 = 0b1101;
1320
1321 /// 0b1110: fSAMPLING=fDTS/32, N=6
1322 pub const FDTS_Div32_N6: u32 = 0b1110;
1323
1324 /// 0b1111: fSAMPLING=fDTS/32, N=8
1325 pub const FDTS_Div32_N8: u32 = 0b1111;
1326 }
1327 }
1328
1329 /// Input capture 1 prescaler
1330 pub mod IC1PSC {
1331 /// Offset (2 bits)
1332 pub const offset: u32 = 2;
1333 /// Mask (2 bits: 0b11 << 2)
1334 pub const mask: u32 = 0b11 << offset;
1335 /// Read-only values (empty)
1336 pub mod R {}
1337 /// Write-only values (empty)
1338 pub mod W {}
1339 /// Read-write values (empty)
1340 pub mod RW {}
1341 }
1342}
1343
1344/// CCMR2_Output and CCMR2_Input
1345/// CCMR2_Output: capture/compare mode register 2 (output mode)
1346/// CCMR2_Input: capture/compare mode register 2 (input mode)
1347pub mod CCMR2 {
1348
1349 /// O24CE
1350 pub mod OC4CE {
1351 /// Offset (15 bits)
1352 pub const offset: u32 = 15;
1353 /// Mask (1 bit: 1 << 15)
1354 pub const mask: u32 = 1 << offset;
1355 /// Read-only values (empty)
1356 pub mod R {}
1357 /// Write-only values (empty)
1358 pub mod W {}
1359 /// Read-write values (empty)
1360 pub mod RW {}
1361 }
1362
1363 /// OC4M
1364 pub mod OC4M {
1365 /// Offset (12 bits)
1366 pub const offset: u32 = 12;
1367 /// Mask (3 bits: 0b111 << 12)
1368 pub const mask: u32 = 0b111 << offset;
1369 /// Read-only values (empty)
1370 pub mod R {}
1371 /// Write-only values (empty)
1372 pub mod W {}
1373 /// Read-write values
1374 pub mod RW {
1375
1376 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1377 pub const Frozen: u32 = 0b000;
1378
1379 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
1380 pub const ActiveOnMatch: u32 = 0b001;
1381
1382 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
1383 pub const InactiveOnMatch: u32 = 0b010;
1384
1385 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
1386 pub const Toggle: u32 = 0b011;
1387
1388 /// 0b100: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
1389 pub const ForceInactive: u32 = 0b100;
1390
1391 /// 0b101: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
1392 pub const ForceActive: u32 = 0b101;
1393
1394 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
1395 pub const PwmMode1: u32 = 0b110;
1396
1397 /// 0b111: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
1398 pub const PwmMode2: u32 = 0b111;
1399 }
1400 }
1401
1402 /// OC4PE
1403 pub mod OC4PE {
1404 /// Offset (11 bits)
1405 pub const offset: u32 = 11;
1406 /// Mask (1 bit: 1 << 11)
1407 pub const mask: u32 = 1 << offset;
1408 /// Read-only values (empty)
1409 pub mod R {}
1410 /// Write-only values (empty)
1411 pub mod W {}
1412 /// Read-write values
1413 pub mod RW {
1414
1415 /// 0b0: Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately
1416 pub const Disabled: u32 = 0b0;
1417
1418 /// 0b1: Preload register on CCR4 enabled. Preload value is loaded into active register on each update event
1419 pub const Enabled: u32 = 0b1;
1420 }
1421 }
1422
1423 /// OC4FE
1424 pub mod OC4FE {
1425 /// Offset (10 bits)
1426 pub const offset: u32 = 10;
1427 /// Mask (1 bit: 1 << 10)
1428 pub const mask: u32 = 1 << offset;
1429 /// Read-only values (empty)
1430 pub mod R {}
1431 /// Write-only values (empty)
1432 pub mod W {}
1433 /// Read-write values (empty)
1434 pub mod RW {}
1435 }
1436
1437 /// CC4S
1438 pub mod CC4S {
1439 /// Offset (8 bits)
1440 pub const offset: u32 = 8;
1441 /// Mask (2 bits: 0b11 << 8)
1442 pub const mask: u32 = 0b11 << offset;
1443 /// Read-only values (empty)
1444 pub mod R {}
1445 /// Write-only values (empty)
1446 pub mod W {}
1447 /// Read-write values
1448 pub mod RW {
1449
1450 /// 0b00: CC4 channel is configured as output
1451 pub const Output: u32 = 0b00;
1452 }
1453 }
1454
1455 /// OC3CE
1456 pub mod OC3CE {
1457 /// Offset (7 bits)
1458 pub const offset: u32 = 7;
1459 /// Mask (1 bit: 1 << 7)
1460 pub const mask: u32 = 1 << offset;
1461 /// Read-only values (empty)
1462 pub mod R {}
1463 /// Write-only values (empty)
1464 pub mod W {}
1465 /// Read-write values (empty)
1466 pub mod RW {}
1467 }
1468
1469 /// OC3M
1470 pub mod OC3M {
1471 /// Offset (4 bits)
1472 pub const offset: u32 = 4;
1473 /// Mask (3 bits: 0b111 << 4)
1474 pub const mask: u32 = 0b111 << offset;
1475 /// Read-only values (empty)
1476 pub mod R {}
1477 /// Write-only values (empty)
1478 pub mod W {}
1479 pub use super::OC4M::RW;
1480 }
1481
1482 /// OC3PE
1483 pub mod OC3PE {
1484 /// Offset (3 bits)
1485 pub const offset: u32 = 3;
1486 /// Mask (1 bit: 1 << 3)
1487 pub const mask: u32 = 1 << offset;
1488 /// Read-only values (empty)
1489 pub mod R {}
1490 /// Write-only values (empty)
1491 pub mod W {}
1492 /// Read-write values
1493 pub mod RW {
1494
1495 /// 0b0: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1496 pub const Disabled: u32 = 0b0;
1497
1498 /// 0b1: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
1499 pub const Enabled: u32 = 0b1;
1500 }
1501 }
1502
1503 /// OC3FE
1504 pub mod OC3FE {
1505 /// Offset (2 bits)
1506 pub const offset: u32 = 2;
1507 /// Mask (1 bit: 1 << 2)
1508 pub const mask: u32 = 1 << offset;
1509 /// Read-only values (empty)
1510 pub mod R {}
1511 /// Write-only values (empty)
1512 pub mod W {}
1513 /// Read-write values (empty)
1514 pub mod RW {}
1515 }
1516
1517 /// CC3S
1518 pub mod CC3S {
1519 /// Offset (0 bits)
1520 pub const offset: u32 = 0;
1521 /// Mask (2 bits: 0b11 << 0)
1522 pub const mask: u32 = 0b11 << offset;
1523 /// Read-only values (empty)
1524 pub mod R {}
1525 /// Write-only values (empty)
1526 pub mod W {}
1527 /// Read-write values
1528 pub mod RW {
1529
1530 /// 0b00: CC3 channel is configured as output
1531 pub const Output: u32 = 0b00;
1532 }
1533 }
1534
1535 /// Output Compare 2 mode - bit 3
1536 pub mod OC4M_3 {
1537 /// Offset (24 bits)
1538 pub const offset: u32 = 24;
1539 /// Mask (1 bit: 1 << 24)
1540 pub const mask: u32 = 1 << offset;
1541 /// Read-only values (empty)
1542 pub mod R {}
1543 /// Write-only values (empty)
1544 pub mod W {}
1545 /// Read-write values
1546 pub mod RW {
1547
1548 /// 0b0: Normal output compare mode (modes 0-7)
1549 pub const Normal: u32 = 0b0;
1550
1551 /// 0b1: Extended output compare mode (modes 7-15)
1552 pub const Extended: u32 = 0b1;
1553 }
1554 }
1555
1556 /// Output Compare 1 mode - bit 3
1557 pub mod OC3M_3 {
1558 /// Offset (16 bits)
1559 pub const offset: u32 = 16;
1560 /// Mask (1 bit: 1 << 16)
1561 pub const mask: u32 = 1 << offset;
1562 /// Read-only values (empty)
1563 pub mod R {}
1564 /// Write-only values (empty)
1565 pub mod W {}
1566 pub use super::OC4M_3::RW;
1567 }
1568
1569 /// Input capture 4 filter
1570 pub mod IC4F {
1571 /// Offset (12 bits)
1572 pub const offset: u32 = 12;
1573 /// Mask (4 bits: 0b1111 << 12)
1574 pub const mask: u32 = 0b1111 << offset;
1575 /// Read-only values (empty)
1576 pub mod R {}
1577 /// Write-only values (empty)
1578 pub mod W {}
1579 /// Read-write values (empty)
1580 pub mod RW {}
1581 }
1582
1583 /// Input capture 4 prescaler
1584 pub mod IC4PSC {
1585 /// Offset (10 bits)
1586 pub const offset: u32 = 10;
1587 /// Mask (2 bits: 0b11 << 10)
1588 pub const mask: u32 = 0b11 << offset;
1589 /// Read-only values (empty)
1590 pub mod R {}
1591 /// Write-only values (empty)
1592 pub mod W {}
1593 /// Read-write values (empty)
1594 pub mod RW {}
1595 }
1596
1597 /// Input capture 3 filter
1598 pub mod IC3F {
1599 /// Offset (4 bits)
1600 pub const offset: u32 = 4;
1601 /// Mask (4 bits: 0b1111 << 4)
1602 pub const mask: u32 = 0b1111 << offset;
1603 /// Read-only values (empty)
1604 pub mod R {}
1605 /// Write-only values (empty)
1606 pub mod W {}
1607 /// Read-write values (empty)
1608 pub mod RW {}
1609 }
1610
1611 /// Input capture 3 prescaler
1612 pub mod IC3PSC {
1613 /// Offset (2 bits)
1614 pub const offset: u32 = 2;
1615 /// Mask (2 bits: 0b11 << 2)
1616 pub const mask: u32 = 0b11 << offset;
1617 /// Read-only values (empty)
1618 pub mod R {}
1619 /// Write-only values (empty)
1620 pub mod W {}
1621 /// Read-write values (empty)
1622 pub mod RW {}
1623 }
1624}
1625
1626/// capture/compare enable register
1627pub mod CCER {
1628
1629 /// Capture/Compare 4 output Polarity
1630 pub mod CC4NP {
1631 /// Offset (15 bits)
1632 pub const offset: u32 = 15;
1633 /// Mask (1 bit: 1 << 15)
1634 pub const mask: u32 = 1 << offset;
1635 /// Read-only values (empty)
1636 pub mod R {}
1637 /// Write-only values (empty)
1638 pub mod W {}
1639 /// Read-write values (empty)
1640 pub mod RW {}
1641 }
1642
1643 /// Capture/Compare 3 output Polarity
1644 pub mod CC4P {
1645 /// Offset (13 bits)
1646 pub const offset: u32 = 13;
1647 /// Mask (1 bit: 1 << 13)
1648 pub const mask: u32 = 1 << offset;
1649 /// Read-only values (empty)
1650 pub mod R {}
1651 /// Write-only values (empty)
1652 pub mod W {}
1653 /// Read-write values (empty)
1654 pub mod RW {}
1655 }
1656
1657 /// Capture/Compare 4 output enable
1658 pub mod CC4E {
1659 /// Offset (12 bits)
1660 pub const offset: u32 = 12;
1661 /// Mask (1 bit: 1 << 12)
1662 pub const mask: u32 = 1 << offset;
1663 /// Read-only values (empty)
1664 pub mod R {}
1665 /// Write-only values (empty)
1666 pub mod W {}
1667 /// Read-write values (empty)
1668 pub mod RW {}
1669 }
1670
1671 /// Capture/Compare 3 output Polarity
1672 pub mod CC3NP {
1673 /// Offset (11 bits)
1674 pub const offset: u32 = 11;
1675 /// Mask (1 bit: 1 << 11)
1676 pub const mask: u32 = 1 << offset;
1677 /// Read-only values (empty)
1678 pub mod R {}
1679 /// Write-only values (empty)
1680 pub mod W {}
1681 /// Read-write values (empty)
1682 pub mod RW {}
1683 }
1684
1685 /// Capture/Compare 3 output Polarity
1686 pub mod CC3P {
1687 /// Offset (9 bits)
1688 pub const offset: u32 = 9;
1689 /// Mask (1 bit: 1 << 9)
1690 pub const mask: u32 = 1 << offset;
1691 /// Read-only values (empty)
1692 pub mod R {}
1693 /// Write-only values (empty)
1694 pub mod W {}
1695 /// Read-write values (empty)
1696 pub mod RW {}
1697 }
1698
1699 /// Capture/Compare 3 output enable
1700 pub mod CC3E {
1701 /// Offset (8 bits)
1702 pub const offset: u32 = 8;
1703 /// Mask (1 bit: 1 << 8)
1704 pub const mask: u32 = 1 << offset;
1705 /// Read-only values (empty)
1706 pub mod R {}
1707 /// Write-only values (empty)
1708 pub mod W {}
1709 /// Read-write values (empty)
1710 pub mod RW {}
1711 }
1712
1713 /// Capture/Compare 2 output Polarity
1714 pub mod CC2NP {
1715 /// Offset (7 bits)
1716 pub const offset: u32 = 7;
1717 /// Mask (1 bit: 1 << 7)
1718 pub const mask: u32 = 1 << offset;
1719 /// Read-only values (empty)
1720 pub mod R {}
1721 /// Write-only values (empty)
1722 pub mod W {}
1723 /// Read-write values (empty)
1724 pub mod RW {}
1725 }
1726
1727 /// Capture/Compare 2 output Polarity
1728 pub mod CC2P {
1729 /// Offset (5 bits)
1730 pub const offset: u32 = 5;
1731 /// Mask (1 bit: 1 << 5)
1732 pub const mask: u32 = 1 << offset;
1733 /// Read-only values (empty)
1734 pub mod R {}
1735 /// Write-only values (empty)
1736 pub mod W {}
1737 /// Read-write values (empty)
1738 pub mod RW {}
1739 }
1740
1741 /// Capture/Compare 2 output enable
1742 pub mod CC2E {
1743 /// Offset (4 bits)
1744 pub const offset: u32 = 4;
1745 /// Mask (1 bit: 1 << 4)
1746 pub const mask: u32 = 1 << offset;
1747 /// Read-only values (empty)
1748 pub mod R {}
1749 /// Write-only values (empty)
1750 pub mod W {}
1751 /// Read-write values (empty)
1752 pub mod RW {}
1753 }
1754
1755 /// Capture/Compare 1 output Polarity
1756 pub mod CC1NP {
1757 /// Offset (3 bits)
1758 pub const offset: u32 = 3;
1759 /// Mask (1 bit: 1 << 3)
1760 pub const mask: u32 = 1 << offset;
1761 /// Read-only values (empty)
1762 pub mod R {}
1763 /// Write-only values (empty)
1764 pub mod W {}
1765 /// Read-write values (empty)
1766 pub mod RW {}
1767 }
1768
1769 /// Capture/Compare 1 output Polarity
1770 pub mod CC1P {
1771 /// Offset (1 bits)
1772 pub const offset: u32 = 1;
1773 /// Mask (1 bit: 1 << 1)
1774 pub const mask: u32 = 1 << offset;
1775 /// Read-only values (empty)
1776 pub mod R {}
1777 /// Write-only values (empty)
1778 pub mod W {}
1779 /// Read-write values (empty)
1780 pub mod RW {}
1781 }
1782
1783 /// Capture/Compare 1 output enable
1784 pub mod CC1E {
1785 /// Offset (0 bits)
1786 pub const offset: u32 = 0;
1787 /// Mask (1 bit: 1 << 0)
1788 pub const mask: u32 = 1 << offset;
1789 /// Read-only values (empty)
1790 pub mod R {}
1791 /// Write-only values (empty)
1792 pub mod W {}
1793 /// Read-write values (empty)
1794 pub mod RW {}
1795 }
1796}
1797
1798/// counter
1799pub mod CNT {
1800
1801 /// Counter value
1802 pub mod CNT {
1803 /// Offset (0 bits)
1804 pub const offset: u32 = 0;
1805 /// Mask (32 bits: 0xffffffff << 0)
1806 pub const mask: u32 = 0xffffffff << offset;
1807 /// Read-only values (empty)
1808 pub mod R {}
1809 /// Write-only values (empty)
1810 pub mod W {}
1811 /// Read-write values (empty)
1812 pub mod RW {}
1813 }
1814
1815 /// UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0
1816 pub mod UIFCPY {
1817 /// Offset (31 bits)
1818 pub const offset: u32 = 31;
1819 /// Mask (1 bit: 1 << 31)
1820 pub const mask: u32 = 1 << offset;
1821 /// Read-only values (empty)
1822 pub mod R {}
1823 /// Write-only values (empty)
1824 pub mod W {}
1825 /// Read-write values (empty)
1826 pub mod RW {}
1827 }
1828}
1829
1830/// prescaler
1831pub mod PSC {
1832
1833 /// Prescaler value
1834 pub mod PSC {
1835 /// Offset (0 bits)
1836 pub const offset: u32 = 0;
1837 /// Mask (16 bits: 0xffff << 0)
1838 pub const mask: u32 = 0xffff << offset;
1839 /// Read-only values (empty)
1840 pub mod R {}
1841 /// Write-only values (empty)
1842 pub mod W {}
1843 /// Read-write values (empty)
1844 pub mod RW {}
1845 }
1846}
1847
1848/// auto-reload register
1849pub mod ARR {
1850
1851 /// Auto-reload value
1852 pub mod ARR {
1853 /// Offset (0 bits)
1854 pub const offset: u32 = 0;
1855 /// Mask (32 bits: 0xffffffff << 0)
1856 pub const mask: u32 = 0xffffffff << offset;
1857 /// Read-only values (empty)
1858 pub mod R {}
1859 /// Write-only values (empty)
1860 pub mod W {}
1861 /// Read-write values (empty)
1862 pub mod RW {}
1863 }
1864}
1865
1866/// capture/compare register
1867pub mod CCR1 {
1868
1869 /// Capture/Compare value
1870 pub mod CCR {
1871 /// Offset (0 bits)
1872 pub const offset: u32 = 0;
1873 /// Mask (32 bits: 0xffffffff << 0)
1874 pub const mask: u32 = 0xffffffff << offset;
1875 /// Read-only values (empty)
1876 pub mod R {}
1877 /// Write-only values (empty)
1878 pub mod W {}
1879 /// Read-write values (empty)
1880 pub mod RW {}
1881 }
1882}
1883
1884/// capture/compare register
1885pub mod CCR2 {
1886 pub use super::CCR1::CCR;
1887}
1888
1889/// capture/compare register
1890pub mod CCR3 {
1891 pub use super::CCR1::CCR;
1892}
1893
1894/// capture/compare register
1895pub mod CCR4 {
1896 pub use super::CCR1::CCR;
1897}
1898
1899/// DMA control register
1900pub mod DCR {
1901
1902 /// DMA burst length
1903 pub mod DBL {
1904 /// Offset (8 bits)
1905 pub const offset: u32 = 8;
1906 /// Mask (5 bits: 0b11111 << 8)
1907 pub const mask: u32 = 0b11111 << offset;
1908 /// Read-only values (empty)
1909 pub mod R {}
1910 /// Write-only values (empty)
1911 pub mod W {}
1912 /// Read-write values (empty)
1913 pub mod RW {}
1914 }
1915
1916 /// DMA base address
1917 pub mod DBA {
1918 /// Offset (0 bits)
1919 pub const offset: u32 = 0;
1920 /// Mask (5 bits: 0b11111 << 0)
1921 pub const mask: u32 = 0b11111 << offset;
1922 /// Read-only values (empty)
1923 pub mod R {}
1924 /// Write-only values (empty)
1925 pub mod W {}
1926 /// Read-write values (empty)
1927 pub mod RW {}
1928 }
1929}
1930
1931/// DMA address for full transfer
1932pub mod DMAR {
1933
1934 /// DMA register for burst accesses
1935 pub mod DMAB {
1936 /// Offset (0 bits)
1937 pub const offset: u32 = 0;
1938 /// Mask (32 bits: 0xffffffff << 0)
1939 pub const mask: u32 = 0xffffffff << offset;
1940 /// Read-only values (empty)
1941 pub mod R {}
1942 /// Write-only values (empty)
1943 pub mod W {}
1944 /// Read-write values (empty)
1945 pub mod RW {}
1946 }
1947}
1948
1949/// option register 1
1950pub mod OR {
1951
1952 /// Timer Input 4 remap
1953 pub mod TI4_RMP {
1954 /// Offset (6 bits)
1955 pub const offset: u32 = 6;
1956 /// Mask (2 bits: 0b11 << 6)
1957 pub const mask: u32 = 0b11 << offset;
1958 /// Read-only values (empty)
1959 pub mod R {}
1960 /// Write-only values (empty)
1961 pub mod W {}
1962 /// Read-write values (empty)
1963 pub mod RW {}
1964 }
1965}
1966#[repr(C)]
1967pub struct RegisterBlock {
1968 /// control register 1
1969 pub CR1: RWRegister<u32>,
1970
1971 /// control register 2
1972 pub CR2: RWRegister<u32>,
1973
1974 /// slave mode control register
1975 pub SMCR: RWRegister<u32>,
1976
1977 /// DMA/Interrupt enable register
1978 pub DIER: RWRegister<u32>,
1979
1980 /// status register
1981 pub SR: RWRegister<u32>,
1982
1983 /// event generation register
1984 pub EGR: WORegister<u32>,
1985
1986 /// CCMR1_Output and CCMR1_Input
1987 /// CCMR1_Output: capture/compare mode register 1 (output mode)
1988 /// CCMR1_Input: capture/compare mode register 1 (input mode)
1989 pub CCMR1: RWRegister<u32>,
1990
1991 /// CCMR2_Output and CCMR2_Input
1992 /// CCMR2_Output: capture/compare mode register 2 (output mode)
1993 /// CCMR2_Input: capture/compare mode register 2 (input mode)
1994 pub CCMR2: RWRegister<u32>,
1995
1996 /// capture/compare enable register
1997 pub CCER: RWRegister<u32>,
1998
1999 /// counter
2000 pub CNT: RWRegister<u32>,
2001
2002 /// prescaler
2003 pub PSC: RWRegister<u32>,
2004
2005 /// auto-reload register
2006 pub ARR: RWRegister<u32>,
2007
2008 _reserved1: [u8; 4],
2009
2010 /// capture/compare register
2011 pub CCR1: RWRegister<u32>,
2012
2013 /// capture/compare register
2014 pub CCR2: RWRegister<u32>,
2015
2016 /// capture/compare register
2017 pub CCR3: RWRegister<u32>,
2018
2019 /// capture/compare register
2020 pub CCR4: RWRegister<u32>,
2021
2022 _reserved2: [u8; 4],
2023
2024 /// DMA control register
2025 pub DCR: RWRegister<u32>,
2026
2027 /// DMA address for full transfer
2028 pub DMAR: RWRegister<u32>,
2029
2030 /// option register 1
2031 pub OR: RWRegister<u32>,
2032}
2033pub struct ResetValues {
2034 pub CR1: u32,
2035 pub CR2: u32,
2036 pub SMCR: u32,
2037 pub DIER: u32,
2038 pub SR: u32,
2039 pub EGR: u32,
2040 pub CCMR1: u32,
2041 pub CCMR2: u32,
2042 pub CCER: u32,
2043 pub CNT: u32,
2044 pub PSC: u32,
2045 pub ARR: u32,
2046 pub CCR1: u32,
2047 pub CCR2: u32,
2048 pub CCR3: u32,
2049 pub CCR4: u32,
2050 pub DCR: u32,
2051 pub DMAR: u32,
2052 pub OR: u32,
2053}
2054#[cfg(not(feature = "nosync"))]
2055pub struct Instance {
2056 pub(crate) addr: u32,
2057 pub(crate) _marker: PhantomData<*const RegisterBlock>,
2058}
2059#[cfg(not(feature = "nosync"))]
2060impl ::core::ops::Deref for Instance {
2061 type Target = RegisterBlock;
2062 #[inline(always)]
2063 fn deref(&self) -> &RegisterBlock {
2064 unsafe { &*(self.addr as *const _) }
2065 }
2066}
2067#[cfg(feature = "rtic")]
2068unsafe impl Send for Instance {}