stm32ral/stm32f7/peripherals/quadspi.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! QuadSPI interface
4//!
5//! Used by: stm32f730, stm32f745, stm32f750, stm32f765, stm32f7x2, stm32f7x3, stm32f7x6, stm32f7x7, stm32f7x9
6
7use crate::{RORegister, RWRegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// control register
12pub mod CR {
13
14 /// Clock prescaler
15 pub mod PRESCALER {
16 /// Offset (24 bits)
17 pub const offset: u32 = 24;
18 /// Mask (8 bits: 0xff << 24)
19 pub const mask: u32 = 0xff << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values (empty)
25 pub mod RW {}
26 }
27
28 /// Polling match mode
29 pub mod PMM {
30 /// Offset (23 bits)
31 pub const offset: u32 = 23;
32 /// Mask (1 bit: 1 << 23)
33 pub const mask: u32 = 1 << offset;
34 /// Read-only values (empty)
35 pub mod R {}
36 /// Write-only values (empty)
37 pub mod W {}
38 /// Read-write values (empty)
39 pub mod RW {}
40 }
41
42 /// Automatic poll mode stop
43 pub mod APMS {
44 /// Offset (22 bits)
45 pub const offset: u32 = 22;
46 /// Mask (1 bit: 1 << 22)
47 pub const mask: u32 = 1 << offset;
48 /// Read-only values (empty)
49 pub mod R {}
50 /// Write-only values (empty)
51 pub mod W {}
52 /// Read-write values (empty)
53 pub mod RW {}
54 }
55
56 /// TimeOut interrupt enable
57 pub mod TOIE {
58 /// Offset (20 bits)
59 pub const offset: u32 = 20;
60 /// Mask (1 bit: 1 << 20)
61 pub const mask: u32 = 1 << offset;
62 /// Read-only values (empty)
63 pub mod R {}
64 /// Write-only values (empty)
65 pub mod W {}
66 /// Read-write values (empty)
67 pub mod RW {}
68 }
69
70 /// Status match interrupt enable
71 pub mod SMIE {
72 /// Offset (19 bits)
73 pub const offset: u32 = 19;
74 /// Mask (1 bit: 1 << 19)
75 pub const mask: u32 = 1 << offset;
76 /// Read-only values (empty)
77 pub mod R {}
78 /// Write-only values (empty)
79 pub mod W {}
80 /// Read-write values (empty)
81 pub mod RW {}
82 }
83
84 /// FIFO threshold interrupt enable
85 pub mod FTIE {
86 /// Offset (18 bits)
87 pub const offset: u32 = 18;
88 /// Mask (1 bit: 1 << 18)
89 pub const mask: u32 = 1 << offset;
90 /// Read-only values (empty)
91 pub mod R {}
92 /// Write-only values (empty)
93 pub mod W {}
94 /// Read-write values (empty)
95 pub mod RW {}
96 }
97
98 /// Transfer complete interrupt enable
99 pub mod TCIE {
100 /// Offset (17 bits)
101 pub const offset: u32 = 17;
102 /// Mask (1 bit: 1 << 17)
103 pub const mask: u32 = 1 << offset;
104 /// Read-only values (empty)
105 pub mod R {}
106 /// Write-only values (empty)
107 pub mod W {}
108 /// Read-write values (empty)
109 pub mod RW {}
110 }
111
112 /// Transfer error interrupt enable
113 pub mod TEIE {
114 /// Offset (16 bits)
115 pub const offset: u32 = 16;
116 /// Mask (1 bit: 1 << 16)
117 pub const mask: u32 = 1 << offset;
118 /// Read-only values (empty)
119 pub mod R {}
120 /// Write-only values (empty)
121 pub mod W {}
122 /// Read-write values (empty)
123 pub mod RW {}
124 }
125
126 /// IFO threshold level
127 pub mod FTHRES {
128 /// Offset (8 bits)
129 pub const offset: u32 = 8;
130 /// Mask (5 bits: 0b11111 << 8)
131 pub const mask: u32 = 0b11111 << offset;
132 /// Read-only values (empty)
133 pub mod R {}
134 /// Write-only values (empty)
135 pub mod W {}
136 /// Read-write values (empty)
137 pub mod RW {}
138 }
139
140 /// FLASH memory selection
141 pub mod FSEL {
142 /// Offset (7 bits)
143 pub const offset: u32 = 7;
144 /// Mask (1 bit: 1 << 7)
145 pub const mask: u32 = 1 << offset;
146 /// Read-only values (empty)
147 pub mod R {}
148 /// Write-only values (empty)
149 pub mod W {}
150 /// Read-write values (empty)
151 pub mod RW {}
152 }
153
154 /// Dual-flash mode
155 pub mod DFM {
156 /// Offset (6 bits)
157 pub const offset: u32 = 6;
158 /// Mask (1 bit: 1 << 6)
159 pub const mask: u32 = 1 << offset;
160 /// Read-only values (empty)
161 pub mod R {}
162 /// Write-only values (empty)
163 pub mod W {}
164 /// Read-write values (empty)
165 pub mod RW {}
166 }
167
168 /// Sample shift
169 pub mod SSHIFT {
170 /// Offset (4 bits)
171 pub const offset: u32 = 4;
172 /// Mask (1 bit: 1 << 4)
173 pub const mask: u32 = 1 << offset;
174 /// Read-only values (empty)
175 pub mod R {}
176 /// Write-only values (empty)
177 pub mod W {}
178 /// Read-write values (empty)
179 pub mod RW {}
180 }
181
182 /// Timeout counter enable
183 pub mod TCEN {
184 /// Offset (3 bits)
185 pub const offset: u32 = 3;
186 /// Mask (1 bit: 1 << 3)
187 pub const mask: u32 = 1 << offset;
188 /// Read-only values (empty)
189 pub mod R {}
190 /// Write-only values (empty)
191 pub mod W {}
192 /// Read-write values (empty)
193 pub mod RW {}
194 }
195
196 /// DMA enable
197 pub mod DMAEN {
198 /// Offset (2 bits)
199 pub const offset: u32 = 2;
200 /// Mask (1 bit: 1 << 2)
201 pub const mask: u32 = 1 << offset;
202 /// Read-only values (empty)
203 pub mod R {}
204 /// Write-only values (empty)
205 pub mod W {}
206 /// Read-write values (empty)
207 pub mod RW {}
208 }
209
210 /// Abort request
211 pub mod ABORT {
212 /// Offset (1 bits)
213 pub const offset: u32 = 1;
214 /// Mask (1 bit: 1 << 1)
215 pub const mask: u32 = 1 << offset;
216 /// Read-only values (empty)
217 pub mod R {}
218 /// Write-only values (empty)
219 pub mod W {}
220 /// Read-write values (empty)
221 pub mod RW {}
222 }
223
224 /// Enable
225 pub mod EN {
226 /// Offset (0 bits)
227 pub const offset: u32 = 0;
228 /// Mask (1 bit: 1 << 0)
229 pub const mask: u32 = 1 << offset;
230 /// Read-only values (empty)
231 pub mod R {}
232 /// Write-only values (empty)
233 pub mod W {}
234 /// Read-write values (empty)
235 pub mod RW {}
236 }
237}
238
239/// device configuration register
240pub mod DCR {
241
242 /// FLASH memory size
243 pub mod FSIZE {
244 /// Offset (16 bits)
245 pub const offset: u32 = 16;
246 /// Mask (5 bits: 0b11111 << 16)
247 pub const mask: u32 = 0b11111 << offset;
248 /// Read-only values (empty)
249 pub mod R {}
250 /// Write-only values (empty)
251 pub mod W {}
252 /// Read-write values (empty)
253 pub mod RW {}
254 }
255
256 /// Chip select high time
257 pub mod CSHT {
258 /// Offset (8 bits)
259 pub const offset: u32 = 8;
260 /// Mask (3 bits: 0b111 << 8)
261 pub const mask: u32 = 0b111 << offset;
262 /// Read-only values (empty)
263 pub mod R {}
264 /// Write-only values (empty)
265 pub mod W {}
266 /// Read-write values (empty)
267 pub mod RW {}
268 }
269
270 /// Mode 0 / mode 3
271 pub mod CKMODE {
272 /// Offset (0 bits)
273 pub const offset: u32 = 0;
274 /// Mask (1 bit: 1 << 0)
275 pub const mask: u32 = 1 << offset;
276 /// Read-only values (empty)
277 pub mod R {}
278 /// Write-only values (empty)
279 pub mod W {}
280 /// Read-write values (empty)
281 pub mod RW {}
282 }
283}
284
285/// status register
286pub mod SR {
287
288 /// FIFO level
289 pub mod FLEVEL {
290 /// Offset (8 bits)
291 pub const offset: u32 = 8;
292 /// Mask (7 bits: 0x7f << 8)
293 pub const mask: u32 = 0x7f << offset;
294 /// Read-only values (empty)
295 pub mod R {}
296 /// Write-only values (empty)
297 pub mod W {}
298 /// Read-write values (empty)
299 pub mod RW {}
300 }
301
302 /// Busy
303 pub mod BUSY {
304 /// Offset (5 bits)
305 pub const offset: u32 = 5;
306 /// Mask (1 bit: 1 << 5)
307 pub const mask: u32 = 1 << offset;
308 /// Read-only values (empty)
309 pub mod R {}
310 /// Write-only values (empty)
311 pub mod W {}
312 /// Read-write values (empty)
313 pub mod RW {}
314 }
315
316 /// Timeout flag
317 pub mod TOF {
318 /// Offset (4 bits)
319 pub const offset: u32 = 4;
320 /// Mask (1 bit: 1 << 4)
321 pub const mask: u32 = 1 << offset;
322 /// Read-only values (empty)
323 pub mod R {}
324 /// Write-only values (empty)
325 pub mod W {}
326 /// Read-write values (empty)
327 pub mod RW {}
328 }
329
330 /// Status match flag
331 pub mod SMF {
332 /// Offset (3 bits)
333 pub const offset: u32 = 3;
334 /// Mask (1 bit: 1 << 3)
335 pub const mask: u32 = 1 << offset;
336 /// Read-only values (empty)
337 pub mod R {}
338 /// Write-only values (empty)
339 pub mod W {}
340 /// Read-write values (empty)
341 pub mod RW {}
342 }
343
344 /// FIFO threshold flag
345 pub mod FTF {
346 /// Offset (2 bits)
347 pub const offset: u32 = 2;
348 /// Mask (1 bit: 1 << 2)
349 pub const mask: u32 = 1 << offset;
350 /// Read-only values (empty)
351 pub mod R {}
352 /// Write-only values (empty)
353 pub mod W {}
354 /// Read-write values (empty)
355 pub mod RW {}
356 }
357
358 /// Transfer complete flag
359 pub mod TCF {
360 /// Offset (1 bits)
361 pub const offset: u32 = 1;
362 /// Mask (1 bit: 1 << 1)
363 pub const mask: u32 = 1 << offset;
364 /// Read-only values (empty)
365 pub mod R {}
366 /// Write-only values (empty)
367 pub mod W {}
368 /// Read-write values (empty)
369 pub mod RW {}
370 }
371
372 /// Transfer error flag
373 pub mod TEF {
374 /// Offset (0 bits)
375 pub const offset: u32 = 0;
376 /// Mask (1 bit: 1 << 0)
377 pub const mask: u32 = 1 << offset;
378 /// Read-only values (empty)
379 pub mod R {}
380 /// Write-only values (empty)
381 pub mod W {}
382 /// Read-write values (empty)
383 pub mod RW {}
384 }
385}
386
387/// flag clear register
388pub mod FCR {
389
390 /// Clear timeout flag
391 pub mod CTOF {
392 /// Offset (4 bits)
393 pub const offset: u32 = 4;
394 /// Mask (1 bit: 1 << 4)
395 pub const mask: u32 = 1 << offset;
396 /// Read-only values (empty)
397 pub mod R {}
398 /// Write-only values (empty)
399 pub mod W {}
400 /// Read-write values (empty)
401 pub mod RW {}
402 }
403
404 /// Clear status match flag
405 pub mod CSMF {
406 /// Offset (3 bits)
407 pub const offset: u32 = 3;
408 /// Mask (1 bit: 1 << 3)
409 pub const mask: u32 = 1 << offset;
410 /// Read-only values (empty)
411 pub mod R {}
412 /// Write-only values (empty)
413 pub mod W {}
414 /// Read-write values (empty)
415 pub mod RW {}
416 }
417
418 /// Clear transfer complete flag
419 pub mod CTCF {
420 /// Offset (1 bits)
421 pub const offset: u32 = 1;
422 /// Mask (1 bit: 1 << 1)
423 pub const mask: u32 = 1 << offset;
424 /// Read-only values (empty)
425 pub mod R {}
426 /// Write-only values (empty)
427 pub mod W {}
428 /// Read-write values (empty)
429 pub mod RW {}
430 }
431
432 /// Clear transfer error flag
433 pub mod CTEF {
434 /// Offset (0 bits)
435 pub const offset: u32 = 0;
436 /// Mask (1 bit: 1 << 0)
437 pub const mask: u32 = 1 << offset;
438 /// Read-only values (empty)
439 pub mod R {}
440 /// Write-only values (empty)
441 pub mod W {}
442 /// Read-write values (empty)
443 pub mod RW {}
444 }
445}
446
447/// data length register
448pub mod DLR {
449
450 /// Data length
451 pub mod DL {
452 /// Offset (0 bits)
453 pub const offset: u32 = 0;
454 /// Mask (32 bits: 0xffffffff << 0)
455 pub const mask: u32 = 0xffffffff << offset;
456 /// Read-only values (empty)
457 pub mod R {}
458 /// Write-only values (empty)
459 pub mod W {}
460 /// Read-write values (empty)
461 pub mod RW {}
462 }
463}
464
465/// communication configuration register
466pub mod CCR {
467
468 /// Double data rate mode
469 pub mod DDRM {
470 /// Offset (31 bits)
471 pub const offset: u32 = 31;
472 /// Mask (1 bit: 1 << 31)
473 pub const mask: u32 = 1 << offset;
474 /// Read-only values (empty)
475 pub mod R {}
476 /// Write-only values (empty)
477 pub mod W {}
478 /// Read-write values (empty)
479 pub mod RW {}
480 }
481
482 /// DDR hold half cycle
483 pub mod DHHC {
484 /// Offset (30 bits)
485 pub const offset: u32 = 30;
486 /// Mask (1 bit: 1 << 30)
487 pub const mask: u32 = 1 << offset;
488 /// Read-only values (empty)
489 pub mod R {}
490 /// Write-only values (empty)
491 pub mod W {}
492 /// Read-write values (empty)
493 pub mod RW {}
494 }
495
496 /// Send instruction only once mode
497 pub mod SIOO {
498 /// Offset (28 bits)
499 pub const offset: u32 = 28;
500 /// Mask (1 bit: 1 << 28)
501 pub const mask: u32 = 1 << offset;
502 /// Read-only values (empty)
503 pub mod R {}
504 /// Write-only values (empty)
505 pub mod W {}
506 /// Read-write values (empty)
507 pub mod RW {}
508 }
509
510 /// Functional mode
511 pub mod FMODE {
512 /// Offset (26 bits)
513 pub const offset: u32 = 26;
514 /// Mask (2 bits: 0b11 << 26)
515 pub const mask: u32 = 0b11 << offset;
516 /// Read-only values (empty)
517 pub mod R {}
518 /// Write-only values (empty)
519 pub mod W {}
520 /// Read-write values (empty)
521 pub mod RW {}
522 }
523
524 /// Data mode
525 pub mod DMODE {
526 /// Offset (24 bits)
527 pub const offset: u32 = 24;
528 /// Mask (2 bits: 0b11 << 24)
529 pub const mask: u32 = 0b11 << offset;
530 /// Read-only values (empty)
531 pub mod R {}
532 /// Write-only values (empty)
533 pub mod W {}
534 /// Read-write values (empty)
535 pub mod RW {}
536 }
537
538 /// Number of dummy cycles
539 pub mod DCYC {
540 /// Offset (18 bits)
541 pub const offset: u32 = 18;
542 /// Mask (5 bits: 0b11111 << 18)
543 pub const mask: u32 = 0b11111 << offset;
544 /// Read-only values (empty)
545 pub mod R {}
546 /// Write-only values (empty)
547 pub mod W {}
548 /// Read-write values (empty)
549 pub mod RW {}
550 }
551
552 /// Alternate bytes size
553 pub mod ABSIZE {
554 /// Offset (16 bits)
555 pub const offset: u32 = 16;
556 /// Mask (2 bits: 0b11 << 16)
557 pub const mask: u32 = 0b11 << offset;
558 /// Read-only values (empty)
559 pub mod R {}
560 /// Write-only values (empty)
561 pub mod W {}
562 /// Read-write values (empty)
563 pub mod RW {}
564 }
565
566 /// Alternate bytes mode
567 pub mod ABMODE {
568 /// Offset (14 bits)
569 pub const offset: u32 = 14;
570 /// Mask (2 bits: 0b11 << 14)
571 pub const mask: u32 = 0b11 << offset;
572 /// Read-only values (empty)
573 pub mod R {}
574 /// Write-only values (empty)
575 pub mod W {}
576 /// Read-write values (empty)
577 pub mod RW {}
578 }
579
580 /// Address size
581 pub mod ADSIZE {
582 /// Offset (12 bits)
583 pub const offset: u32 = 12;
584 /// Mask (2 bits: 0b11 << 12)
585 pub const mask: u32 = 0b11 << offset;
586 /// Read-only values (empty)
587 pub mod R {}
588 /// Write-only values (empty)
589 pub mod W {}
590 /// Read-write values (empty)
591 pub mod RW {}
592 }
593
594 /// Address mode
595 pub mod ADMODE {
596 /// Offset (10 bits)
597 pub const offset: u32 = 10;
598 /// Mask (2 bits: 0b11 << 10)
599 pub const mask: u32 = 0b11 << offset;
600 /// Read-only values (empty)
601 pub mod R {}
602 /// Write-only values (empty)
603 pub mod W {}
604 /// Read-write values (empty)
605 pub mod RW {}
606 }
607
608 /// Instruction mode
609 pub mod IMODE {
610 /// Offset (8 bits)
611 pub const offset: u32 = 8;
612 /// Mask (2 bits: 0b11 << 8)
613 pub const mask: u32 = 0b11 << offset;
614 /// Read-only values (empty)
615 pub mod R {}
616 /// Write-only values (empty)
617 pub mod W {}
618 /// Read-write values (empty)
619 pub mod RW {}
620 }
621
622 /// Instruction
623 pub mod INSTRUCTION {
624 /// Offset (0 bits)
625 pub const offset: u32 = 0;
626 /// Mask (8 bits: 0xff << 0)
627 pub const mask: u32 = 0xff << offset;
628 /// Read-only values (empty)
629 pub mod R {}
630 /// Write-only values (empty)
631 pub mod W {}
632 /// Read-write values (empty)
633 pub mod RW {}
634 }
635}
636
637/// address register
638pub mod AR {
639
640 /// Address
641 pub mod ADDRESS {
642 /// Offset (0 bits)
643 pub const offset: u32 = 0;
644 /// Mask (32 bits: 0xffffffff << 0)
645 pub const mask: u32 = 0xffffffff << offset;
646 /// Read-only values (empty)
647 pub mod R {}
648 /// Write-only values (empty)
649 pub mod W {}
650 /// Read-write values (empty)
651 pub mod RW {}
652 }
653}
654
655/// ABR
656pub mod ABR {
657
658 /// ALTERNATE
659 pub mod ALTERNATE {
660 /// Offset (0 bits)
661 pub const offset: u32 = 0;
662 /// Mask (32 bits: 0xffffffff << 0)
663 pub const mask: u32 = 0xffffffff << offset;
664 /// Read-only values (empty)
665 pub mod R {}
666 /// Write-only values (empty)
667 pub mod W {}
668 /// Read-write values (empty)
669 pub mod RW {}
670 }
671}
672
673/// data register
674pub mod DR {
675
676 /// Data
677 pub mod DATA {
678 /// Offset (0 bits)
679 pub const offset: u32 = 0;
680 /// Mask (32 bits: 0xffffffff << 0)
681 pub const mask: u32 = 0xffffffff << offset;
682 /// Read-only values (empty)
683 pub mod R {}
684 /// Write-only values (empty)
685 pub mod W {}
686 /// Read-write values (empty)
687 pub mod RW {}
688 }
689}
690
691/// polling status mask register
692pub mod PSMKR {
693
694 /// Status mask
695 pub mod MASK {
696 /// Offset (0 bits)
697 pub const offset: u32 = 0;
698 /// Mask (32 bits: 0xffffffff << 0)
699 pub const mask: u32 = 0xffffffff << offset;
700 /// Read-only values (empty)
701 pub mod R {}
702 /// Write-only values (empty)
703 pub mod W {}
704 /// Read-write values (empty)
705 pub mod RW {}
706 }
707}
708
709/// polling status match register
710pub mod PSMAR {
711
712 /// Status match
713 pub mod MATCH {
714 /// Offset (0 bits)
715 pub const offset: u32 = 0;
716 /// Mask (32 bits: 0xffffffff << 0)
717 pub const mask: u32 = 0xffffffff << offset;
718 /// Read-only values (empty)
719 pub mod R {}
720 /// Write-only values (empty)
721 pub mod W {}
722 /// Read-write values (empty)
723 pub mod RW {}
724 }
725}
726
727/// polling interval register
728pub mod PIR {
729
730 /// Polling interval
731 pub mod INTERVAL {
732 /// Offset (0 bits)
733 pub const offset: u32 = 0;
734 /// Mask (16 bits: 0xffff << 0)
735 pub const mask: u32 = 0xffff << offset;
736 /// Read-only values (empty)
737 pub mod R {}
738 /// Write-only values (empty)
739 pub mod W {}
740 /// Read-write values (empty)
741 pub mod RW {}
742 }
743}
744
745/// low-power timeout register
746pub mod LPTR {
747
748 /// Timeout period
749 pub mod TIMEOUT {
750 /// Offset (0 bits)
751 pub const offset: u32 = 0;
752 /// Mask (16 bits: 0xffff << 0)
753 pub const mask: u32 = 0xffff << offset;
754 /// Read-only values (empty)
755 pub mod R {}
756 /// Write-only values (empty)
757 pub mod W {}
758 /// Read-write values (empty)
759 pub mod RW {}
760 }
761}
762#[repr(C)]
763pub struct RegisterBlock {
764 /// control register
765 pub CR: RWRegister<u32>,
766
767 /// device configuration register
768 pub DCR: RWRegister<u32>,
769
770 /// status register
771 pub SR: RORegister<u32>,
772
773 /// flag clear register
774 pub FCR: RWRegister<u32>,
775
776 /// data length register
777 pub DLR: RWRegister<u32>,
778
779 /// communication configuration register
780 pub CCR: RWRegister<u32>,
781
782 /// address register
783 pub AR: RWRegister<u32>,
784
785 /// ABR
786 pub ABR: RWRegister<u32>,
787
788 /// data register
789 pub DR: RWRegister<u32>,
790
791 /// polling status mask register
792 pub PSMKR: RWRegister<u32>,
793
794 /// polling status match register
795 pub PSMAR: RWRegister<u32>,
796
797 /// polling interval register
798 pub PIR: RWRegister<u32>,
799
800 /// low-power timeout register
801 pub LPTR: RWRegister<u32>,
802}
803pub struct ResetValues {
804 pub CR: u32,
805 pub DCR: u32,
806 pub SR: u32,
807 pub FCR: u32,
808 pub DLR: u32,
809 pub CCR: u32,
810 pub AR: u32,
811 pub ABR: u32,
812 pub DR: u32,
813 pub PSMKR: u32,
814 pub PSMAR: u32,
815 pub PIR: u32,
816 pub LPTR: u32,
817}
818#[cfg(not(feature = "nosync"))]
819pub struct Instance {
820 pub(crate) addr: u32,
821 pub(crate) _marker: PhantomData<*const RegisterBlock>,
822}
823#[cfg(not(feature = "nosync"))]
824impl ::core::ops::Deref for Instance {
825 type Target = RegisterBlock;
826 #[inline(always)]
827 fn deref(&self) -> &RegisterBlock {
828 unsafe { &*(self.addr as *const _) }
829 }
830}
831#[cfg(feature = "rtic")]
832unsafe impl Send for Instance {}