stm32ral/stm32f4/stm32f446/rcc.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Reset and clock control
4
5use crate::RWRegister;
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// clock control register
10pub mod CR {
11
12 /// PLLI2S clock ready flag
13 pub mod PLLI2SRDY {
14 /// Offset (27 bits)
15 pub const offset: u32 = 27;
16 /// Mask (1 bit: 1 << 27)
17 pub const mask: u32 = 1 << offset;
18 /// Read-only values
19 pub mod R {
20
21 /// 0b0: Clock not ready
22 pub const NotReady: u32 = 0b0;
23
24 /// 0b1: Clock ready
25 pub const Ready: u32 = 0b1;
26 }
27 /// Write-only values (empty)
28 pub mod W {}
29 /// Read-write values (empty)
30 pub mod RW {}
31 }
32
33 /// PLLI2S enable
34 pub mod PLLI2SON {
35 /// Offset (26 bits)
36 pub const offset: u32 = 26;
37 /// Mask (1 bit: 1 << 26)
38 pub const mask: u32 = 1 << offset;
39 /// Read-only values (empty)
40 pub mod R {}
41 /// Write-only values (empty)
42 pub mod W {}
43 /// Read-write values
44 pub mod RW {
45
46 /// 0b0: Clock Off
47 pub const Off: u32 = 0b0;
48
49 /// 0b1: Clock On
50 pub const On: u32 = 0b1;
51 }
52 }
53
54 /// Main PLL (PLL) clock ready flag
55 pub mod PLLRDY {
56 /// Offset (25 bits)
57 pub const offset: u32 = 25;
58 /// Mask (1 bit: 1 << 25)
59 pub const mask: u32 = 1 << offset;
60 pub use super::PLLI2SRDY::R;
61 /// Write-only values (empty)
62 pub mod W {}
63 /// Read-write values (empty)
64 pub mod RW {}
65 }
66
67 /// Main PLL (PLL) enable
68 pub mod PLLON {
69 /// Offset (24 bits)
70 pub const offset: u32 = 24;
71 /// Mask (1 bit: 1 << 24)
72 pub const mask: u32 = 1 << offset;
73 /// Read-only values (empty)
74 pub mod R {}
75 /// Write-only values (empty)
76 pub mod W {}
77 pub use super::PLLI2SON::RW;
78 }
79
80 /// Clock security system enable
81 pub mod CSSON {
82 /// Offset (19 bits)
83 pub const offset: u32 = 19;
84 /// Mask (1 bit: 1 << 19)
85 pub const mask: u32 = 1 << offset;
86 /// Read-only values (empty)
87 pub mod R {}
88 /// Write-only values (empty)
89 pub mod W {}
90 /// Read-write values
91 pub mod RW {
92
93 /// 0b0: Clock security system disabled (clock detector OFF)
94 pub const Off: u32 = 0b0;
95
96 /// 0b1: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)
97 pub const On: u32 = 0b1;
98 }
99 }
100
101 /// HSE clock bypass
102 pub mod HSEBYP {
103 /// Offset (18 bits)
104 pub const offset: u32 = 18;
105 /// Mask (1 bit: 1 << 18)
106 pub const mask: u32 = 1 << offset;
107 /// Read-only values (empty)
108 pub mod R {}
109 /// Write-only values (empty)
110 pub mod W {}
111 /// Read-write values
112 pub mod RW {
113
114 /// 0b0: HSE crystal oscillator not bypassed
115 pub const NotBypassed: u32 = 0b0;
116
117 /// 0b1: HSE crystal oscillator bypassed with external clock
118 pub const Bypassed: u32 = 0b1;
119 }
120 }
121
122 /// HSE clock ready flag
123 pub mod HSERDY {
124 /// Offset (17 bits)
125 pub const offset: u32 = 17;
126 /// Mask (1 bit: 1 << 17)
127 pub const mask: u32 = 1 << offset;
128 pub use super::PLLI2SRDY::R;
129 /// Write-only values (empty)
130 pub mod W {}
131 /// Read-write values (empty)
132 pub mod RW {}
133 }
134
135 /// HSE clock enable
136 pub mod HSEON {
137 /// Offset (16 bits)
138 pub const offset: u32 = 16;
139 /// Mask (1 bit: 1 << 16)
140 pub const mask: u32 = 1 << offset;
141 /// Read-only values (empty)
142 pub mod R {}
143 /// Write-only values (empty)
144 pub mod W {}
145 pub use super::PLLI2SON::RW;
146 }
147
148 /// Internal high-speed clock calibration
149 pub mod HSICAL {
150 /// Offset (8 bits)
151 pub const offset: u32 = 8;
152 /// Mask (8 bits: 0xff << 8)
153 pub const mask: u32 = 0xff << offset;
154 /// Read-only values (empty)
155 pub mod R {}
156 /// Write-only values (empty)
157 pub mod W {}
158 /// Read-write values (empty)
159 pub mod RW {}
160 }
161
162 /// Internal high-speed clock trimming
163 pub mod HSITRIM {
164 /// Offset (3 bits)
165 pub const offset: u32 = 3;
166 /// Mask (5 bits: 0b11111 << 3)
167 pub const mask: u32 = 0b11111 << offset;
168 /// Read-only values (empty)
169 pub mod R {}
170 /// Write-only values (empty)
171 pub mod W {}
172 /// Read-write values (empty)
173 pub mod RW {}
174 }
175
176 /// Internal high-speed clock ready flag
177 pub mod HSIRDY {
178 /// Offset (1 bits)
179 pub const offset: u32 = 1;
180 /// Mask (1 bit: 1 << 1)
181 pub const mask: u32 = 1 << offset;
182 pub use super::PLLI2SRDY::R;
183 /// Write-only values (empty)
184 pub mod W {}
185 /// Read-write values (empty)
186 pub mod RW {}
187 }
188
189 /// Internal high-speed clock enable
190 pub mod HSION {
191 /// Offset (0 bits)
192 pub const offset: u32 = 0;
193 /// Mask (1 bit: 1 << 0)
194 pub const mask: u32 = 1 << offset;
195 /// Read-only values (empty)
196 pub mod R {}
197 /// Write-only values (empty)
198 pub mod W {}
199 pub use super::PLLI2SON::RW;
200 }
201
202 /// PLLSAI clock ready flag
203 pub mod PLLSAIRDY {
204 /// Offset (29 bits)
205 pub const offset: u32 = 29;
206 /// Mask (1 bit: 1 << 29)
207 pub const mask: u32 = 1 << offset;
208 pub use super::PLLI2SRDY::R;
209 /// Write-only values (empty)
210 pub mod W {}
211 /// Read-write values (empty)
212 pub mod RW {}
213 }
214
215 /// PLLSAI enable
216 pub mod PLLSAION {
217 /// Offset (28 bits)
218 pub const offset: u32 = 28;
219 /// Mask (1 bit: 1 << 28)
220 pub const mask: u32 = 1 << offset;
221 /// Read-only values (empty)
222 pub mod R {}
223 /// Write-only values (empty)
224 pub mod W {}
225 pub use super::PLLI2SON::RW;
226 }
227}
228
229/// PLL configuration register
230pub mod PLLCFGR {
231
232 /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
233 pub mod PLLSRC {
234 /// Offset (22 bits)
235 pub const offset: u32 = 22;
236 /// Mask (1 bit: 1 << 22)
237 pub const mask: u32 = 1 << offset;
238 /// Read-only values (empty)
239 pub mod R {}
240 /// Write-only values (empty)
241 pub mod W {}
242 /// Read-write values
243 pub mod RW {
244
245 /// 0b0: HSI clock selected as PLL and PLLI2S clock entry
246 pub const HSI: u32 = 0b0;
247
248 /// 0b1: HSE oscillator clock selected as PLL and PLLI2S clock entry
249 pub const HSE: u32 = 0b1;
250 }
251 }
252
253 /// Main PLL division factor for I2Ss, SAIs, SYSTEM and SPDIF-Rx clocks
254 pub mod PLLR {
255 /// Offset (28 bits)
256 pub const offset: u32 = 28;
257 /// Mask (3 bits: 0b111 << 28)
258 pub const mask: u32 = 0b111 << offset;
259 /// Read-only values (empty)
260 pub mod R {}
261 /// Write-only values (empty)
262 pub mod W {}
263 /// Read-write values (empty)
264 pub mod RW {}
265 }
266
267 /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
268 pub mod PLLM {
269 /// Offset (0 bits)
270 pub const offset: u32 = 0;
271 /// Mask (6 bits: 0x3f << 0)
272 pub const mask: u32 = 0x3f << offset;
273 /// Read-only values (empty)
274 pub mod R {}
275 /// Write-only values (empty)
276 pub mod W {}
277 /// Read-write values (empty)
278 pub mod RW {}
279 }
280
281 /// Main PLL (PLL) multiplication factor for VCO
282 pub mod PLLN {
283 /// Offset (6 bits)
284 pub const offset: u32 = 6;
285 /// Mask (9 bits: 0x1ff << 6)
286 pub const mask: u32 = 0x1ff << offset;
287 /// Read-only values (empty)
288 pub mod R {}
289 /// Write-only values (empty)
290 pub mod W {}
291 /// Read-write values (empty)
292 pub mod RW {}
293 }
294
295 /// Main PLL (PLL) division factor for main system clock
296 pub mod PLLP {
297 /// Offset (16 bits)
298 pub const offset: u32 = 16;
299 /// Mask (2 bits: 0b11 << 16)
300 pub const mask: u32 = 0b11 << offset;
301 /// Read-only values (empty)
302 pub mod R {}
303 /// Write-only values (empty)
304 pub mod W {}
305 /// Read-write values
306 pub mod RW {
307
308 /// 0b00: PLLP=2
309 pub const Div2: u32 = 0b00;
310
311 /// 0b01: PLLP=4
312 pub const Div4: u32 = 0b01;
313
314 /// 0b10: PLLP=6
315 pub const Div6: u32 = 0b10;
316
317 /// 0b11: PLLP=8
318 pub const Div8: u32 = 0b11;
319 }
320 }
321
322 /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
323 pub mod PLLQ {
324 /// Offset (24 bits)
325 pub const offset: u32 = 24;
326 /// Mask (4 bits: 0b1111 << 24)
327 pub const mask: u32 = 0b1111 << offset;
328 /// Read-only values (empty)
329 pub mod R {}
330 /// Write-only values (empty)
331 pub mod W {}
332 /// Read-write values (empty)
333 pub mod RW {}
334 }
335}
336
337/// clock configuration register
338pub mod CFGR {
339
340 /// Microcontroller clock output 2
341 pub mod MCO2 {
342 /// Offset (30 bits)
343 pub const offset: u32 = 30;
344 /// Mask (2 bits: 0b11 << 30)
345 pub const mask: u32 = 0b11 << offset;
346 /// Read-only values (empty)
347 pub mod R {}
348 /// Write-only values (empty)
349 pub mod W {}
350 /// Read-write values
351 pub mod RW {
352
353 /// 0b00: System clock (SYSCLK) selected
354 pub const SYSCLK: u32 = 0b00;
355
356 /// 0b01: PLLI2S clock selected
357 pub const PLLI2S: u32 = 0b01;
358
359 /// 0b10: HSE oscillator clock selected
360 pub const HSE: u32 = 0b10;
361
362 /// 0b11: PLL clock selected
363 pub const PLL: u32 = 0b11;
364 }
365 }
366
367 /// MCO2 prescaler
368 pub mod MCO2PRE {
369 /// Offset (27 bits)
370 pub const offset: u32 = 27;
371 /// Mask (3 bits: 0b111 << 27)
372 pub const mask: u32 = 0b111 << offset;
373 /// Read-only values (empty)
374 pub mod R {}
375 /// Write-only values (empty)
376 pub mod W {}
377 /// Read-write values
378 pub mod RW {
379
380 /// 0b000: No division
381 pub const Div1: u32 = 0b000;
382
383 /// 0b100: Division by 2
384 pub const Div2: u32 = 0b100;
385
386 /// 0b101: Division by 3
387 pub const Div3: u32 = 0b101;
388
389 /// 0b110: Division by 4
390 pub const Div4: u32 = 0b110;
391
392 /// 0b111: Division by 5
393 pub const Div5: u32 = 0b111;
394 }
395 }
396
397 /// MCO1 prescaler
398 pub mod MCO1PRE {
399 /// Offset (24 bits)
400 pub const offset: u32 = 24;
401 /// Mask (3 bits: 0b111 << 24)
402 pub const mask: u32 = 0b111 << offset;
403 /// Read-only values (empty)
404 pub mod R {}
405 /// Write-only values (empty)
406 pub mod W {}
407 pub use super::MCO2PRE::RW;
408 }
409
410 /// I2S clock selection
411 pub mod I2SSRC {
412 /// Offset (23 bits)
413 pub const offset: u32 = 23;
414 /// Mask (1 bit: 1 << 23)
415 pub const mask: u32 = 1 << offset;
416 /// Read-only values (empty)
417 pub mod R {}
418 /// Write-only values (empty)
419 pub mod W {}
420 /// Read-write values
421 pub mod RW {
422
423 /// 0b0: PLLI2S clock used as I2S clock source
424 pub const PLLI2S: u32 = 0b0;
425
426 /// 0b1: External clock mapped on the I2S_CKIN pin used as I2S clock source
427 pub const CKIN: u32 = 0b1;
428 }
429 }
430
431 /// Microcontroller clock output 1
432 pub mod MCO1 {
433 /// Offset (21 bits)
434 pub const offset: u32 = 21;
435 /// Mask (2 bits: 0b11 << 21)
436 pub const mask: u32 = 0b11 << offset;
437 /// Read-only values (empty)
438 pub mod R {}
439 /// Write-only values (empty)
440 pub mod W {}
441 /// Read-write values
442 pub mod RW {
443
444 /// 0b00: HSI clock selected
445 pub const HSI: u32 = 0b00;
446
447 /// 0b01: LSE oscillator selected
448 pub const LSE: u32 = 0b01;
449
450 /// 0b10: HSE oscillator clock selected
451 pub const HSE: u32 = 0b10;
452
453 /// 0b11: PLL clock selected
454 pub const PLL: u32 = 0b11;
455 }
456 }
457
458 /// HSE division factor for RTC clock
459 pub mod RTCPRE {
460 /// Offset (16 bits)
461 pub const offset: u32 = 16;
462 /// Mask (5 bits: 0b11111 << 16)
463 pub const mask: u32 = 0b11111 << offset;
464 /// Read-only values (empty)
465 pub mod R {}
466 /// Write-only values (empty)
467 pub mod W {}
468 /// Read-write values (empty)
469 pub mod RW {}
470 }
471
472 /// APB high-speed prescaler (APB2)
473 pub mod PPRE2 {
474 /// Offset (13 bits)
475 pub const offset: u32 = 13;
476 /// Mask (3 bits: 0b111 << 13)
477 pub const mask: u32 = 0b111 << offset;
478 /// Read-only values (empty)
479 pub mod R {}
480 /// Write-only values (empty)
481 pub mod W {}
482 /// Read-write values
483 pub mod RW {
484
485 /// 0b000: HCLK not divided
486 pub const Div1: u32 = 0b000;
487
488 /// 0b100: HCLK divided by 2
489 pub const Div2: u32 = 0b100;
490
491 /// 0b101: HCLK divided by 4
492 pub const Div4: u32 = 0b101;
493
494 /// 0b110: HCLK divided by 8
495 pub const Div8: u32 = 0b110;
496
497 /// 0b111: HCLK divided by 16
498 pub const Div16: u32 = 0b111;
499 }
500 }
501
502 /// APB Low speed prescaler (APB1)
503 pub mod PPRE1 {
504 /// Offset (10 bits)
505 pub const offset: u32 = 10;
506 /// Mask (3 bits: 0b111 << 10)
507 pub const mask: u32 = 0b111 << offset;
508 /// Read-only values (empty)
509 pub mod R {}
510 /// Write-only values (empty)
511 pub mod W {}
512 pub use super::PPRE2::RW;
513 }
514
515 /// AHB prescaler
516 pub mod HPRE {
517 /// Offset (4 bits)
518 pub const offset: u32 = 4;
519 /// Mask (4 bits: 0b1111 << 4)
520 pub const mask: u32 = 0b1111 << offset;
521 /// Read-only values (empty)
522 pub mod R {}
523 /// Write-only values (empty)
524 pub mod W {}
525 /// Read-write values
526 pub mod RW {
527
528 /// 0b0000: SYSCLK not divided
529 pub const Div1: u32 = 0b0000;
530
531 /// 0b1000: SYSCLK divided by 2
532 pub const Div2: u32 = 0b1000;
533
534 /// 0b1001: SYSCLK divided by 4
535 pub const Div4: u32 = 0b1001;
536
537 /// 0b1010: SYSCLK divided by 8
538 pub const Div8: u32 = 0b1010;
539
540 /// 0b1011: SYSCLK divided by 16
541 pub const Div16: u32 = 0b1011;
542
543 /// 0b1100: SYSCLK divided by 64
544 pub const Div64: u32 = 0b1100;
545
546 /// 0b1101: SYSCLK divided by 128
547 pub const Div128: u32 = 0b1101;
548
549 /// 0b1110: SYSCLK divided by 256
550 pub const Div256: u32 = 0b1110;
551
552 /// 0b1111: SYSCLK divided by 512
553 pub const Div512: u32 = 0b1111;
554 }
555 }
556
557 /// System clock switch
558 pub mod SW {
559 /// Offset (0 bits)
560 pub const offset: u32 = 0;
561 /// Mask (2 bits: 0b11 << 0)
562 pub const mask: u32 = 0b11 << offset;
563 /// Read-only values (empty)
564 pub mod R {}
565 /// Write-only values (empty)
566 pub mod W {}
567 /// Read-write values
568 pub mod RW {
569
570 /// 0b00: HSI selected as system clock
571 pub const HSI: u32 = 0b00;
572
573 /// 0b01: HSE selected as system clock
574 pub const HSE: u32 = 0b01;
575
576 /// 0b10: PLL selected as system clock
577 pub const PLL: u32 = 0b10;
578 }
579 }
580
581 /// System clock switch status
582 pub mod SWS {
583 /// Offset (2 bits)
584 pub const offset: u32 = 2;
585 /// Mask (2 bits: 0b11 << 2)
586 pub const mask: u32 = 0b11 << offset;
587 /// Read-only values
588 pub mod R {
589
590 /// 0b00: HSI oscillator used as system clock
591 pub const HSI: u32 = 0b00;
592
593 /// 0b01: HSE oscillator used as system clock
594 pub const HSE: u32 = 0b01;
595
596 /// 0b10: PLL used as system clock
597 pub const PLL: u32 = 0b10;
598 }
599 /// Write-only values (empty)
600 pub mod W {}
601 /// Read-write values (empty)
602 pub mod RW {}
603 }
604}
605
606/// clock interrupt register
607pub mod CIR {
608
609 /// Clock security system interrupt clear
610 pub mod CSSC {
611 /// Offset (23 bits)
612 pub const offset: u32 = 23;
613 /// Mask (1 bit: 1 << 23)
614 pub const mask: u32 = 1 << offset;
615 /// Read-only values (empty)
616 pub mod R {}
617 /// Write-only values
618 pub mod W {
619
620 /// 0b1: Clear CSSF flag
621 pub const Clear: u32 = 0b1;
622 }
623 /// Read-write values (empty)
624 pub mod RW {}
625 }
626
627 /// PLLSAI Ready Interrupt Clear
628 pub mod PLLSAIRDYC {
629 /// Offset (22 bits)
630 pub const offset: u32 = 22;
631 /// Mask (1 bit: 1 << 22)
632 pub const mask: u32 = 1 << offset;
633 /// Read-only values (empty)
634 pub mod R {}
635 /// Write-only values
636 pub mod W {
637
638 /// 0b1: Clear interrupt flag
639 pub const Clear: u32 = 0b1;
640 }
641 /// Read-write values (empty)
642 pub mod RW {}
643 }
644
645 /// PLLI2S ready interrupt clear
646 pub mod PLLI2SRDYC {
647 /// Offset (21 bits)
648 pub const offset: u32 = 21;
649 /// Mask (1 bit: 1 << 21)
650 pub const mask: u32 = 1 << offset;
651 /// Read-only values (empty)
652 pub mod R {}
653 pub use super::PLLSAIRDYC::W;
654 /// Read-write values (empty)
655 pub mod RW {}
656 }
657
658 /// Main PLL(PLL) ready interrupt clear
659 pub mod PLLRDYC {
660 /// Offset (20 bits)
661 pub const offset: u32 = 20;
662 /// Mask (1 bit: 1 << 20)
663 pub const mask: u32 = 1 << offset;
664 /// Read-only values (empty)
665 pub mod R {}
666 pub use super::PLLSAIRDYC::W;
667 /// Read-write values (empty)
668 pub mod RW {}
669 }
670
671 /// HSE ready interrupt clear
672 pub mod HSERDYC {
673 /// Offset (19 bits)
674 pub const offset: u32 = 19;
675 /// Mask (1 bit: 1 << 19)
676 pub const mask: u32 = 1 << offset;
677 /// Read-only values (empty)
678 pub mod R {}
679 pub use super::PLLSAIRDYC::W;
680 /// Read-write values (empty)
681 pub mod RW {}
682 }
683
684 /// HSI ready interrupt clear
685 pub mod HSIRDYC {
686 /// Offset (18 bits)
687 pub const offset: u32 = 18;
688 /// Mask (1 bit: 1 << 18)
689 pub const mask: u32 = 1 << offset;
690 /// Read-only values (empty)
691 pub mod R {}
692 pub use super::PLLSAIRDYC::W;
693 /// Read-write values (empty)
694 pub mod RW {}
695 }
696
697 /// LSE ready interrupt clear
698 pub mod LSERDYC {
699 /// Offset (17 bits)
700 pub const offset: u32 = 17;
701 /// Mask (1 bit: 1 << 17)
702 pub const mask: u32 = 1 << offset;
703 /// Read-only values (empty)
704 pub mod R {}
705 pub use super::PLLSAIRDYC::W;
706 /// Read-write values (empty)
707 pub mod RW {}
708 }
709
710 /// LSI ready interrupt clear
711 pub mod LSIRDYC {
712 /// Offset (16 bits)
713 pub const offset: u32 = 16;
714 /// Mask (1 bit: 1 << 16)
715 pub const mask: u32 = 1 << offset;
716 /// Read-only values (empty)
717 pub mod R {}
718 pub use super::PLLSAIRDYC::W;
719 /// Read-write values (empty)
720 pub mod RW {}
721 }
722
723 /// PLLSAI Ready Interrupt Enable
724 pub mod PLLSAIRDYIE {
725 /// Offset (14 bits)
726 pub const offset: u32 = 14;
727 /// Mask (1 bit: 1 << 14)
728 pub const mask: u32 = 1 << offset;
729 /// Read-only values (empty)
730 pub mod R {}
731 /// Write-only values (empty)
732 pub mod W {}
733 /// Read-write values
734 pub mod RW {
735
736 /// 0b0: Interrupt disabled
737 pub const Disabled: u32 = 0b0;
738
739 /// 0b1: Interrupt enabled
740 pub const Enabled: u32 = 0b1;
741 }
742 }
743
744 /// PLLI2S ready interrupt enable
745 pub mod PLLI2SRDYIE {
746 /// Offset (13 bits)
747 pub const offset: u32 = 13;
748 /// Mask (1 bit: 1 << 13)
749 pub const mask: u32 = 1 << offset;
750 /// Read-only values (empty)
751 pub mod R {}
752 /// Write-only values (empty)
753 pub mod W {}
754 pub use super::PLLSAIRDYIE::RW;
755 }
756
757 /// Main PLL (PLL) ready interrupt enable
758 pub mod PLLRDYIE {
759 /// Offset (12 bits)
760 pub const offset: u32 = 12;
761 /// Mask (1 bit: 1 << 12)
762 pub const mask: u32 = 1 << offset;
763 /// Read-only values (empty)
764 pub mod R {}
765 /// Write-only values (empty)
766 pub mod W {}
767 pub use super::PLLSAIRDYIE::RW;
768 }
769
770 /// HSE ready interrupt enable
771 pub mod HSERDYIE {
772 /// Offset (11 bits)
773 pub const offset: u32 = 11;
774 /// Mask (1 bit: 1 << 11)
775 pub const mask: u32 = 1 << offset;
776 /// Read-only values (empty)
777 pub mod R {}
778 /// Write-only values (empty)
779 pub mod W {}
780 pub use super::PLLSAIRDYIE::RW;
781 }
782
783 /// HSI ready interrupt enable
784 pub mod HSIRDYIE {
785 /// Offset (10 bits)
786 pub const offset: u32 = 10;
787 /// Mask (1 bit: 1 << 10)
788 pub const mask: u32 = 1 << offset;
789 /// Read-only values (empty)
790 pub mod R {}
791 /// Write-only values (empty)
792 pub mod W {}
793 pub use super::PLLSAIRDYIE::RW;
794 }
795
796 /// LSE ready interrupt enable
797 pub mod LSERDYIE {
798 /// Offset (9 bits)
799 pub const offset: u32 = 9;
800 /// Mask (1 bit: 1 << 9)
801 pub const mask: u32 = 1 << offset;
802 /// Read-only values (empty)
803 pub mod R {}
804 /// Write-only values (empty)
805 pub mod W {}
806 pub use super::PLLSAIRDYIE::RW;
807 }
808
809 /// LSI ready interrupt enable
810 pub mod LSIRDYIE {
811 /// Offset (8 bits)
812 pub const offset: u32 = 8;
813 /// Mask (1 bit: 1 << 8)
814 pub const mask: u32 = 1 << offset;
815 /// Read-only values (empty)
816 pub mod R {}
817 /// Write-only values (empty)
818 pub mod W {}
819 pub use super::PLLSAIRDYIE::RW;
820 }
821
822 /// Clock security system interrupt flag
823 pub mod CSSF {
824 /// Offset (7 bits)
825 pub const offset: u32 = 7;
826 /// Mask (1 bit: 1 << 7)
827 pub const mask: u32 = 1 << offset;
828 /// Read-only values
829 pub mod R {
830
831 /// 0b0: No clock security interrupt caused by HSE clock failure
832 pub const NotInterrupted: u32 = 0b0;
833
834 /// 0b1: Clock security interrupt caused by HSE clock failure
835 pub const Interrupted: u32 = 0b1;
836 }
837 /// Write-only values (empty)
838 pub mod W {}
839 /// Read-write values (empty)
840 pub mod RW {}
841 }
842
843 /// PLLSAI ready interrupt flag
844 pub mod PLLSAIRDYF {
845 /// Offset (6 bits)
846 pub const offset: u32 = 6;
847 /// Mask (1 bit: 1 << 6)
848 pub const mask: u32 = 1 << offset;
849 /// Read-only values
850 pub mod R {
851
852 /// 0b0: No clock ready interrupt
853 pub const NotInterrupted: u32 = 0b0;
854
855 /// 0b1: Clock ready interrupt
856 pub const Interrupted: u32 = 0b1;
857 }
858 /// Write-only values (empty)
859 pub mod W {}
860 /// Read-write values (empty)
861 pub mod RW {}
862 }
863
864 /// PLLI2S ready interrupt flag
865 pub mod PLLI2SRDYF {
866 /// Offset (5 bits)
867 pub const offset: u32 = 5;
868 /// Mask (1 bit: 1 << 5)
869 pub const mask: u32 = 1 << offset;
870 pub use super::PLLSAIRDYF::R;
871 /// Write-only values (empty)
872 pub mod W {}
873 /// Read-write values (empty)
874 pub mod RW {}
875 }
876
877 /// Main PLL (PLL) ready interrupt flag
878 pub mod PLLRDYF {
879 /// Offset (4 bits)
880 pub const offset: u32 = 4;
881 /// Mask (1 bit: 1 << 4)
882 pub const mask: u32 = 1 << offset;
883 pub use super::PLLSAIRDYF::R;
884 /// Write-only values (empty)
885 pub mod W {}
886 /// Read-write values (empty)
887 pub mod RW {}
888 }
889
890 /// HSE ready interrupt flag
891 pub mod HSERDYF {
892 /// Offset (3 bits)
893 pub const offset: u32 = 3;
894 /// Mask (1 bit: 1 << 3)
895 pub const mask: u32 = 1 << offset;
896 pub use super::PLLSAIRDYF::R;
897 /// Write-only values (empty)
898 pub mod W {}
899 /// Read-write values (empty)
900 pub mod RW {}
901 }
902
903 /// HSI ready interrupt flag
904 pub mod HSIRDYF {
905 /// Offset (2 bits)
906 pub const offset: u32 = 2;
907 /// Mask (1 bit: 1 << 2)
908 pub const mask: u32 = 1 << offset;
909 pub use super::PLLSAIRDYF::R;
910 /// Write-only values (empty)
911 pub mod W {}
912 /// Read-write values (empty)
913 pub mod RW {}
914 }
915
916 /// LSE ready interrupt flag
917 pub mod LSERDYF {
918 /// Offset (1 bits)
919 pub const offset: u32 = 1;
920 /// Mask (1 bit: 1 << 1)
921 pub const mask: u32 = 1 << offset;
922 pub use super::PLLSAIRDYF::R;
923 /// Write-only values (empty)
924 pub mod W {}
925 /// Read-write values (empty)
926 pub mod RW {}
927 }
928
929 /// LSI ready interrupt flag
930 pub mod LSIRDYF {
931 /// Offset (0 bits)
932 pub const offset: u32 = 0;
933 /// Mask (1 bit: 1 << 0)
934 pub const mask: u32 = 1 << offset;
935 pub use super::PLLSAIRDYF::R;
936 /// Write-only values (empty)
937 pub mod W {}
938 /// Read-write values (empty)
939 pub mod RW {}
940 }
941}
942
943/// AHB1 peripheral reset register
944pub mod AHB1RSTR {
945
946 /// USB OTG HS module reset
947 pub mod OTGHSRST {
948 /// Offset (29 bits)
949 pub const offset: u32 = 29;
950 /// Mask (1 bit: 1 << 29)
951 pub const mask: u32 = 1 << offset;
952 /// Read-only values (empty)
953 pub mod R {}
954 /// Write-only values (empty)
955 pub mod W {}
956 /// Read-write values
957 pub mod RW {
958
959 /// 0b1: Reset the selected module
960 pub const Reset: u32 = 0b1;
961 }
962 }
963
964 /// DMA2 reset
965 pub mod DMA2RST {
966 /// Offset (22 bits)
967 pub const offset: u32 = 22;
968 /// Mask (1 bit: 1 << 22)
969 pub const mask: u32 = 1 << offset;
970 /// Read-only values (empty)
971 pub mod R {}
972 /// Write-only values (empty)
973 pub mod W {}
974 pub use super::OTGHSRST::RW;
975 }
976
977 /// DMA2 reset
978 pub mod DMA1RST {
979 /// Offset (21 bits)
980 pub const offset: u32 = 21;
981 /// Mask (1 bit: 1 << 21)
982 pub const mask: u32 = 1 << offset;
983 /// Read-only values (empty)
984 pub mod R {}
985 /// Write-only values (empty)
986 pub mod W {}
987 pub use super::OTGHSRST::RW;
988 }
989
990 /// CRC reset
991 pub mod CRCRST {
992 /// Offset (12 bits)
993 pub const offset: u32 = 12;
994 /// Mask (1 bit: 1 << 12)
995 pub const mask: u32 = 1 << offset;
996 /// Read-only values (empty)
997 pub mod R {}
998 /// Write-only values (empty)
999 pub mod W {}
1000 pub use super::OTGHSRST::RW;
1001 }
1002
1003 /// IO port H reset
1004 pub mod GPIOHRST {
1005 /// Offset (7 bits)
1006 pub const offset: u32 = 7;
1007 /// Mask (1 bit: 1 << 7)
1008 pub const mask: u32 = 1 << offset;
1009 /// Read-only values (empty)
1010 pub mod R {}
1011 /// Write-only values (empty)
1012 pub mod W {}
1013 pub use super::OTGHSRST::RW;
1014 }
1015
1016 /// IO port G reset
1017 pub mod GPIOGRST {
1018 /// Offset (6 bits)
1019 pub const offset: u32 = 6;
1020 /// Mask (1 bit: 1 << 6)
1021 pub const mask: u32 = 1 << offset;
1022 /// Read-only values (empty)
1023 pub mod R {}
1024 /// Write-only values (empty)
1025 pub mod W {}
1026 pub use super::OTGHSRST::RW;
1027 }
1028
1029 /// IO port F reset
1030 pub mod GPIOFRST {
1031 /// Offset (5 bits)
1032 pub const offset: u32 = 5;
1033 /// Mask (1 bit: 1 << 5)
1034 pub const mask: u32 = 1 << offset;
1035 /// Read-only values (empty)
1036 pub mod R {}
1037 /// Write-only values (empty)
1038 pub mod W {}
1039 pub use super::OTGHSRST::RW;
1040 }
1041
1042 /// IO port E reset
1043 pub mod GPIOERST {
1044 /// Offset (4 bits)
1045 pub const offset: u32 = 4;
1046 /// Mask (1 bit: 1 << 4)
1047 pub const mask: u32 = 1 << offset;
1048 /// Read-only values (empty)
1049 pub mod R {}
1050 /// Write-only values (empty)
1051 pub mod W {}
1052 pub use super::OTGHSRST::RW;
1053 }
1054
1055 /// IO port D reset
1056 pub mod GPIODRST {
1057 /// Offset (3 bits)
1058 pub const offset: u32 = 3;
1059 /// Mask (1 bit: 1 << 3)
1060 pub const mask: u32 = 1 << offset;
1061 /// Read-only values (empty)
1062 pub mod R {}
1063 /// Write-only values (empty)
1064 pub mod W {}
1065 pub use super::OTGHSRST::RW;
1066 }
1067
1068 /// IO port C reset
1069 pub mod GPIOCRST {
1070 /// Offset (2 bits)
1071 pub const offset: u32 = 2;
1072 /// Mask (1 bit: 1 << 2)
1073 pub const mask: u32 = 1 << offset;
1074 /// Read-only values (empty)
1075 pub mod R {}
1076 /// Write-only values (empty)
1077 pub mod W {}
1078 pub use super::OTGHSRST::RW;
1079 }
1080
1081 /// IO port B reset
1082 pub mod GPIOBRST {
1083 /// Offset (1 bits)
1084 pub const offset: u32 = 1;
1085 /// Mask (1 bit: 1 << 1)
1086 pub const mask: u32 = 1 << offset;
1087 /// Read-only values (empty)
1088 pub mod R {}
1089 /// Write-only values (empty)
1090 pub mod W {}
1091 pub use super::OTGHSRST::RW;
1092 }
1093
1094 /// IO port A reset
1095 pub mod GPIOARST {
1096 /// Offset (0 bits)
1097 pub const offset: u32 = 0;
1098 /// Mask (1 bit: 1 << 0)
1099 pub const mask: u32 = 1 << offset;
1100 /// Read-only values (empty)
1101 pub mod R {}
1102 /// Write-only values (empty)
1103 pub mod W {}
1104 pub use super::OTGHSRST::RW;
1105 }
1106}
1107
1108/// AHB2 peripheral reset register
1109pub mod AHB2RSTR {
1110
1111 /// USB OTG FS module reset
1112 pub mod OTGFSRST {
1113 /// Offset (7 bits)
1114 pub const offset: u32 = 7;
1115 /// Mask (1 bit: 1 << 7)
1116 pub const mask: u32 = 1 << offset;
1117 /// Read-only values (empty)
1118 pub mod R {}
1119 /// Write-only values (empty)
1120 pub mod W {}
1121 /// Read-write values
1122 pub mod RW {
1123
1124 /// 0b1: Reset the selected module
1125 pub const Reset: u32 = 0b1;
1126 }
1127 }
1128
1129 /// Camera interface reset
1130 pub mod DCMIRST {
1131 /// Offset (0 bits)
1132 pub const offset: u32 = 0;
1133 /// Mask (1 bit: 1 << 0)
1134 pub const mask: u32 = 1 << offset;
1135 /// Read-only values (empty)
1136 pub mod R {}
1137 /// Write-only values (empty)
1138 pub mod W {}
1139 pub use super::OTGFSRST::RW;
1140 }
1141}
1142
1143/// AHB3 peripheral reset register
1144pub mod AHB3RSTR {
1145
1146 /// Flexible memory controller module reset
1147 pub mod FMCRST {
1148 /// Offset (0 bits)
1149 pub const offset: u32 = 0;
1150 /// Mask (1 bit: 1 << 0)
1151 pub const mask: u32 = 1 << offset;
1152 /// Read-only values (empty)
1153 pub mod R {}
1154 /// Write-only values (empty)
1155 pub mod W {}
1156 /// Read-write values
1157 pub mod RW {
1158
1159 /// 0b1: Reset the selected module
1160 pub const Reset: u32 = 0b1;
1161 }
1162 }
1163
1164 /// QUADSPI module reset
1165 pub mod QSPIRST {
1166 /// Offset (1 bits)
1167 pub const offset: u32 = 1;
1168 /// Mask (1 bit: 1 << 1)
1169 pub const mask: u32 = 1 << offset;
1170 /// Read-only values (empty)
1171 pub mod R {}
1172 /// Write-only values (empty)
1173 pub mod W {}
1174 pub use super::FMCRST::RW;
1175 }
1176}
1177
1178/// APB1 peripheral reset register
1179pub mod APB1RSTR {
1180
1181 /// TIM2 reset
1182 pub mod TIM2RST {
1183 /// Offset (0 bits)
1184 pub const offset: u32 = 0;
1185 /// Mask (1 bit: 1 << 0)
1186 pub const mask: u32 = 1 << offset;
1187 /// Read-only values (empty)
1188 pub mod R {}
1189 /// Write-only values (empty)
1190 pub mod W {}
1191 /// Read-write values
1192 pub mod RW {
1193
1194 /// 0b1: Reset the selected module
1195 pub const Reset: u32 = 0b1;
1196 }
1197 }
1198
1199 /// TIM3 reset
1200 pub mod TIM3RST {
1201 /// Offset (1 bits)
1202 pub const offset: u32 = 1;
1203 /// Mask (1 bit: 1 << 1)
1204 pub const mask: u32 = 1 << offset;
1205 /// Read-only values (empty)
1206 pub mod R {}
1207 /// Write-only values (empty)
1208 pub mod W {}
1209 pub use super::TIM2RST::RW;
1210 }
1211
1212 /// TIM4 reset
1213 pub mod TIM4RST {
1214 /// Offset (2 bits)
1215 pub const offset: u32 = 2;
1216 /// Mask (1 bit: 1 << 2)
1217 pub const mask: u32 = 1 << offset;
1218 /// Read-only values (empty)
1219 pub mod R {}
1220 /// Write-only values (empty)
1221 pub mod W {}
1222 pub use super::TIM2RST::RW;
1223 }
1224
1225 /// TIM5 reset
1226 pub mod TIM5RST {
1227 /// Offset (3 bits)
1228 pub const offset: u32 = 3;
1229 /// Mask (1 bit: 1 << 3)
1230 pub const mask: u32 = 1 << offset;
1231 /// Read-only values (empty)
1232 pub mod R {}
1233 /// Write-only values (empty)
1234 pub mod W {}
1235 pub use super::TIM2RST::RW;
1236 }
1237
1238 /// TIM6 reset
1239 pub mod TIM6RST {
1240 /// Offset (4 bits)
1241 pub const offset: u32 = 4;
1242 /// Mask (1 bit: 1 << 4)
1243 pub const mask: u32 = 1 << offset;
1244 /// Read-only values (empty)
1245 pub mod R {}
1246 /// Write-only values (empty)
1247 pub mod W {}
1248 pub use super::TIM2RST::RW;
1249 }
1250
1251 /// TIM7 reset
1252 pub mod TIM7RST {
1253 /// Offset (5 bits)
1254 pub const offset: u32 = 5;
1255 /// Mask (1 bit: 1 << 5)
1256 pub const mask: u32 = 1 << offset;
1257 /// Read-only values (empty)
1258 pub mod R {}
1259 /// Write-only values (empty)
1260 pub mod W {}
1261 pub use super::TIM2RST::RW;
1262 }
1263
1264 /// TIM12 reset
1265 pub mod TIM12RST {
1266 /// Offset (6 bits)
1267 pub const offset: u32 = 6;
1268 /// Mask (1 bit: 1 << 6)
1269 pub const mask: u32 = 1 << offset;
1270 /// Read-only values (empty)
1271 pub mod R {}
1272 /// Write-only values (empty)
1273 pub mod W {}
1274 pub use super::TIM2RST::RW;
1275 }
1276
1277 /// TIM13 reset
1278 pub mod TIM13RST {
1279 /// Offset (7 bits)
1280 pub const offset: u32 = 7;
1281 /// Mask (1 bit: 1 << 7)
1282 pub const mask: u32 = 1 << offset;
1283 /// Read-only values (empty)
1284 pub mod R {}
1285 /// Write-only values (empty)
1286 pub mod W {}
1287 pub use super::TIM2RST::RW;
1288 }
1289
1290 /// TIM14 reset
1291 pub mod TIM14RST {
1292 /// Offset (8 bits)
1293 pub const offset: u32 = 8;
1294 /// Mask (1 bit: 1 << 8)
1295 pub const mask: u32 = 1 << offset;
1296 /// Read-only values (empty)
1297 pub mod R {}
1298 /// Write-only values (empty)
1299 pub mod W {}
1300 pub use super::TIM2RST::RW;
1301 }
1302
1303 /// Window watchdog reset
1304 pub mod WWDGRST {
1305 /// Offset (11 bits)
1306 pub const offset: u32 = 11;
1307 /// Mask (1 bit: 1 << 11)
1308 pub const mask: u32 = 1 << offset;
1309 /// Read-only values (empty)
1310 pub mod R {}
1311 /// Write-only values (empty)
1312 pub mod W {}
1313 pub use super::TIM2RST::RW;
1314 }
1315
1316 /// SPI 2 reset
1317 pub mod SPI2RST {
1318 /// Offset (14 bits)
1319 pub const offset: u32 = 14;
1320 /// Mask (1 bit: 1 << 14)
1321 pub const mask: u32 = 1 << offset;
1322 /// Read-only values (empty)
1323 pub mod R {}
1324 /// Write-only values (empty)
1325 pub mod W {}
1326 pub use super::TIM2RST::RW;
1327 }
1328
1329 /// SPI 3 reset
1330 pub mod SPI3RST {
1331 /// Offset (15 bits)
1332 pub const offset: u32 = 15;
1333 /// Mask (1 bit: 1 << 15)
1334 pub const mask: u32 = 1 << offset;
1335 /// Read-only values (empty)
1336 pub mod R {}
1337 /// Write-only values (empty)
1338 pub mod W {}
1339 pub use super::TIM2RST::RW;
1340 }
1341
1342 /// SPDIF-IN reset
1343 pub mod SPDIFRST {
1344 /// Offset (16 bits)
1345 pub const offset: u32 = 16;
1346 /// Mask (1 bit: 1 << 16)
1347 pub const mask: u32 = 1 << offset;
1348 /// Read-only values (empty)
1349 pub mod R {}
1350 /// Write-only values (empty)
1351 pub mod W {}
1352 pub use super::TIM2RST::RW;
1353 }
1354
1355 /// USART 2 reset
1356 pub mod USART2RST {
1357 /// Offset (17 bits)
1358 pub const offset: u32 = 17;
1359 /// Mask (1 bit: 1 << 17)
1360 pub const mask: u32 = 1 << offset;
1361 /// Read-only values (empty)
1362 pub mod R {}
1363 /// Write-only values (empty)
1364 pub mod W {}
1365 pub use super::TIM2RST::RW;
1366 }
1367
1368 /// USART 3 reset
1369 pub mod USART3RST {
1370 /// Offset (18 bits)
1371 pub const offset: u32 = 18;
1372 /// Mask (1 bit: 1 << 18)
1373 pub const mask: u32 = 1 << offset;
1374 /// Read-only values (empty)
1375 pub mod R {}
1376 /// Write-only values (empty)
1377 pub mod W {}
1378 pub use super::TIM2RST::RW;
1379 }
1380
1381 /// USART 4 reset
1382 pub mod UART4RST {
1383 /// Offset (19 bits)
1384 pub const offset: u32 = 19;
1385 /// Mask (1 bit: 1 << 19)
1386 pub const mask: u32 = 1 << offset;
1387 /// Read-only values (empty)
1388 pub mod R {}
1389 /// Write-only values (empty)
1390 pub mod W {}
1391 pub use super::TIM2RST::RW;
1392 }
1393
1394 /// USART 5 reset
1395 pub mod UART5RST {
1396 /// Offset (20 bits)
1397 pub const offset: u32 = 20;
1398 /// Mask (1 bit: 1 << 20)
1399 pub const mask: u32 = 1 << offset;
1400 /// Read-only values (empty)
1401 pub mod R {}
1402 /// Write-only values (empty)
1403 pub mod W {}
1404 pub use super::TIM2RST::RW;
1405 }
1406
1407 /// I2C 1 reset
1408 pub mod I2C1RST {
1409 /// Offset (21 bits)
1410 pub const offset: u32 = 21;
1411 /// Mask (1 bit: 1 << 21)
1412 pub const mask: u32 = 1 << offset;
1413 /// Read-only values (empty)
1414 pub mod R {}
1415 /// Write-only values (empty)
1416 pub mod W {}
1417 pub use super::TIM2RST::RW;
1418 }
1419
1420 /// I2C 2 reset
1421 pub mod I2C2RST {
1422 /// Offset (22 bits)
1423 pub const offset: u32 = 22;
1424 /// Mask (1 bit: 1 << 22)
1425 pub const mask: u32 = 1 << offset;
1426 /// Read-only values (empty)
1427 pub mod R {}
1428 /// Write-only values (empty)
1429 pub mod W {}
1430 pub use super::TIM2RST::RW;
1431 }
1432
1433 /// I2C3 reset
1434 pub mod I2C3RST {
1435 /// Offset (23 bits)
1436 pub const offset: u32 = 23;
1437 /// Mask (1 bit: 1 << 23)
1438 pub const mask: u32 = 1 << offset;
1439 /// Read-only values (empty)
1440 pub mod R {}
1441 /// Write-only values (empty)
1442 pub mod W {}
1443 pub use super::TIM2RST::RW;
1444 }
1445
1446 /// FMPI2C1 reset
1447 pub mod FMPI2C1RST {
1448 /// Offset (24 bits)
1449 pub const offset: u32 = 24;
1450 /// Mask (1 bit: 1 << 24)
1451 pub const mask: u32 = 1 << offset;
1452 /// Read-only values (empty)
1453 pub mod R {}
1454 /// Write-only values (empty)
1455 pub mod W {}
1456 pub use super::TIM2RST::RW;
1457 }
1458
1459 /// CAN1 reset
1460 pub mod CAN1RST {
1461 /// Offset (25 bits)
1462 pub const offset: u32 = 25;
1463 /// Mask (1 bit: 1 << 25)
1464 pub const mask: u32 = 1 << offset;
1465 /// Read-only values (empty)
1466 pub mod R {}
1467 /// Write-only values (empty)
1468 pub mod W {}
1469 pub use super::TIM2RST::RW;
1470 }
1471
1472 /// CAN2 reset
1473 pub mod CAN2RST {
1474 /// Offset (26 bits)
1475 pub const offset: u32 = 26;
1476 /// Mask (1 bit: 1 << 26)
1477 pub const mask: u32 = 1 << offset;
1478 /// Read-only values (empty)
1479 pub mod R {}
1480 /// Write-only values (empty)
1481 pub mod W {}
1482 pub use super::TIM2RST::RW;
1483 }
1484
1485 /// Power interface reset
1486 pub mod PWRRST {
1487 /// Offset (28 bits)
1488 pub const offset: u32 = 28;
1489 /// Mask (1 bit: 1 << 28)
1490 pub const mask: u32 = 1 << offset;
1491 /// Read-only values (empty)
1492 pub mod R {}
1493 /// Write-only values (empty)
1494 pub mod W {}
1495 pub use super::TIM2RST::RW;
1496 }
1497
1498 /// DAC reset
1499 pub mod DACRST {
1500 /// Offset (29 bits)
1501 pub const offset: u32 = 29;
1502 /// Mask (1 bit: 1 << 29)
1503 pub const mask: u32 = 1 << offset;
1504 /// Read-only values (empty)
1505 pub mod R {}
1506 /// Write-only values (empty)
1507 pub mod W {}
1508 pub use super::TIM2RST::RW;
1509 }
1510}
1511
1512/// APB2 peripheral reset register
1513pub mod APB2RSTR {
1514
1515 /// TIM1 reset
1516 pub mod TIM1RST {
1517 /// Offset (0 bits)
1518 pub const offset: u32 = 0;
1519 /// Mask (1 bit: 1 << 0)
1520 pub const mask: u32 = 1 << offset;
1521 /// Read-only values (empty)
1522 pub mod R {}
1523 /// Write-only values (empty)
1524 pub mod W {}
1525 /// Read-write values
1526 pub mod RW {
1527
1528 /// 0b1: Reset the selected module
1529 pub const Reset: u32 = 0b1;
1530 }
1531 }
1532
1533 /// TIM8 reset
1534 pub mod TIM8RST {
1535 /// Offset (1 bits)
1536 pub const offset: u32 = 1;
1537 /// Mask (1 bit: 1 << 1)
1538 pub const mask: u32 = 1 << offset;
1539 /// Read-only values (empty)
1540 pub mod R {}
1541 /// Write-only values (empty)
1542 pub mod W {}
1543 pub use super::TIM1RST::RW;
1544 }
1545
1546 /// USART1 reset
1547 pub mod USART1RST {
1548 /// Offset (4 bits)
1549 pub const offset: u32 = 4;
1550 /// Mask (1 bit: 1 << 4)
1551 pub const mask: u32 = 1 << offset;
1552 /// Read-only values (empty)
1553 pub mod R {}
1554 /// Write-only values (empty)
1555 pub mod W {}
1556 pub use super::TIM1RST::RW;
1557 }
1558
1559 /// USART6 reset
1560 pub mod USART6RST {
1561 /// Offset (5 bits)
1562 pub const offset: u32 = 5;
1563 /// Mask (1 bit: 1 << 5)
1564 pub const mask: u32 = 1 << offset;
1565 /// Read-only values (empty)
1566 pub mod R {}
1567 /// Write-only values (empty)
1568 pub mod W {}
1569 pub use super::TIM1RST::RW;
1570 }
1571
1572 /// ADC interface reset (common to all ADCs)
1573 pub mod ADCRST {
1574 /// Offset (8 bits)
1575 pub const offset: u32 = 8;
1576 /// Mask (1 bit: 1 << 8)
1577 pub const mask: u32 = 1 << offset;
1578 /// Read-only values (empty)
1579 pub mod R {}
1580 /// Write-only values (empty)
1581 pub mod W {}
1582 pub use super::TIM1RST::RW;
1583 }
1584
1585 /// SDIO reset
1586 pub mod SDIORST {
1587 /// Offset (11 bits)
1588 pub const offset: u32 = 11;
1589 /// Mask (1 bit: 1 << 11)
1590 pub const mask: u32 = 1 << offset;
1591 /// Read-only values (empty)
1592 pub mod R {}
1593 /// Write-only values (empty)
1594 pub mod W {}
1595 pub use super::TIM1RST::RW;
1596 }
1597
1598 /// SPI 1 reset
1599 pub mod SPI1RST {
1600 /// Offset (12 bits)
1601 pub const offset: u32 = 12;
1602 /// Mask (1 bit: 1 << 12)
1603 pub const mask: u32 = 1 << offset;
1604 /// Read-only values (empty)
1605 pub mod R {}
1606 /// Write-only values (empty)
1607 pub mod W {}
1608 pub use super::TIM1RST::RW;
1609 }
1610
1611 /// SPI4 reset
1612 pub mod SPI4RST {
1613 /// Offset (13 bits)
1614 pub const offset: u32 = 13;
1615 /// Mask (1 bit: 1 << 13)
1616 pub const mask: u32 = 1 << offset;
1617 /// Read-only values (empty)
1618 pub mod R {}
1619 /// Write-only values (empty)
1620 pub mod W {}
1621 pub use super::TIM1RST::RW;
1622 }
1623
1624 /// System configuration controller reset
1625 pub mod SYSCFGRST {
1626 /// Offset (14 bits)
1627 pub const offset: u32 = 14;
1628 /// Mask (1 bit: 1 << 14)
1629 pub const mask: u32 = 1 << offset;
1630 /// Read-only values (empty)
1631 pub mod R {}
1632 /// Write-only values (empty)
1633 pub mod W {}
1634 pub use super::TIM1RST::RW;
1635 }
1636
1637 /// TIM9 reset
1638 pub mod TIM9RST {
1639 /// Offset (16 bits)
1640 pub const offset: u32 = 16;
1641 /// Mask (1 bit: 1 << 16)
1642 pub const mask: u32 = 1 << offset;
1643 /// Read-only values (empty)
1644 pub mod R {}
1645 /// Write-only values (empty)
1646 pub mod W {}
1647 pub use super::TIM1RST::RW;
1648 }
1649
1650 /// TIM10 reset
1651 pub mod TIM10RST {
1652 /// Offset (17 bits)
1653 pub const offset: u32 = 17;
1654 /// Mask (1 bit: 1 << 17)
1655 pub const mask: u32 = 1 << offset;
1656 /// Read-only values (empty)
1657 pub mod R {}
1658 /// Write-only values (empty)
1659 pub mod W {}
1660 pub use super::TIM1RST::RW;
1661 }
1662
1663 /// TIM11 reset
1664 pub mod TIM11RST {
1665 /// Offset (18 bits)
1666 pub const offset: u32 = 18;
1667 /// Mask (1 bit: 1 << 18)
1668 pub const mask: u32 = 1 << offset;
1669 /// Read-only values (empty)
1670 pub mod R {}
1671 /// Write-only values (empty)
1672 pub mod W {}
1673 pub use super::TIM1RST::RW;
1674 }
1675
1676 /// SAI1 reset
1677 pub mod SAI1RST {
1678 /// Offset (22 bits)
1679 pub const offset: u32 = 22;
1680 /// Mask (1 bit: 1 << 22)
1681 pub const mask: u32 = 1 << offset;
1682 /// Read-only values (empty)
1683 pub mod R {}
1684 /// Write-only values (empty)
1685 pub mod W {}
1686 pub use super::TIM1RST::RW;
1687 }
1688
1689 /// SAI2 reset
1690 pub mod SAI2RST {
1691 /// Offset (23 bits)
1692 pub const offset: u32 = 23;
1693 /// Mask (1 bit: 1 << 23)
1694 pub const mask: u32 = 1 << offset;
1695 /// Read-only values (empty)
1696 pub mod R {}
1697 /// Write-only values (empty)
1698 pub mod W {}
1699 pub use super::TIM1RST::RW;
1700 }
1701}
1702
1703/// AHB1 peripheral clock register
1704pub mod AHB1ENR {
1705
1706 /// USB OTG HSULPI clock enable
1707 pub mod OTGHSULPIEN {
1708 /// Offset (30 bits)
1709 pub const offset: u32 = 30;
1710 /// Mask (1 bit: 1 << 30)
1711 pub const mask: u32 = 1 << offset;
1712 /// Read-only values (empty)
1713 pub mod R {}
1714 /// Write-only values (empty)
1715 pub mod W {}
1716 /// Read-write values
1717 pub mod RW {
1718
1719 /// 0b0: The selected clock is disabled
1720 pub const Disabled: u32 = 0b0;
1721
1722 /// 0b1: The selected clock is enabled
1723 pub const Enabled: u32 = 0b1;
1724 }
1725 }
1726
1727 /// USB OTG HS clock enable
1728 pub mod OTGHSEN {
1729 /// Offset (29 bits)
1730 pub const offset: u32 = 29;
1731 /// Mask (1 bit: 1 << 29)
1732 pub const mask: u32 = 1 << offset;
1733 /// Read-only values (empty)
1734 pub mod R {}
1735 /// Write-only values (empty)
1736 pub mod W {}
1737 pub use super::OTGHSULPIEN::RW;
1738 }
1739
1740 /// DMA2 clock enable
1741 pub mod DMA2EN {
1742 /// Offset (22 bits)
1743 pub const offset: u32 = 22;
1744 /// Mask (1 bit: 1 << 22)
1745 pub const mask: u32 = 1 << offset;
1746 /// Read-only values (empty)
1747 pub mod R {}
1748 /// Write-only values (empty)
1749 pub mod W {}
1750 pub use super::OTGHSULPIEN::RW;
1751 }
1752
1753 /// DMA1 clock enable
1754 pub mod DMA1EN {
1755 /// Offset (21 bits)
1756 pub const offset: u32 = 21;
1757 /// Mask (1 bit: 1 << 21)
1758 pub const mask: u32 = 1 << offset;
1759 /// Read-only values (empty)
1760 pub mod R {}
1761 /// Write-only values (empty)
1762 pub mod W {}
1763 pub use super::OTGHSULPIEN::RW;
1764 }
1765
1766 /// Backup SRAM interface clock enable
1767 pub mod BKPSRAMEN {
1768 /// Offset (18 bits)
1769 pub const offset: u32 = 18;
1770 /// Mask (1 bit: 1 << 18)
1771 pub const mask: u32 = 1 << offset;
1772 /// Read-only values (empty)
1773 pub mod R {}
1774 /// Write-only values (empty)
1775 pub mod W {}
1776 pub use super::OTGHSULPIEN::RW;
1777 }
1778
1779 /// CRC clock enable
1780 pub mod CRCEN {
1781 /// Offset (12 bits)
1782 pub const offset: u32 = 12;
1783 /// Mask (1 bit: 1 << 12)
1784 pub const mask: u32 = 1 << offset;
1785 /// Read-only values (empty)
1786 pub mod R {}
1787 /// Write-only values (empty)
1788 pub mod W {}
1789 pub use super::OTGHSULPIEN::RW;
1790 }
1791
1792 /// IO port H clock enable
1793 pub mod GPIOHEN {
1794 /// Offset (7 bits)
1795 pub const offset: u32 = 7;
1796 /// Mask (1 bit: 1 << 7)
1797 pub const mask: u32 = 1 << offset;
1798 /// Read-only values (empty)
1799 pub mod R {}
1800 /// Write-only values (empty)
1801 pub mod W {}
1802 pub use super::OTGHSULPIEN::RW;
1803 }
1804
1805 /// IO port G clock enable
1806 pub mod GPIOGEN {
1807 /// Offset (6 bits)
1808 pub const offset: u32 = 6;
1809 /// Mask (1 bit: 1 << 6)
1810 pub const mask: u32 = 1 << offset;
1811 /// Read-only values (empty)
1812 pub mod R {}
1813 /// Write-only values (empty)
1814 pub mod W {}
1815 pub use super::OTGHSULPIEN::RW;
1816 }
1817
1818 /// IO port F clock enable
1819 pub mod GPIOFEN {
1820 /// Offset (5 bits)
1821 pub const offset: u32 = 5;
1822 /// Mask (1 bit: 1 << 5)
1823 pub const mask: u32 = 1 << offset;
1824 /// Read-only values (empty)
1825 pub mod R {}
1826 /// Write-only values (empty)
1827 pub mod W {}
1828 pub use super::OTGHSULPIEN::RW;
1829 }
1830
1831 /// IO port E clock enable
1832 pub mod GPIOEEN {
1833 /// Offset (4 bits)
1834 pub const offset: u32 = 4;
1835 /// Mask (1 bit: 1 << 4)
1836 pub const mask: u32 = 1 << offset;
1837 /// Read-only values (empty)
1838 pub mod R {}
1839 /// Write-only values (empty)
1840 pub mod W {}
1841 pub use super::OTGHSULPIEN::RW;
1842 }
1843
1844 /// IO port D clock enable
1845 pub mod GPIODEN {
1846 /// Offset (3 bits)
1847 pub const offset: u32 = 3;
1848 /// Mask (1 bit: 1 << 3)
1849 pub const mask: u32 = 1 << offset;
1850 /// Read-only values (empty)
1851 pub mod R {}
1852 /// Write-only values (empty)
1853 pub mod W {}
1854 pub use super::OTGHSULPIEN::RW;
1855 }
1856
1857 /// IO port C clock enable
1858 pub mod GPIOCEN {
1859 /// Offset (2 bits)
1860 pub const offset: u32 = 2;
1861 /// Mask (1 bit: 1 << 2)
1862 pub const mask: u32 = 1 << offset;
1863 /// Read-only values (empty)
1864 pub mod R {}
1865 /// Write-only values (empty)
1866 pub mod W {}
1867 pub use super::OTGHSULPIEN::RW;
1868 }
1869
1870 /// IO port B clock enable
1871 pub mod GPIOBEN {
1872 /// Offset (1 bits)
1873 pub const offset: u32 = 1;
1874 /// Mask (1 bit: 1 << 1)
1875 pub const mask: u32 = 1 << offset;
1876 /// Read-only values (empty)
1877 pub mod R {}
1878 /// Write-only values (empty)
1879 pub mod W {}
1880 pub use super::OTGHSULPIEN::RW;
1881 }
1882
1883 /// IO port A clock enable
1884 pub mod GPIOAEN {
1885 /// Offset (0 bits)
1886 pub const offset: u32 = 0;
1887 /// Mask (1 bit: 1 << 0)
1888 pub const mask: u32 = 1 << offset;
1889 /// Read-only values (empty)
1890 pub mod R {}
1891 /// Write-only values (empty)
1892 pub mod W {}
1893 pub use super::OTGHSULPIEN::RW;
1894 }
1895}
1896
1897/// AHB2 peripheral clock enable register
1898pub mod AHB2ENR {
1899
1900 /// USB OTG FS clock enable
1901 pub mod OTGFSEN {
1902 /// Offset (7 bits)
1903 pub const offset: u32 = 7;
1904 /// Mask (1 bit: 1 << 7)
1905 pub const mask: u32 = 1 << offset;
1906 /// Read-only values (empty)
1907 pub mod R {}
1908 /// Write-only values (empty)
1909 pub mod W {}
1910 /// Read-write values
1911 pub mod RW {
1912
1913 /// 0b0: The selected clock is disabled
1914 pub const Disabled: u32 = 0b0;
1915
1916 /// 0b1: The selected clock is enabled
1917 pub const Enabled: u32 = 0b1;
1918 }
1919 }
1920
1921 /// Camera interface enable
1922 pub mod DCMIEN {
1923 /// Offset (0 bits)
1924 pub const offset: u32 = 0;
1925 /// Mask (1 bit: 1 << 0)
1926 pub const mask: u32 = 1 << offset;
1927 /// Read-only values (empty)
1928 pub mod R {}
1929 /// Write-only values (empty)
1930 pub mod W {}
1931 pub use super::OTGFSEN::RW;
1932 }
1933}
1934
1935/// AHB3 peripheral clock enable register
1936pub mod AHB3ENR {
1937
1938 /// Flexible memory controller module clock enable
1939 pub mod FMCEN {
1940 /// Offset (0 bits)
1941 pub const offset: u32 = 0;
1942 /// Mask (1 bit: 1 << 0)
1943 pub const mask: u32 = 1 << offset;
1944 /// Read-only values (empty)
1945 pub mod R {}
1946 /// Write-only values (empty)
1947 pub mod W {}
1948 /// Read-write values
1949 pub mod RW {
1950
1951 /// 0b0: The selected clock is disabled
1952 pub const Disabled: u32 = 0b0;
1953
1954 /// 0b1: The selected clock is enabled
1955 pub const Enabled: u32 = 0b1;
1956 }
1957 }
1958
1959 /// QUADSPI memory controller module clock enable
1960 pub mod QSPIEN {
1961 /// Offset (1 bits)
1962 pub const offset: u32 = 1;
1963 /// Mask (1 bit: 1 << 1)
1964 pub const mask: u32 = 1 << offset;
1965 /// Read-only values (empty)
1966 pub mod R {}
1967 /// Write-only values (empty)
1968 pub mod W {}
1969 pub use super::FMCEN::RW;
1970 }
1971}
1972
1973/// APB1 peripheral clock enable register
1974pub mod APB1ENR {
1975
1976 /// TIM2 clock enable
1977 pub mod TIM2EN {
1978 /// Offset (0 bits)
1979 pub const offset: u32 = 0;
1980 /// Mask (1 bit: 1 << 0)
1981 pub const mask: u32 = 1 << offset;
1982 /// Read-only values (empty)
1983 pub mod R {}
1984 /// Write-only values (empty)
1985 pub mod W {}
1986 /// Read-write values
1987 pub mod RW {
1988
1989 /// 0b0: The selected clock is disabled
1990 pub const Disabled: u32 = 0b0;
1991
1992 /// 0b1: The selected clock is enabled
1993 pub const Enabled: u32 = 0b1;
1994 }
1995 }
1996
1997 /// TIM3 clock enable
1998 pub mod TIM3EN {
1999 /// Offset (1 bits)
2000 pub const offset: u32 = 1;
2001 /// Mask (1 bit: 1 << 1)
2002 pub const mask: u32 = 1 << offset;
2003 /// Read-only values (empty)
2004 pub mod R {}
2005 /// Write-only values (empty)
2006 pub mod W {}
2007 pub use super::TIM2EN::RW;
2008 }
2009
2010 /// TIM4 clock enable
2011 pub mod TIM4EN {
2012 /// Offset (2 bits)
2013 pub const offset: u32 = 2;
2014 /// Mask (1 bit: 1 << 2)
2015 pub const mask: u32 = 1 << offset;
2016 /// Read-only values (empty)
2017 pub mod R {}
2018 /// Write-only values (empty)
2019 pub mod W {}
2020 pub use super::TIM2EN::RW;
2021 }
2022
2023 /// TIM5 clock enable
2024 pub mod TIM5EN {
2025 /// Offset (3 bits)
2026 pub const offset: u32 = 3;
2027 /// Mask (1 bit: 1 << 3)
2028 pub const mask: u32 = 1 << offset;
2029 /// Read-only values (empty)
2030 pub mod R {}
2031 /// Write-only values (empty)
2032 pub mod W {}
2033 pub use super::TIM2EN::RW;
2034 }
2035
2036 /// TIM6 clock enable
2037 pub mod TIM6EN {
2038 /// Offset (4 bits)
2039 pub const offset: u32 = 4;
2040 /// Mask (1 bit: 1 << 4)
2041 pub const mask: u32 = 1 << offset;
2042 /// Read-only values (empty)
2043 pub mod R {}
2044 /// Write-only values (empty)
2045 pub mod W {}
2046 pub use super::TIM2EN::RW;
2047 }
2048
2049 /// TIM7 clock enable
2050 pub mod TIM7EN {
2051 /// Offset (5 bits)
2052 pub const offset: u32 = 5;
2053 /// Mask (1 bit: 1 << 5)
2054 pub const mask: u32 = 1 << offset;
2055 /// Read-only values (empty)
2056 pub mod R {}
2057 /// Write-only values (empty)
2058 pub mod W {}
2059 pub use super::TIM2EN::RW;
2060 }
2061
2062 /// TIM12 clock enable
2063 pub mod TIM12EN {
2064 /// Offset (6 bits)
2065 pub const offset: u32 = 6;
2066 /// Mask (1 bit: 1 << 6)
2067 pub const mask: u32 = 1 << offset;
2068 /// Read-only values (empty)
2069 pub mod R {}
2070 /// Write-only values (empty)
2071 pub mod W {}
2072 pub use super::TIM2EN::RW;
2073 }
2074
2075 /// TIM13 clock enable
2076 pub mod TIM13EN {
2077 /// Offset (7 bits)
2078 pub const offset: u32 = 7;
2079 /// Mask (1 bit: 1 << 7)
2080 pub const mask: u32 = 1 << offset;
2081 /// Read-only values (empty)
2082 pub mod R {}
2083 /// Write-only values (empty)
2084 pub mod W {}
2085 pub use super::TIM2EN::RW;
2086 }
2087
2088 /// TIM14 clock enable
2089 pub mod TIM14EN {
2090 /// Offset (8 bits)
2091 pub const offset: u32 = 8;
2092 /// Mask (1 bit: 1 << 8)
2093 pub const mask: u32 = 1 << offset;
2094 /// Read-only values (empty)
2095 pub mod R {}
2096 /// Write-only values (empty)
2097 pub mod W {}
2098 pub use super::TIM2EN::RW;
2099 }
2100
2101 /// Window watchdog clock enable
2102 pub mod WWDGEN {
2103 /// Offset (11 bits)
2104 pub const offset: u32 = 11;
2105 /// Mask (1 bit: 1 << 11)
2106 pub const mask: u32 = 1 << offset;
2107 /// Read-only values (empty)
2108 pub mod R {}
2109 /// Write-only values (empty)
2110 pub mod W {}
2111 pub use super::TIM2EN::RW;
2112 }
2113
2114 /// SPI2 clock enable
2115 pub mod SPI2EN {
2116 /// Offset (14 bits)
2117 pub const offset: u32 = 14;
2118 /// Mask (1 bit: 1 << 14)
2119 pub const mask: u32 = 1 << offset;
2120 /// Read-only values (empty)
2121 pub mod R {}
2122 /// Write-only values (empty)
2123 pub mod W {}
2124 pub use super::TIM2EN::RW;
2125 }
2126
2127 /// SPI3 clock enable
2128 pub mod SPI3EN {
2129 /// Offset (15 bits)
2130 pub const offset: u32 = 15;
2131 /// Mask (1 bit: 1 << 15)
2132 pub const mask: u32 = 1 << offset;
2133 /// Read-only values (empty)
2134 pub mod R {}
2135 /// Write-only values (empty)
2136 pub mod W {}
2137 pub use super::TIM2EN::RW;
2138 }
2139
2140 /// SPDIF-IN clock enable
2141 pub mod SPDIFEN {
2142 /// Offset (16 bits)
2143 pub const offset: u32 = 16;
2144 /// Mask (1 bit: 1 << 16)
2145 pub const mask: u32 = 1 << offset;
2146 /// Read-only values (empty)
2147 pub mod R {}
2148 /// Write-only values (empty)
2149 pub mod W {}
2150 pub use super::TIM2EN::RW;
2151 }
2152
2153 /// USART 2 clock enable
2154 pub mod USART2EN {
2155 /// Offset (17 bits)
2156 pub const offset: u32 = 17;
2157 /// Mask (1 bit: 1 << 17)
2158 pub const mask: u32 = 1 << offset;
2159 /// Read-only values (empty)
2160 pub mod R {}
2161 /// Write-only values (empty)
2162 pub mod W {}
2163 pub use super::TIM2EN::RW;
2164 }
2165
2166 /// USART3 clock enable
2167 pub mod USART3EN {
2168 /// Offset (18 bits)
2169 pub const offset: u32 = 18;
2170 /// Mask (1 bit: 1 << 18)
2171 pub const mask: u32 = 1 << offset;
2172 /// Read-only values (empty)
2173 pub mod R {}
2174 /// Write-only values (empty)
2175 pub mod W {}
2176 pub use super::TIM2EN::RW;
2177 }
2178
2179 /// UART4 clock enable
2180 pub mod UART4EN {
2181 /// Offset (19 bits)
2182 pub const offset: u32 = 19;
2183 /// Mask (1 bit: 1 << 19)
2184 pub const mask: u32 = 1 << offset;
2185 /// Read-only values (empty)
2186 pub mod R {}
2187 /// Write-only values (empty)
2188 pub mod W {}
2189 pub use super::TIM2EN::RW;
2190 }
2191
2192 /// UART5 clock enable
2193 pub mod UART5EN {
2194 /// Offset (20 bits)
2195 pub const offset: u32 = 20;
2196 /// Mask (1 bit: 1 << 20)
2197 pub const mask: u32 = 1 << offset;
2198 /// Read-only values (empty)
2199 pub mod R {}
2200 /// Write-only values (empty)
2201 pub mod W {}
2202 pub use super::TIM2EN::RW;
2203 }
2204
2205 /// I2C1 clock enable
2206 pub mod I2C1EN {
2207 /// Offset (21 bits)
2208 pub const offset: u32 = 21;
2209 /// Mask (1 bit: 1 << 21)
2210 pub const mask: u32 = 1 << offset;
2211 /// Read-only values (empty)
2212 pub mod R {}
2213 /// Write-only values (empty)
2214 pub mod W {}
2215 pub use super::TIM2EN::RW;
2216 }
2217
2218 /// I2C2 clock enable
2219 pub mod I2C2EN {
2220 /// Offset (22 bits)
2221 pub const offset: u32 = 22;
2222 /// Mask (1 bit: 1 << 22)
2223 pub const mask: u32 = 1 << offset;
2224 /// Read-only values (empty)
2225 pub mod R {}
2226 /// Write-only values (empty)
2227 pub mod W {}
2228 pub use super::TIM2EN::RW;
2229 }
2230
2231 /// I2C3 clock enable
2232 pub mod I2C3EN {
2233 /// Offset (23 bits)
2234 pub const offset: u32 = 23;
2235 /// Mask (1 bit: 1 << 23)
2236 pub const mask: u32 = 1 << offset;
2237 /// Read-only values (empty)
2238 pub mod R {}
2239 /// Write-only values (empty)
2240 pub mod W {}
2241 pub use super::TIM2EN::RW;
2242 }
2243
2244 /// FMPI2C1 clock enable
2245 pub mod FMPI2C1EN {
2246 /// Offset (24 bits)
2247 pub const offset: u32 = 24;
2248 /// Mask (1 bit: 1 << 24)
2249 pub const mask: u32 = 1 << offset;
2250 /// Read-only values (empty)
2251 pub mod R {}
2252 /// Write-only values (empty)
2253 pub mod W {}
2254 pub use super::TIM2EN::RW;
2255 }
2256
2257 /// CAN 1 clock enable
2258 pub mod CAN1EN {
2259 /// Offset (25 bits)
2260 pub const offset: u32 = 25;
2261 /// Mask (1 bit: 1 << 25)
2262 pub const mask: u32 = 1 << offset;
2263 /// Read-only values (empty)
2264 pub mod R {}
2265 /// Write-only values (empty)
2266 pub mod W {}
2267 pub use super::TIM2EN::RW;
2268 }
2269
2270 /// CAN 2 clock enable
2271 pub mod CAN2EN {
2272 /// Offset (26 bits)
2273 pub const offset: u32 = 26;
2274 /// Mask (1 bit: 1 << 26)
2275 pub const mask: u32 = 1 << offset;
2276 /// Read-only values (empty)
2277 pub mod R {}
2278 /// Write-only values (empty)
2279 pub mod W {}
2280 pub use super::TIM2EN::RW;
2281 }
2282
2283 /// CEC interface clock enable
2284 pub mod CECEN {
2285 /// Offset (27 bits)
2286 pub const offset: u32 = 27;
2287 /// Mask (1 bit: 1 << 27)
2288 pub const mask: u32 = 1 << offset;
2289 /// Read-only values (empty)
2290 pub mod R {}
2291 /// Write-only values (empty)
2292 pub mod W {}
2293 pub use super::TIM2EN::RW;
2294 }
2295
2296 /// Power interface clock enable
2297 pub mod PWREN {
2298 /// Offset (28 bits)
2299 pub const offset: u32 = 28;
2300 /// Mask (1 bit: 1 << 28)
2301 pub const mask: u32 = 1 << offset;
2302 /// Read-only values (empty)
2303 pub mod R {}
2304 /// Write-only values (empty)
2305 pub mod W {}
2306 pub use super::TIM2EN::RW;
2307 }
2308
2309 /// DAC interface clock enable
2310 pub mod DACEN {
2311 /// Offset (29 bits)
2312 pub const offset: u32 = 29;
2313 /// Mask (1 bit: 1 << 29)
2314 pub const mask: u32 = 1 << offset;
2315 /// Read-only values (empty)
2316 pub mod R {}
2317 /// Write-only values (empty)
2318 pub mod W {}
2319 pub use super::TIM2EN::RW;
2320 }
2321}
2322
2323/// APB2 peripheral clock enable register
2324pub mod APB2ENR {
2325
2326 /// TIM1 clock enable
2327 pub mod TIM1EN {
2328 /// Offset (0 bits)
2329 pub const offset: u32 = 0;
2330 /// Mask (1 bit: 1 << 0)
2331 pub const mask: u32 = 1 << offset;
2332 /// Read-only values (empty)
2333 pub mod R {}
2334 /// Write-only values (empty)
2335 pub mod W {}
2336 /// Read-write values
2337 pub mod RW {
2338
2339 /// 0b0: The selected clock is disabled
2340 pub const Disabled: u32 = 0b0;
2341
2342 /// 0b1: The selected clock is enabled
2343 pub const Enabled: u32 = 0b1;
2344 }
2345 }
2346
2347 /// TIM8 clock enable
2348 pub mod TIM8EN {
2349 /// Offset (1 bits)
2350 pub const offset: u32 = 1;
2351 /// Mask (1 bit: 1 << 1)
2352 pub const mask: u32 = 1 << offset;
2353 /// Read-only values (empty)
2354 pub mod R {}
2355 /// Write-only values (empty)
2356 pub mod W {}
2357 pub use super::TIM1EN::RW;
2358 }
2359
2360 /// USART1 clock enable
2361 pub mod USART1EN {
2362 /// Offset (4 bits)
2363 pub const offset: u32 = 4;
2364 /// Mask (1 bit: 1 << 4)
2365 pub const mask: u32 = 1 << offset;
2366 /// Read-only values (empty)
2367 pub mod R {}
2368 /// Write-only values (empty)
2369 pub mod W {}
2370 pub use super::TIM1EN::RW;
2371 }
2372
2373 /// USART6 clock enable
2374 pub mod USART6EN {
2375 /// Offset (5 bits)
2376 pub const offset: u32 = 5;
2377 /// Mask (1 bit: 1 << 5)
2378 pub const mask: u32 = 1 << offset;
2379 /// Read-only values (empty)
2380 pub mod R {}
2381 /// Write-only values (empty)
2382 pub mod W {}
2383 pub use super::TIM1EN::RW;
2384 }
2385
2386 /// ADC1 clock enable
2387 pub mod ADC1EN {
2388 /// Offset (8 bits)
2389 pub const offset: u32 = 8;
2390 /// Mask (1 bit: 1 << 8)
2391 pub const mask: u32 = 1 << offset;
2392 /// Read-only values (empty)
2393 pub mod R {}
2394 /// Write-only values (empty)
2395 pub mod W {}
2396 pub use super::TIM1EN::RW;
2397 }
2398
2399 /// ADC2 clock enable
2400 pub mod ADC2EN {
2401 /// Offset (9 bits)
2402 pub const offset: u32 = 9;
2403 /// Mask (1 bit: 1 << 9)
2404 pub const mask: u32 = 1 << offset;
2405 /// Read-only values (empty)
2406 pub mod R {}
2407 /// Write-only values (empty)
2408 pub mod W {}
2409 pub use super::TIM1EN::RW;
2410 }
2411
2412 /// ADC3 clock enable
2413 pub mod ADC3EN {
2414 /// Offset (10 bits)
2415 pub const offset: u32 = 10;
2416 /// Mask (1 bit: 1 << 10)
2417 pub const mask: u32 = 1 << offset;
2418 /// Read-only values (empty)
2419 pub mod R {}
2420 /// Write-only values (empty)
2421 pub mod W {}
2422 pub use super::TIM1EN::RW;
2423 }
2424
2425 /// SDIO clock enable
2426 pub mod SDIOEN {
2427 /// Offset (11 bits)
2428 pub const offset: u32 = 11;
2429 /// Mask (1 bit: 1 << 11)
2430 pub const mask: u32 = 1 << offset;
2431 /// Read-only values (empty)
2432 pub mod R {}
2433 /// Write-only values (empty)
2434 pub mod W {}
2435 pub use super::TIM1EN::RW;
2436 }
2437
2438 /// SPI1 clock enable
2439 pub mod SPI1EN {
2440 /// Offset (12 bits)
2441 pub const offset: u32 = 12;
2442 /// Mask (1 bit: 1 << 12)
2443 pub const mask: u32 = 1 << offset;
2444 /// Read-only values (empty)
2445 pub mod R {}
2446 /// Write-only values (empty)
2447 pub mod W {}
2448 pub use super::TIM1EN::RW;
2449 }
2450
2451 /// SPI4 clock enable
2452 pub mod SPI4EN {
2453 /// Offset (13 bits)
2454 pub const offset: u32 = 13;
2455 /// Mask (1 bit: 1 << 13)
2456 pub const mask: u32 = 1 << offset;
2457 /// Read-only values (empty)
2458 pub mod R {}
2459 /// Write-only values (empty)
2460 pub mod W {}
2461 pub use super::TIM1EN::RW;
2462 }
2463
2464 /// System configuration controller clock enable
2465 pub mod SYSCFGEN {
2466 /// Offset (14 bits)
2467 pub const offset: u32 = 14;
2468 /// Mask (1 bit: 1 << 14)
2469 pub const mask: u32 = 1 << offset;
2470 /// Read-only values (empty)
2471 pub mod R {}
2472 /// Write-only values (empty)
2473 pub mod W {}
2474 pub use super::TIM1EN::RW;
2475 }
2476
2477 /// TIM9 clock enable
2478 pub mod TIM9EN {
2479 /// Offset (16 bits)
2480 pub const offset: u32 = 16;
2481 /// Mask (1 bit: 1 << 16)
2482 pub const mask: u32 = 1 << offset;
2483 /// Read-only values (empty)
2484 pub mod R {}
2485 /// Write-only values (empty)
2486 pub mod W {}
2487 pub use super::TIM1EN::RW;
2488 }
2489
2490 /// TIM10 clock enable
2491 pub mod TIM10EN {
2492 /// Offset (17 bits)
2493 pub const offset: u32 = 17;
2494 /// Mask (1 bit: 1 << 17)
2495 pub const mask: u32 = 1 << offset;
2496 /// Read-only values (empty)
2497 pub mod R {}
2498 /// Write-only values (empty)
2499 pub mod W {}
2500 pub use super::TIM1EN::RW;
2501 }
2502
2503 /// TIM11 clock enable
2504 pub mod TIM11EN {
2505 /// Offset (18 bits)
2506 pub const offset: u32 = 18;
2507 /// Mask (1 bit: 1 << 18)
2508 pub const mask: u32 = 1 << offset;
2509 /// Read-only values (empty)
2510 pub mod R {}
2511 /// Write-only values (empty)
2512 pub mod W {}
2513 pub use super::TIM1EN::RW;
2514 }
2515
2516 /// SAI1 clock enable
2517 pub mod SAI1EN {
2518 /// Offset (22 bits)
2519 pub const offset: u32 = 22;
2520 /// Mask (1 bit: 1 << 22)
2521 pub const mask: u32 = 1 << offset;
2522 /// Read-only values (empty)
2523 pub mod R {}
2524 /// Write-only values (empty)
2525 pub mod W {}
2526 pub use super::TIM1EN::RW;
2527 }
2528
2529 /// SAI2 clock enable
2530 pub mod SAI2EN {
2531 /// Offset (23 bits)
2532 pub const offset: u32 = 23;
2533 /// Mask (1 bit: 1 << 23)
2534 pub const mask: u32 = 1 << offset;
2535 /// Read-only values (empty)
2536 pub mod R {}
2537 /// Write-only values (empty)
2538 pub mod W {}
2539 pub use super::TIM1EN::RW;
2540 }
2541}
2542
2543/// AHB1 peripheral clock enable in low power mode register
2544pub mod AHB1LPENR {
2545
2546 /// IO port A clock enable during sleep mode
2547 pub mod GPIOALPEN {
2548 /// Offset (0 bits)
2549 pub const offset: u32 = 0;
2550 /// Mask (1 bit: 1 << 0)
2551 pub const mask: u32 = 1 << offset;
2552 /// Read-only values (empty)
2553 pub mod R {}
2554 /// Write-only values (empty)
2555 pub mod W {}
2556 /// Read-write values
2557 pub mod RW {
2558
2559 /// 0b0: Selected module is disabled during Sleep mode
2560 pub const DisabledInSleep: u32 = 0b0;
2561
2562 /// 0b1: Selected module is enabled during Sleep mode
2563 pub const EnabledInSleep: u32 = 0b1;
2564 }
2565 }
2566
2567 /// IO port B clock enable during Sleep mode
2568 pub mod GPIOBLPEN {
2569 /// Offset (1 bits)
2570 pub const offset: u32 = 1;
2571 /// Mask (1 bit: 1 << 1)
2572 pub const mask: u32 = 1 << offset;
2573 /// Read-only values (empty)
2574 pub mod R {}
2575 /// Write-only values (empty)
2576 pub mod W {}
2577 pub use super::GPIOALPEN::RW;
2578 }
2579
2580 /// IO port C clock enable during Sleep mode
2581 pub mod GPIOCLPEN {
2582 /// Offset (2 bits)
2583 pub const offset: u32 = 2;
2584 /// Mask (1 bit: 1 << 2)
2585 pub const mask: u32 = 1 << offset;
2586 /// Read-only values (empty)
2587 pub mod R {}
2588 /// Write-only values (empty)
2589 pub mod W {}
2590 pub use super::GPIOALPEN::RW;
2591 }
2592
2593 /// IO port D clock enable during Sleep mode
2594 pub mod GPIODLPEN {
2595 /// Offset (3 bits)
2596 pub const offset: u32 = 3;
2597 /// Mask (1 bit: 1 << 3)
2598 pub const mask: u32 = 1 << offset;
2599 /// Read-only values (empty)
2600 pub mod R {}
2601 /// Write-only values (empty)
2602 pub mod W {}
2603 pub use super::GPIOALPEN::RW;
2604 }
2605
2606 /// IO port E clock enable during Sleep mode
2607 pub mod GPIOELPEN {
2608 /// Offset (4 bits)
2609 pub const offset: u32 = 4;
2610 /// Mask (1 bit: 1 << 4)
2611 pub const mask: u32 = 1 << offset;
2612 /// Read-only values (empty)
2613 pub mod R {}
2614 /// Write-only values (empty)
2615 pub mod W {}
2616 pub use super::GPIOALPEN::RW;
2617 }
2618
2619 /// IO port F clock enable during Sleep mode
2620 pub mod GPIOFLPEN {
2621 /// Offset (5 bits)
2622 pub const offset: u32 = 5;
2623 /// Mask (1 bit: 1 << 5)
2624 pub const mask: u32 = 1 << offset;
2625 /// Read-only values (empty)
2626 pub mod R {}
2627 /// Write-only values (empty)
2628 pub mod W {}
2629 pub use super::GPIOALPEN::RW;
2630 }
2631
2632 /// IO port G clock enable during Sleep mode
2633 pub mod GPIOGLPEN {
2634 /// Offset (6 bits)
2635 pub const offset: u32 = 6;
2636 /// Mask (1 bit: 1 << 6)
2637 pub const mask: u32 = 1 << offset;
2638 /// Read-only values (empty)
2639 pub mod R {}
2640 /// Write-only values (empty)
2641 pub mod W {}
2642 pub use super::GPIOALPEN::RW;
2643 }
2644
2645 /// IO port H clock enable during Sleep mode
2646 pub mod GPIOHLPEN {
2647 /// Offset (7 bits)
2648 pub const offset: u32 = 7;
2649 /// Mask (1 bit: 1 << 7)
2650 pub const mask: u32 = 1 << offset;
2651 /// Read-only values (empty)
2652 pub mod R {}
2653 /// Write-only values (empty)
2654 pub mod W {}
2655 pub use super::GPIOALPEN::RW;
2656 }
2657
2658 /// CRC clock enable during Sleep mode
2659 pub mod CRCLPEN {
2660 /// Offset (12 bits)
2661 pub const offset: u32 = 12;
2662 /// Mask (1 bit: 1 << 12)
2663 pub const mask: u32 = 1 << offset;
2664 /// Read-only values (empty)
2665 pub mod R {}
2666 /// Write-only values (empty)
2667 pub mod W {}
2668 pub use super::GPIOALPEN::RW;
2669 }
2670
2671 /// Flash interface clock enable during Sleep mode
2672 pub mod FLITFLPEN {
2673 /// Offset (15 bits)
2674 pub const offset: u32 = 15;
2675 /// Mask (1 bit: 1 << 15)
2676 pub const mask: u32 = 1 << offset;
2677 /// Read-only values (empty)
2678 pub mod R {}
2679 /// Write-only values (empty)
2680 pub mod W {}
2681 pub use super::GPIOALPEN::RW;
2682 }
2683
2684 /// SRAM 1interface clock enable during Sleep mode
2685 pub mod SRAM1LPEN {
2686 /// Offset (16 bits)
2687 pub const offset: u32 = 16;
2688 /// Mask (1 bit: 1 << 16)
2689 pub const mask: u32 = 1 << offset;
2690 /// Read-only values (empty)
2691 pub mod R {}
2692 /// Write-only values (empty)
2693 pub mod W {}
2694 pub use super::GPIOALPEN::RW;
2695 }
2696
2697 /// SRAM 2 interface clock enable during Sleep mode
2698 pub mod SRAM2LPEN {
2699 /// Offset (17 bits)
2700 pub const offset: u32 = 17;
2701 /// Mask (1 bit: 1 << 17)
2702 pub const mask: u32 = 1 << offset;
2703 /// Read-only values (empty)
2704 pub mod R {}
2705 /// Write-only values (empty)
2706 pub mod W {}
2707 pub use super::GPIOALPEN::RW;
2708 }
2709
2710 /// Backup SRAM interface clock enable during Sleep mode
2711 pub mod BKPSRAMLPEN {
2712 /// Offset (18 bits)
2713 pub const offset: u32 = 18;
2714 /// Mask (1 bit: 1 << 18)
2715 pub const mask: u32 = 1 << offset;
2716 /// Read-only values (empty)
2717 pub mod R {}
2718 /// Write-only values (empty)
2719 pub mod W {}
2720 pub use super::GPIOALPEN::RW;
2721 }
2722
2723 /// DMA1 clock enable during Sleep mode
2724 pub mod DMA1LPEN {
2725 /// Offset (21 bits)
2726 pub const offset: u32 = 21;
2727 /// Mask (1 bit: 1 << 21)
2728 pub const mask: u32 = 1 << offset;
2729 /// Read-only values (empty)
2730 pub mod R {}
2731 /// Write-only values (empty)
2732 pub mod W {}
2733 pub use super::GPIOALPEN::RW;
2734 }
2735
2736 /// DMA2 clock enable during Sleep mode
2737 pub mod DMA2LPEN {
2738 /// Offset (22 bits)
2739 pub const offset: u32 = 22;
2740 /// Mask (1 bit: 1 << 22)
2741 pub const mask: u32 = 1 << offset;
2742 /// Read-only values (empty)
2743 pub mod R {}
2744 /// Write-only values (empty)
2745 pub mod W {}
2746 pub use super::GPIOALPEN::RW;
2747 }
2748
2749 /// USB OTG HS clock enable during Sleep mode
2750 pub mod OTGHSLPEN {
2751 /// Offset (29 bits)
2752 pub const offset: u32 = 29;
2753 /// Mask (1 bit: 1 << 29)
2754 pub const mask: u32 = 1 << offset;
2755 /// Read-only values (empty)
2756 pub mod R {}
2757 /// Write-only values (empty)
2758 pub mod W {}
2759 pub use super::GPIOALPEN::RW;
2760 }
2761
2762 /// USB OTG HS ULPI clock enable during Sleep mode
2763 pub mod OTGHSULPILPEN {
2764 /// Offset (30 bits)
2765 pub const offset: u32 = 30;
2766 /// Mask (1 bit: 1 << 30)
2767 pub const mask: u32 = 1 << offset;
2768 /// Read-only values (empty)
2769 pub mod R {}
2770 /// Write-only values (empty)
2771 pub mod W {}
2772 pub use super::GPIOALPEN::RW;
2773 }
2774}
2775
2776/// AHB2 peripheral clock enable in low power mode register
2777pub mod AHB2LPENR {
2778
2779 /// USB OTG FS clock enable during Sleep mode
2780 pub mod OTGFSLPEN {
2781 /// Offset (7 bits)
2782 pub const offset: u32 = 7;
2783 /// Mask (1 bit: 1 << 7)
2784 pub const mask: u32 = 1 << offset;
2785 /// Read-only values (empty)
2786 pub mod R {}
2787 /// Write-only values (empty)
2788 pub mod W {}
2789 /// Read-write values
2790 pub mod RW {
2791
2792 /// 0b0: Selected module is disabled during Sleep mode
2793 pub const DisabledInSleep: u32 = 0b0;
2794
2795 /// 0b1: Selected module is enabled during Sleep mode
2796 pub const EnabledInSleep: u32 = 0b1;
2797 }
2798 }
2799
2800 /// Camera interface enable during Sleep mode
2801 pub mod DCMILPEN {
2802 /// Offset (0 bits)
2803 pub const offset: u32 = 0;
2804 /// Mask (1 bit: 1 << 0)
2805 pub const mask: u32 = 1 << offset;
2806 /// Read-only values (empty)
2807 pub mod R {}
2808 /// Write-only values (empty)
2809 pub mod W {}
2810 pub use super::OTGFSLPEN::RW;
2811 }
2812}
2813
2814/// AHB3 peripheral clock enable in low power mode register
2815pub mod AHB3LPENR {
2816
2817 /// Flexible memory controller module clock enable during Sleep mode
2818 pub mod FMCLPEN {
2819 /// Offset (0 bits)
2820 pub const offset: u32 = 0;
2821 /// Mask (1 bit: 1 << 0)
2822 pub const mask: u32 = 1 << offset;
2823 /// Read-only values (empty)
2824 pub mod R {}
2825 /// Write-only values (empty)
2826 pub mod W {}
2827 /// Read-write values
2828 pub mod RW {
2829
2830 /// 0b0: Selected module is disabled during Sleep mode
2831 pub const DisabledInSleep: u32 = 0b0;
2832
2833 /// 0b1: Selected module is enabled during Sleep mode
2834 pub const EnabledInSleep: u32 = 0b1;
2835 }
2836 }
2837
2838 /// QUADSPI memory controller module clock enable during Sleep mode
2839 pub mod QSPILPEN {
2840 /// Offset (1 bits)
2841 pub const offset: u32 = 1;
2842 /// Mask (1 bit: 1 << 1)
2843 pub const mask: u32 = 1 << offset;
2844 /// Read-only values (empty)
2845 pub mod R {}
2846 /// Write-only values (empty)
2847 pub mod W {}
2848 pub use super::FMCLPEN::RW;
2849 }
2850}
2851
2852/// APB1 peripheral clock enable in low power mode register
2853pub mod APB1LPENR {
2854
2855 /// TIM2 clock enable during Sleep mode
2856 pub mod TIM2LPEN {
2857 /// Offset (0 bits)
2858 pub const offset: u32 = 0;
2859 /// Mask (1 bit: 1 << 0)
2860 pub const mask: u32 = 1 << offset;
2861 /// Read-only values (empty)
2862 pub mod R {}
2863 /// Write-only values (empty)
2864 pub mod W {}
2865 /// Read-write values
2866 pub mod RW {
2867
2868 /// 0b0: Selected module is disabled during Sleep mode
2869 pub const DisabledInSleep: u32 = 0b0;
2870
2871 /// 0b1: Selected module is enabled during Sleep mode
2872 pub const EnabledInSleep: u32 = 0b1;
2873 }
2874 }
2875
2876 /// TIM3 clock enable during Sleep mode
2877 pub mod TIM3LPEN {
2878 /// Offset (1 bits)
2879 pub const offset: u32 = 1;
2880 /// Mask (1 bit: 1 << 1)
2881 pub const mask: u32 = 1 << offset;
2882 /// Read-only values (empty)
2883 pub mod R {}
2884 /// Write-only values (empty)
2885 pub mod W {}
2886 pub use super::TIM2LPEN::RW;
2887 }
2888
2889 /// TIM4 clock enable during Sleep mode
2890 pub mod TIM4LPEN {
2891 /// Offset (2 bits)
2892 pub const offset: u32 = 2;
2893 /// Mask (1 bit: 1 << 2)
2894 pub const mask: u32 = 1 << offset;
2895 /// Read-only values (empty)
2896 pub mod R {}
2897 /// Write-only values (empty)
2898 pub mod W {}
2899 pub use super::TIM2LPEN::RW;
2900 }
2901
2902 /// TIM5 clock enable during Sleep mode
2903 pub mod TIM5LPEN {
2904 /// Offset (3 bits)
2905 pub const offset: u32 = 3;
2906 /// Mask (1 bit: 1 << 3)
2907 pub const mask: u32 = 1 << offset;
2908 /// Read-only values (empty)
2909 pub mod R {}
2910 /// Write-only values (empty)
2911 pub mod W {}
2912 pub use super::TIM2LPEN::RW;
2913 }
2914
2915 /// TIM6 clock enable during Sleep mode
2916 pub mod TIM6LPEN {
2917 /// Offset (4 bits)
2918 pub const offset: u32 = 4;
2919 /// Mask (1 bit: 1 << 4)
2920 pub const mask: u32 = 1 << offset;
2921 /// Read-only values (empty)
2922 pub mod R {}
2923 /// Write-only values (empty)
2924 pub mod W {}
2925 pub use super::TIM2LPEN::RW;
2926 }
2927
2928 /// TIM7 clock enable during Sleep mode
2929 pub mod TIM7LPEN {
2930 /// Offset (5 bits)
2931 pub const offset: u32 = 5;
2932 /// Mask (1 bit: 1 << 5)
2933 pub const mask: u32 = 1 << offset;
2934 /// Read-only values (empty)
2935 pub mod R {}
2936 /// Write-only values (empty)
2937 pub mod W {}
2938 pub use super::TIM2LPEN::RW;
2939 }
2940
2941 /// TIM12 clock enable during Sleep mode
2942 pub mod TIM12LPEN {
2943 /// Offset (6 bits)
2944 pub const offset: u32 = 6;
2945 /// Mask (1 bit: 1 << 6)
2946 pub const mask: u32 = 1 << offset;
2947 /// Read-only values (empty)
2948 pub mod R {}
2949 /// Write-only values (empty)
2950 pub mod W {}
2951 pub use super::TIM2LPEN::RW;
2952 }
2953
2954 /// TIM13 clock enable during Sleep mode
2955 pub mod TIM13LPEN {
2956 /// Offset (7 bits)
2957 pub const offset: u32 = 7;
2958 /// Mask (1 bit: 1 << 7)
2959 pub const mask: u32 = 1 << offset;
2960 /// Read-only values (empty)
2961 pub mod R {}
2962 /// Write-only values (empty)
2963 pub mod W {}
2964 pub use super::TIM2LPEN::RW;
2965 }
2966
2967 /// TIM14 clock enable during Sleep mode
2968 pub mod TIM14LPEN {
2969 /// Offset (8 bits)
2970 pub const offset: u32 = 8;
2971 /// Mask (1 bit: 1 << 8)
2972 pub const mask: u32 = 1 << offset;
2973 /// Read-only values (empty)
2974 pub mod R {}
2975 /// Write-only values (empty)
2976 pub mod W {}
2977 pub use super::TIM2LPEN::RW;
2978 }
2979
2980 /// Window watchdog clock enable during Sleep mode
2981 pub mod WWDGLPEN {
2982 /// Offset (11 bits)
2983 pub const offset: u32 = 11;
2984 /// Mask (1 bit: 1 << 11)
2985 pub const mask: u32 = 1 << offset;
2986 /// Read-only values (empty)
2987 pub mod R {}
2988 /// Write-only values (empty)
2989 pub mod W {}
2990 pub use super::TIM2LPEN::RW;
2991 }
2992
2993 /// SPI2 clock enable during Sleep mode
2994 pub mod SPI2LPEN {
2995 /// Offset (14 bits)
2996 pub const offset: u32 = 14;
2997 /// Mask (1 bit: 1 << 14)
2998 pub const mask: u32 = 1 << offset;
2999 /// Read-only values (empty)
3000 pub mod R {}
3001 /// Write-only values (empty)
3002 pub mod W {}
3003 pub use super::TIM2LPEN::RW;
3004 }
3005
3006 /// SPI3 clock enable during Sleep mode
3007 pub mod SPI3LPEN {
3008 /// Offset (15 bits)
3009 pub const offset: u32 = 15;
3010 /// Mask (1 bit: 1 << 15)
3011 pub const mask: u32 = 1 << offset;
3012 /// Read-only values (empty)
3013 pub mod R {}
3014 /// Write-only values (empty)
3015 pub mod W {}
3016 pub use super::TIM2LPEN::RW;
3017 }
3018
3019 /// SPDIF clock enable during Sleep mode
3020 pub mod SPDIFLPEN {
3021 /// Offset (16 bits)
3022 pub const offset: u32 = 16;
3023 /// Mask (1 bit: 1 << 16)
3024 pub const mask: u32 = 1 << offset;
3025 /// Read-only values (empty)
3026 pub mod R {}
3027 /// Write-only values (empty)
3028 pub mod W {}
3029 pub use super::TIM2LPEN::RW;
3030 }
3031
3032 /// USART2 clock enable during Sleep mode
3033 pub mod USART2LPEN {
3034 /// Offset (17 bits)
3035 pub const offset: u32 = 17;
3036 /// Mask (1 bit: 1 << 17)
3037 pub const mask: u32 = 1 << offset;
3038 /// Read-only values (empty)
3039 pub mod R {}
3040 /// Write-only values (empty)
3041 pub mod W {}
3042 pub use super::TIM2LPEN::RW;
3043 }
3044
3045 /// USART3 clock enable during Sleep mode
3046 pub mod USART3LPEN {
3047 /// Offset (18 bits)
3048 pub const offset: u32 = 18;
3049 /// Mask (1 bit: 1 << 18)
3050 pub const mask: u32 = 1 << offset;
3051 /// Read-only values (empty)
3052 pub mod R {}
3053 /// Write-only values (empty)
3054 pub mod W {}
3055 pub use super::TIM2LPEN::RW;
3056 }
3057
3058 /// UART4 clock enable during Sleep mode
3059 pub mod UART4LPEN {
3060 /// Offset (19 bits)
3061 pub const offset: u32 = 19;
3062 /// Mask (1 bit: 1 << 19)
3063 pub const mask: u32 = 1 << offset;
3064 /// Read-only values (empty)
3065 pub mod R {}
3066 /// Write-only values (empty)
3067 pub mod W {}
3068 pub use super::TIM2LPEN::RW;
3069 }
3070
3071 /// UART5 clock enable during Sleep mode
3072 pub mod UART5LPEN {
3073 /// Offset (20 bits)
3074 pub const offset: u32 = 20;
3075 /// Mask (1 bit: 1 << 20)
3076 pub const mask: u32 = 1 << offset;
3077 /// Read-only values (empty)
3078 pub mod R {}
3079 /// Write-only values (empty)
3080 pub mod W {}
3081 pub use super::TIM2LPEN::RW;
3082 }
3083
3084 /// I2C1 clock enable during Sleep mode
3085 pub mod I2C1LPEN {
3086 /// Offset (21 bits)
3087 pub const offset: u32 = 21;
3088 /// Mask (1 bit: 1 << 21)
3089 pub const mask: u32 = 1 << offset;
3090 /// Read-only values (empty)
3091 pub mod R {}
3092 /// Write-only values (empty)
3093 pub mod W {}
3094 pub use super::TIM2LPEN::RW;
3095 }
3096
3097 /// I2C2 clock enable during Sleep mode
3098 pub mod I2C2LPEN {
3099 /// Offset (22 bits)
3100 pub const offset: u32 = 22;
3101 /// Mask (1 bit: 1 << 22)
3102 pub const mask: u32 = 1 << offset;
3103 /// Read-only values (empty)
3104 pub mod R {}
3105 /// Write-only values (empty)
3106 pub mod W {}
3107 pub use super::TIM2LPEN::RW;
3108 }
3109
3110 /// I2C3 clock enable during Sleep mode
3111 pub mod I2C3LPEN {
3112 /// Offset (23 bits)
3113 pub const offset: u32 = 23;
3114 /// Mask (1 bit: 1 << 23)
3115 pub const mask: u32 = 1 << offset;
3116 /// Read-only values (empty)
3117 pub mod R {}
3118 /// Write-only values (empty)
3119 pub mod W {}
3120 pub use super::TIM2LPEN::RW;
3121 }
3122
3123 /// FMPI2C1 clock enable during Sleep
3124 pub mod FMPI2C1LPEN {
3125 /// Offset (24 bits)
3126 pub const offset: u32 = 24;
3127 /// Mask (1 bit: 1 << 24)
3128 pub const mask: u32 = 1 << offset;
3129 /// Read-only values (empty)
3130 pub mod R {}
3131 /// Write-only values (empty)
3132 pub mod W {}
3133 pub use super::TIM2LPEN::RW;
3134 }
3135
3136 /// CAN 1 clock enable during Sleep mode
3137 pub mod CAN1LPEN {
3138 /// Offset (25 bits)
3139 pub const offset: u32 = 25;
3140 /// Mask (1 bit: 1 << 25)
3141 pub const mask: u32 = 1 << offset;
3142 /// Read-only values (empty)
3143 pub mod R {}
3144 /// Write-only values (empty)
3145 pub mod W {}
3146 pub use super::TIM2LPEN::RW;
3147 }
3148
3149 /// CAN 2 clock enable during Sleep mode
3150 pub mod CAN2LPEN {
3151 /// Offset (26 bits)
3152 pub const offset: u32 = 26;
3153 /// Mask (1 bit: 1 << 26)
3154 pub const mask: u32 = 1 << offset;
3155 /// Read-only values (empty)
3156 pub mod R {}
3157 /// Write-only values (empty)
3158 pub mod W {}
3159 pub use super::TIM2LPEN::RW;
3160 }
3161
3162 /// CEC clock enable during Sleep mode
3163 pub mod CECLPEN {
3164 /// Offset (27 bits)
3165 pub const offset: u32 = 27;
3166 /// Mask (1 bit: 1 << 27)
3167 pub const mask: u32 = 1 << offset;
3168 /// Read-only values (empty)
3169 pub mod R {}
3170 /// Write-only values (empty)
3171 pub mod W {}
3172 pub use super::TIM2LPEN::RW;
3173 }
3174
3175 /// Power interface clock enable during Sleep mode
3176 pub mod PWRLPEN {
3177 /// Offset (28 bits)
3178 pub const offset: u32 = 28;
3179 /// Mask (1 bit: 1 << 28)
3180 pub const mask: u32 = 1 << offset;
3181 /// Read-only values (empty)
3182 pub mod R {}
3183 /// Write-only values (empty)
3184 pub mod W {}
3185 pub use super::TIM2LPEN::RW;
3186 }
3187
3188 /// DAC interface clock enable during Sleep mode
3189 pub mod DACLPEN {
3190 /// Offset (29 bits)
3191 pub const offset: u32 = 29;
3192 /// Mask (1 bit: 1 << 29)
3193 pub const mask: u32 = 1 << offset;
3194 /// Read-only values (empty)
3195 pub mod R {}
3196 /// Write-only values (empty)
3197 pub mod W {}
3198 pub use super::TIM2LPEN::RW;
3199 }
3200}
3201
3202/// APB2 peripheral clock enabled in low power mode register
3203pub mod APB2LPENR {
3204
3205 /// TIM1 clock enable during Sleep mode
3206 pub mod TIM1LPEN {
3207 /// Offset (0 bits)
3208 pub const offset: u32 = 0;
3209 /// Mask (1 bit: 1 << 0)
3210 pub const mask: u32 = 1 << offset;
3211 /// Read-only values (empty)
3212 pub mod R {}
3213 /// Write-only values (empty)
3214 pub mod W {}
3215 /// Read-write values
3216 pub mod RW {
3217
3218 /// 0b0: Selected module is disabled during Sleep mode
3219 pub const DisabledInSleep: u32 = 0b0;
3220
3221 /// 0b1: Selected module is enabled during Sleep mode
3222 pub const EnabledInSleep: u32 = 0b1;
3223 }
3224 }
3225
3226 /// TIM8 clock enable during Sleep mode
3227 pub mod TIM8LPEN {
3228 /// Offset (1 bits)
3229 pub const offset: u32 = 1;
3230 /// Mask (1 bit: 1 << 1)
3231 pub const mask: u32 = 1 << offset;
3232 /// Read-only values (empty)
3233 pub mod R {}
3234 /// Write-only values (empty)
3235 pub mod W {}
3236 pub use super::TIM1LPEN::RW;
3237 }
3238
3239 /// USART1 clock enable during Sleep mode
3240 pub mod USART1LPEN {
3241 /// Offset (4 bits)
3242 pub const offset: u32 = 4;
3243 /// Mask (1 bit: 1 << 4)
3244 pub const mask: u32 = 1 << offset;
3245 /// Read-only values (empty)
3246 pub mod R {}
3247 /// Write-only values (empty)
3248 pub mod W {}
3249 pub use super::TIM1LPEN::RW;
3250 }
3251
3252 /// USART6 clock enable during Sleep mode
3253 pub mod USART6LPEN {
3254 /// Offset (5 bits)
3255 pub const offset: u32 = 5;
3256 /// Mask (1 bit: 1 << 5)
3257 pub const mask: u32 = 1 << offset;
3258 /// Read-only values (empty)
3259 pub mod R {}
3260 /// Write-only values (empty)
3261 pub mod W {}
3262 pub use super::TIM1LPEN::RW;
3263 }
3264
3265 /// ADC1 clock enable during Sleep mode
3266 pub mod ADC1LPEN {
3267 /// Offset (8 bits)
3268 pub const offset: u32 = 8;
3269 /// Mask (1 bit: 1 << 8)
3270 pub const mask: u32 = 1 << offset;
3271 /// Read-only values (empty)
3272 pub mod R {}
3273 /// Write-only values (empty)
3274 pub mod W {}
3275 pub use super::TIM1LPEN::RW;
3276 }
3277
3278 /// ADC2 clock enable during Sleep mode
3279 pub mod ADC2LPEN {
3280 /// Offset (9 bits)
3281 pub const offset: u32 = 9;
3282 /// Mask (1 bit: 1 << 9)
3283 pub const mask: u32 = 1 << offset;
3284 /// Read-only values (empty)
3285 pub mod R {}
3286 /// Write-only values (empty)
3287 pub mod W {}
3288 pub use super::TIM1LPEN::RW;
3289 }
3290
3291 /// ADC 3 clock enable during Sleep mode
3292 pub mod ADC3LPEN {
3293 /// Offset (10 bits)
3294 pub const offset: u32 = 10;
3295 /// Mask (1 bit: 1 << 10)
3296 pub const mask: u32 = 1 << offset;
3297 /// Read-only values (empty)
3298 pub mod R {}
3299 /// Write-only values (empty)
3300 pub mod W {}
3301 pub use super::TIM1LPEN::RW;
3302 }
3303
3304 /// SDIO clock enable during Sleep mode
3305 pub mod SDIOLPEN {
3306 /// Offset (11 bits)
3307 pub const offset: u32 = 11;
3308 /// Mask (1 bit: 1 << 11)
3309 pub const mask: u32 = 1 << offset;
3310 /// Read-only values (empty)
3311 pub mod R {}
3312 /// Write-only values (empty)
3313 pub mod W {}
3314 pub use super::TIM1LPEN::RW;
3315 }
3316
3317 /// SPI 1 clock enable during Sleep mode
3318 pub mod SPI1LPEN {
3319 /// Offset (12 bits)
3320 pub const offset: u32 = 12;
3321 /// Mask (1 bit: 1 << 12)
3322 pub const mask: u32 = 1 << offset;
3323 /// Read-only values (empty)
3324 pub mod R {}
3325 /// Write-only values (empty)
3326 pub mod W {}
3327 pub use super::TIM1LPEN::RW;
3328 }
3329
3330 /// SPI 4 clock enable during Sleep mode
3331 pub mod SPI4LPEN {
3332 /// Offset (13 bits)
3333 pub const offset: u32 = 13;
3334 /// Mask (1 bit: 1 << 13)
3335 pub const mask: u32 = 1 << offset;
3336 /// Read-only values (empty)
3337 pub mod R {}
3338 /// Write-only values (empty)
3339 pub mod W {}
3340 pub use super::TIM1LPEN::RW;
3341 }
3342
3343 /// System configuration controller clock enable during Sleep mode
3344 pub mod SYSCFGLPEN {
3345 /// Offset (14 bits)
3346 pub const offset: u32 = 14;
3347 /// Mask (1 bit: 1 << 14)
3348 pub const mask: u32 = 1 << offset;
3349 /// Read-only values (empty)
3350 pub mod R {}
3351 /// Write-only values (empty)
3352 pub mod W {}
3353 pub use super::TIM1LPEN::RW;
3354 }
3355
3356 /// TIM9 clock enable during sleep mode
3357 pub mod TIM9LPEN {
3358 /// Offset (16 bits)
3359 pub const offset: u32 = 16;
3360 /// Mask (1 bit: 1 << 16)
3361 pub const mask: u32 = 1 << offset;
3362 /// Read-only values (empty)
3363 pub mod R {}
3364 /// Write-only values (empty)
3365 pub mod W {}
3366 pub use super::TIM1LPEN::RW;
3367 }
3368
3369 /// TIM10 clock enable during Sleep mode
3370 pub mod TIM10LPEN {
3371 /// Offset (17 bits)
3372 pub const offset: u32 = 17;
3373 /// Mask (1 bit: 1 << 17)
3374 pub const mask: u32 = 1 << offset;
3375 /// Read-only values (empty)
3376 pub mod R {}
3377 /// Write-only values (empty)
3378 pub mod W {}
3379 pub use super::TIM1LPEN::RW;
3380 }
3381
3382 /// TIM11 clock enable during Sleep mode
3383 pub mod TIM11LPEN {
3384 /// Offset (18 bits)
3385 pub const offset: u32 = 18;
3386 /// Mask (1 bit: 1 << 18)
3387 pub const mask: u32 = 1 << offset;
3388 /// Read-only values (empty)
3389 pub mod R {}
3390 /// Write-only values (empty)
3391 pub mod W {}
3392 pub use super::TIM1LPEN::RW;
3393 }
3394
3395 /// SAI1 clock enable
3396 pub mod SAI1LPEN {
3397 /// Offset (22 bits)
3398 pub const offset: u32 = 22;
3399 /// Mask (1 bit: 1 << 22)
3400 pub const mask: u32 = 1 << offset;
3401 /// Read-only values (empty)
3402 pub mod R {}
3403 /// Write-only values (empty)
3404 pub mod W {}
3405 pub use super::TIM1LPEN::RW;
3406 }
3407
3408 /// SAI2 clock enable
3409 pub mod SAI2LPEN {
3410 /// Offset (23 bits)
3411 pub const offset: u32 = 23;
3412 /// Mask (1 bit: 1 << 23)
3413 pub const mask: u32 = 1 << offset;
3414 /// Read-only values (empty)
3415 pub mod R {}
3416 /// Write-only values (empty)
3417 pub mod W {}
3418 pub use super::TIM1LPEN::RW;
3419 }
3420}
3421
3422/// Backup domain control register
3423pub mod BDCR {
3424
3425 /// Backup domain software reset
3426 pub mod BDRST {
3427 /// Offset (16 bits)
3428 pub const offset: u32 = 16;
3429 /// Mask (1 bit: 1 << 16)
3430 pub const mask: u32 = 1 << offset;
3431 /// Read-only values (empty)
3432 pub mod R {}
3433 /// Write-only values (empty)
3434 pub mod W {}
3435 /// Read-write values
3436 pub mod RW {
3437
3438 /// 0b0: Reset not activated
3439 pub const Disabled: u32 = 0b0;
3440
3441 /// 0b1: Reset the entire RTC domain
3442 pub const Enabled: u32 = 0b1;
3443 }
3444 }
3445
3446 /// RTC clock enable
3447 pub mod RTCEN {
3448 /// Offset (15 bits)
3449 pub const offset: u32 = 15;
3450 /// Mask (1 bit: 1 << 15)
3451 pub const mask: u32 = 1 << offset;
3452 /// Read-only values (empty)
3453 pub mod R {}
3454 /// Write-only values (empty)
3455 pub mod W {}
3456 /// Read-write values
3457 pub mod RW {
3458
3459 /// 0b0: RTC clock disabled
3460 pub const Disabled: u32 = 0b0;
3461
3462 /// 0b1: RTC clock enabled
3463 pub const Enabled: u32 = 0b1;
3464 }
3465 }
3466
3467 /// RTC clock source selection
3468 pub mod RTCSEL {
3469 /// Offset (8 bits)
3470 pub const offset: u32 = 8;
3471 /// Mask (2 bits: 0b11 << 8)
3472 pub const mask: u32 = 0b11 << offset;
3473 /// Read-only values (empty)
3474 pub mod R {}
3475 /// Write-only values (empty)
3476 pub mod W {}
3477 /// Read-write values
3478 pub mod RW {
3479
3480 /// 0b00: No clock
3481 pub const NoClock: u32 = 0b00;
3482
3483 /// 0b01: LSE oscillator clock used as RTC clock
3484 pub const LSE: u32 = 0b01;
3485
3486 /// 0b10: LSI oscillator clock used as RTC clock
3487 pub const LSI: u32 = 0b10;
3488
3489 /// 0b11: HSE oscillator clock divided by a prescaler used as RTC clock
3490 pub const HSE: u32 = 0b11;
3491 }
3492 }
3493
3494 /// External low-speed oscillator mode
3495 pub mod LSEMOD {
3496 /// Offset (3 bits)
3497 pub const offset: u32 = 3;
3498 /// Mask (1 bit: 1 << 3)
3499 pub const mask: u32 = 1 << offset;
3500 /// Read-only values (empty)
3501 pub mod R {}
3502 /// Write-only values (empty)
3503 pub mod W {}
3504 /// Read-write values
3505 pub mod RW {
3506
3507 /// 0b0: LSE oscillator low power mode selection
3508 pub const Low: u32 = 0b0;
3509
3510 /// 0b1: LSE oscillator high drive mode selection
3511 pub const High: u32 = 0b1;
3512 }
3513 }
3514
3515 /// External low-speed oscillator bypass
3516 pub mod LSEBYP {
3517 /// Offset (2 bits)
3518 pub const offset: u32 = 2;
3519 /// Mask (1 bit: 1 << 2)
3520 pub const mask: u32 = 1 << offset;
3521 /// Read-only values (empty)
3522 pub mod R {}
3523 /// Write-only values (empty)
3524 pub mod W {}
3525 /// Read-write values
3526 pub mod RW {
3527
3528 /// 0b0: LSE crystal oscillator not bypassed
3529 pub const NotBypassed: u32 = 0b0;
3530
3531 /// 0b1: LSE crystal oscillator bypassed with external clock
3532 pub const Bypassed: u32 = 0b1;
3533 }
3534 }
3535
3536 /// External low-speed oscillator ready
3537 pub mod LSERDY {
3538 /// Offset (1 bits)
3539 pub const offset: u32 = 1;
3540 /// Mask (1 bit: 1 << 1)
3541 pub const mask: u32 = 1 << offset;
3542 /// Read-only values
3543 pub mod R {
3544
3545 /// 0b0: LSE oscillator not ready
3546 pub const NotReady: u32 = 0b0;
3547
3548 /// 0b1: LSE oscillator ready
3549 pub const Ready: u32 = 0b1;
3550 }
3551 /// Write-only values (empty)
3552 pub mod W {}
3553 /// Read-write values (empty)
3554 pub mod RW {}
3555 }
3556
3557 /// External low-speed oscillator enable
3558 pub mod LSEON {
3559 /// Offset (0 bits)
3560 pub const offset: u32 = 0;
3561 /// Mask (1 bit: 1 << 0)
3562 pub const mask: u32 = 1 << offset;
3563 /// Read-only values (empty)
3564 pub mod R {}
3565 /// Write-only values (empty)
3566 pub mod W {}
3567 /// Read-write values
3568 pub mod RW {
3569
3570 /// 0b0: LSE oscillator Off
3571 pub const Off: u32 = 0b0;
3572
3573 /// 0b1: LSE oscillator On
3574 pub const On: u32 = 0b1;
3575 }
3576 }
3577}
3578
3579/// clock control & status register
3580pub mod CSR {
3581
3582 /// Low-power reset flag
3583 pub mod LPWRRSTF {
3584 /// Offset (31 bits)
3585 pub const offset: u32 = 31;
3586 /// Mask (1 bit: 1 << 31)
3587 pub const mask: u32 = 1 << offset;
3588 /// Read-only values
3589 pub mod R {
3590
3591 /// 0b0: No reset has occured
3592 pub const NoReset: u32 = 0b0;
3593
3594 /// 0b1: A reset has occured
3595 pub const Reset: u32 = 0b1;
3596 }
3597 /// Write-only values (empty)
3598 pub mod W {}
3599 /// Read-write values (empty)
3600 pub mod RW {}
3601 }
3602
3603 /// Window watchdog reset flag
3604 pub mod WWDGRSTF {
3605 /// Offset (30 bits)
3606 pub const offset: u32 = 30;
3607 /// Mask (1 bit: 1 << 30)
3608 pub const mask: u32 = 1 << offset;
3609 pub use super::LPWRRSTF::R;
3610 /// Write-only values (empty)
3611 pub mod W {}
3612 /// Read-write values (empty)
3613 pub mod RW {}
3614 }
3615
3616 /// Independent watchdog reset flag
3617 pub mod WDGRSTF {
3618 /// Offset (29 bits)
3619 pub const offset: u32 = 29;
3620 /// Mask (1 bit: 1 << 29)
3621 pub const mask: u32 = 1 << offset;
3622 pub use super::LPWRRSTF::R;
3623 /// Write-only values (empty)
3624 pub mod W {}
3625 /// Read-write values (empty)
3626 pub mod RW {}
3627 }
3628
3629 /// Software reset flag
3630 pub mod SFTRSTF {
3631 /// Offset (28 bits)
3632 pub const offset: u32 = 28;
3633 /// Mask (1 bit: 1 << 28)
3634 pub const mask: u32 = 1 << offset;
3635 pub use super::LPWRRSTF::R;
3636 /// Write-only values (empty)
3637 pub mod W {}
3638 /// Read-write values (empty)
3639 pub mod RW {}
3640 }
3641
3642 /// POR/PDR reset flag
3643 pub mod PORRSTF {
3644 /// Offset (27 bits)
3645 pub const offset: u32 = 27;
3646 /// Mask (1 bit: 1 << 27)
3647 pub const mask: u32 = 1 << offset;
3648 pub use super::LPWRRSTF::R;
3649 /// Write-only values (empty)
3650 pub mod W {}
3651 /// Read-write values (empty)
3652 pub mod RW {}
3653 }
3654
3655 /// PIN reset flag
3656 pub mod PADRSTF {
3657 /// Offset (26 bits)
3658 pub const offset: u32 = 26;
3659 /// Mask (1 bit: 1 << 26)
3660 pub const mask: u32 = 1 << offset;
3661 pub use super::LPWRRSTF::R;
3662 /// Write-only values (empty)
3663 pub mod W {}
3664 /// Read-write values (empty)
3665 pub mod RW {}
3666 }
3667
3668 /// BOR reset flag
3669 pub mod BORRSTF {
3670 /// Offset (25 bits)
3671 pub const offset: u32 = 25;
3672 /// Mask (1 bit: 1 << 25)
3673 pub const mask: u32 = 1 << offset;
3674 pub use super::LPWRRSTF::R;
3675 /// Write-only values (empty)
3676 pub mod W {}
3677 /// Read-write values (empty)
3678 pub mod RW {}
3679 }
3680
3681 /// Remove reset flag
3682 pub mod RMVF {
3683 /// Offset (24 bits)
3684 pub const offset: u32 = 24;
3685 /// Mask (1 bit: 1 << 24)
3686 pub const mask: u32 = 1 << offset;
3687 /// Read-only values (empty)
3688 pub mod R {}
3689 /// Write-only values
3690 pub mod W {
3691
3692 /// 0b1: Clears the reset flag
3693 pub const Clear: u32 = 0b1;
3694 }
3695 /// Read-write values (empty)
3696 pub mod RW {}
3697 }
3698
3699 /// Internal low-speed oscillator ready
3700 pub mod LSIRDY {
3701 /// Offset (1 bits)
3702 pub const offset: u32 = 1;
3703 /// Mask (1 bit: 1 << 1)
3704 pub const mask: u32 = 1 << offset;
3705 /// Read-only values
3706 pub mod R {
3707
3708 /// 0b0: LSI oscillator not ready
3709 pub const NotReady: u32 = 0b0;
3710
3711 /// 0b1: LSI oscillator ready
3712 pub const Ready: u32 = 0b1;
3713 }
3714 /// Write-only values (empty)
3715 pub mod W {}
3716 /// Read-write values (empty)
3717 pub mod RW {}
3718 }
3719
3720 /// Internal low-speed oscillator enable
3721 pub mod LSION {
3722 /// Offset (0 bits)
3723 pub const offset: u32 = 0;
3724 /// Mask (1 bit: 1 << 0)
3725 pub const mask: u32 = 1 << offset;
3726 /// Read-only values (empty)
3727 pub mod R {}
3728 /// Write-only values (empty)
3729 pub mod W {}
3730 /// Read-write values
3731 pub mod RW {
3732
3733 /// 0b0: LSI oscillator Off
3734 pub const Off: u32 = 0b0;
3735
3736 /// 0b1: LSI oscillator On
3737 pub const On: u32 = 0b1;
3738 }
3739 }
3740}
3741
3742/// spread spectrum clock generation register
3743pub mod SSCGR {
3744
3745 /// Spread spectrum modulation enable
3746 pub mod SSCGEN {
3747 /// Offset (31 bits)
3748 pub const offset: u32 = 31;
3749 /// Mask (1 bit: 1 << 31)
3750 pub const mask: u32 = 1 << offset;
3751 /// Read-only values (empty)
3752 pub mod R {}
3753 /// Write-only values (empty)
3754 pub mod W {}
3755 /// Read-write values
3756 pub mod RW {
3757
3758 /// 0b0: Spread spectrum modulation disabled
3759 pub const Disabled: u32 = 0b0;
3760
3761 /// 0b1: Spread spectrum modulation enabled
3762 pub const Enabled: u32 = 0b1;
3763 }
3764 }
3765
3766 /// Spread Select
3767 pub mod SPREADSEL {
3768 /// Offset (30 bits)
3769 pub const offset: u32 = 30;
3770 /// Mask (1 bit: 1 << 30)
3771 pub const mask: u32 = 1 << offset;
3772 /// Read-only values (empty)
3773 pub mod R {}
3774 /// Write-only values (empty)
3775 pub mod W {}
3776 /// Read-write values
3777 pub mod RW {
3778
3779 /// 0b0: Center spread
3780 pub const Center: u32 = 0b0;
3781
3782 /// 0b1: Down spread
3783 pub const Down: u32 = 0b1;
3784 }
3785 }
3786
3787 /// Incrementation step
3788 pub mod INCSTEP {
3789 /// Offset (13 bits)
3790 pub const offset: u32 = 13;
3791 /// Mask (15 bits: 0x7fff << 13)
3792 pub const mask: u32 = 0x7fff << offset;
3793 /// Read-only values (empty)
3794 pub mod R {}
3795 /// Write-only values (empty)
3796 pub mod W {}
3797 /// Read-write values (empty)
3798 pub mod RW {}
3799 }
3800
3801 /// Modulation period
3802 pub mod MODPER {
3803 /// Offset (0 bits)
3804 pub const offset: u32 = 0;
3805 /// Mask (13 bits: 0x1fff << 0)
3806 pub const mask: u32 = 0x1fff << offset;
3807 /// Read-only values (empty)
3808 pub mod R {}
3809 /// Write-only values (empty)
3810 pub mod W {}
3811 /// Read-write values (empty)
3812 pub mod RW {}
3813 }
3814}
3815
3816/// PLLI2S configuration register
3817pub mod PLLI2SCFGR {
3818
3819 /// Division factor for audio PLL (PLLI2S) input clock
3820 pub mod PLLI2SM {
3821 /// Offset (0 bits)
3822 pub const offset: u32 = 0;
3823 /// Mask (6 bits: 0x3f << 0)
3824 pub const mask: u32 = 0x3f << offset;
3825 /// Read-only values (empty)
3826 pub mod R {}
3827 /// Write-only values (empty)
3828 pub mod W {}
3829 /// Read-write values (empty)
3830 pub mod RW {}
3831 }
3832
3833 /// PLLI2S multiplication factor for VCO
3834 pub mod PLLI2SN {
3835 /// Offset (6 bits)
3836 pub const offset: u32 = 6;
3837 /// Mask (9 bits: 0x1ff << 6)
3838 pub const mask: u32 = 0x1ff << offset;
3839 /// Read-only values (empty)
3840 pub mod R {}
3841 /// Write-only values (empty)
3842 pub mod W {}
3843 /// Read-write values (empty)
3844 pub mod RW {}
3845 }
3846
3847 /// PLLI2S division factor for SPDIF-IN clock
3848 pub mod PLLI2SP {
3849 /// Offset (16 bits)
3850 pub const offset: u32 = 16;
3851 /// Mask (2 bits: 0b11 << 16)
3852 pub const mask: u32 = 0b11 << offset;
3853 /// Read-only values (empty)
3854 pub mod R {}
3855 /// Write-only values (empty)
3856 pub mod W {}
3857 /// Read-write values
3858 pub mod RW {
3859
3860 /// 0b00: PLL*P=2
3861 pub const Div2: u32 = 0b00;
3862
3863 /// 0b01: PLL*P=4
3864 pub const Div4: u32 = 0b01;
3865
3866 /// 0b10: PLL*P=6
3867 pub const Div6: u32 = 0b10;
3868
3869 /// 0b11: PLL*P=8
3870 pub const Div8: u32 = 0b11;
3871 }
3872 }
3873
3874 /// PLLI2S division factor for SAI1 clock
3875 pub mod PLLI2SQ {
3876 /// Offset (24 bits)
3877 pub const offset: u32 = 24;
3878 /// Mask (4 bits: 0b1111 << 24)
3879 pub const mask: u32 = 0b1111 << offset;
3880 /// Read-only values (empty)
3881 pub mod R {}
3882 /// Write-only values (empty)
3883 pub mod W {}
3884 /// Read-write values (empty)
3885 pub mod RW {}
3886 }
3887
3888 /// PLLI2S division factor for I2S clocks
3889 pub mod PLLI2SR {
3890 /// Offset (28 bits)
3891 pub const offset: u32 = 28;
3892 /// Mask (3 bits: 0b111 << 28)
3893 pub const mask: u32 = 0b111 << offset;
3894 /// Read-only values (empty)
3895 pub mod R {}
3896 /// Write-only values (empty)
3897 pub mod W {}
3898 /// Read-write values (empty)
3899 pub mod RW {}
3900 }
3901}
3902
3903/// PLL configuration register
3904pub mod PLLSAICFGR {
3905
3906 /// Division factor for audio PLLSAI input clock
3907 pub mod PLLSAIM {
3908 /// Offset (0 bits)
3909 pub const offset: u32 = 0;
3910 /// Mask (6 bits: 0x3f << 0)
3911 pub const mask: u32 = 0x3f << offset;
3912 /// Read-only values (empty)
3913 pub mod R {}
3914 /// Write-only values (empty)
3915 pub mod W {}
3916 /// Read-write values (empty)
3917 pub mod RW {}
3918 }
3919
3920 /// PLLSAI division factor for VCO
3921 pub mod PLLSAIN {
3922 /// Offset (6 bits)
3923 pub const offset: u32 = 6;
3924 /// Mask (9 bits: 0x1ff << 6)
3925 pub const mask: u32 = 0x1ff << offset;
3926 /// Read-only values (empty)
3927 pub mod R {}
3928 /// Write-only values (empty)
3929 pub mod W {}
3930 /// Read-write values (empty)
3931 pub mod RW {}
3932 }
3933
3934 /// PLLSAI division factor for 48 MHz clock
3935 pub mod PLLSAIP {
3936 /// Offset (16 bits)
3937 pub const offset: u32 = 16;
3938 /// Mask (2 bits: 0b11 << 16)
3939 pub const mask: u32 = 0b11 << offset;
3940 /// Read-only values (empty)
3941 pub mod R {}
3942 /// Write-only values (empty)
3943 pub mod W {}
3944 /// Read-write values
3945 pub mod RW {
3946
3947 /// 0b00: PLL*P=2
3948 pub const Div2: u32 = 0b00;
3949
3950 /// 0b01: PLL*P=4
3951 pub const Div4: u32 = 0b01;
3952
3953 /// 0b10: PLL*P=6
3954 pub const Div6: u32 = 0b10;
3955
3956 /// 0b11: PLL*P=8
3957 pub const Div8: u32 = 0b11;
3958 }
3959 }
3960
3961 /// PLLSAI division factor for SAIs clock
3962 pub mod PLLSAIQ {
3963 /// Offset (24 bits)
3964 pub const offset: u32 = 24;
3965 /// Mask (4 bits: 0b1111 << 24)
3966 pub const mask: u32 = 0b1111 << offset;
3967 /// Read-only values (empty)
3968 pub mod R {}
3969 /// Write-only values (empty)
3970 pub mod W {}
3971 /// Read-write values (empty)
3972 pub mod RW {}
3973 }
3974}
3975
3976/// Dedicated Clock Configuration Register
3977pub mod DCKCFGR {
3978
3979 /// PLLI2S division factor for SAIs clock
3980 pub mod PLLI2SDIVQ {
3981 /// Offset (0 bits)
3982 pub const offset: u32 = 0;
3983 /// Mask (5 bits: 0b11111 << 0)
3984 pub const mask: u32 = 0b11111 << offset;
3985 /// Read-only values (empty)
3986 pub mod R {}
3987 /// Write-only values (empty)
3988 pub mod W {}
3989 /// Read-write values
3990 pub mod RW {
3991
3992 /// 0b00000: PLLI2SDIVQ = /1
3993 pub const Div1: u32 = 0b00000;
3994
3995 /// 0b00001: PLLI2SDIVQ = /2
3996 pub const Div2: u32 = 0b00001;
3997
3998 /// 0b00010: PLLI2SDIVQ = /3
3999 pub const Div3: u32 = 0b00010;
4000
4001 /// 0b00011: PLLI2SDIVQ = /4
4002 pub const Div4: u32 = 0b00011;
4003
4004 /// 0b00100: PLLI2SDIVQ = /5
4005 pub const Div5: u32 = 0b00100;
4006
4007 /// 0b00101: PLLI2SDIVQ = /6
4008 pub const Div6: u32 = 0b00101;
4009
4010 /// 0b00110: PLLI2SDIVQ = /7
4011 pub const Div7: u32 = 0b00110;
4012
4013 /// 0b00111: PLLI2SDIVQ = /8
4014 pub const Div8: u32 = 0b00111;
4015
4016 /// 0b01000: PLLI2SDIVQ = /9
4017 pub const Div9: u32 = 0b01000;
4018
4019 /// 0b01001: PLLI2SDIVQ = /10
4020 pub const Div10: u32 = 0b01001;
4021
4022 /// 0b01010: PLLI2SDIVQ = /11
4023 pub const Div11: u32 = 0b01010;
4024
4025 /// 0b01011: PLLI2SDIVQ = /12
4026 pub const Div12: u32 = 0b01011;
4027
4028 /// 0b01100: PLLI2SDIVQ = /13
4029 pub const Div13: u32 = 0b01100;
4030
4031 /// 0b01101: PLLI2SDIVQ = /14
4032 pub const Div14: u32 = 0b01101;
4033
4034 /// 0b01110: PLLI2SDIVQ = /15
4035 pub const Div15: u32 = 0b01110;
4036
4037 /// 0b01111: PLLI2SDIVQ = /16
4038 pub const Div16: u32 = 0b01111;
4039
4040 /// 0b10000: PLLI2SDIVQ = /17
4041 pub const Div17: u32 = 0b10000;
4042
4043 /// 0b10001: PLLI2SDIVQ = /18
4044 pub const Div18: u32 = 0b10001;
4045
4046 /// 0b10010: PLLI2SDIVQ = /19
4047 pub const Div19: u32 = 0b10010;
4048
4049 /// 0b10011: PLLI2SDIVQ = /20
4050 pub const Div20: u32 = 0b10011;
4051
4052 /// 0b10100: PLLI2SDIVQ = /21
4053 pub const Div21: u32 = 0b10100;
4054
4055 /// 0b10101: PLLI2SDIVQ = /22
4056 pub const Div22: u32 = 0b10101;
4057
4058 /// 0b10110: PLLI2SDIVQ = /23
4059 pub const Div23: u32 = 0b10110;
4060
4061 /// 0b10111: PLLI2SDIVQ = /24
4062 pub const Div24: u32 = 0b10111;
4063
4064 /// 0b11000: PLLI2SDIVQ = /25
4065 pub const Div25: u32 = 0b11000;
4066
4067 /// 0b11001: PLLI2SDIVQ = /26
4068 pub const Div26: u32 = 0b11001;
4069
4070 /// 0b11010: PLLI2SDIVQ = /27
4071 pub const Div27: u32 = 0b11010;
4072
4073 /// 0b11011: PLLI2SDIVQ = /28
4074 pub const Div28: u32 = 0b11011;
4075
4076 /// 0b11100: PLLI2SDIVQ = /29
4077 pub const Div29: u32 = 0b11100;
4078
4079 /// 0b11101: PLLI2SDIVQ = /30
4080 pub const Div30: u32 = 0b11101;
4081
4082 /// 0b11110: PLLI2SDIVQ = /31
4083 pub const Div31: u32 = 0b11110;
4084
4085 /// 0b11111: PLLI2SDIVQ = /32
4086 pub const Div32: u32 = 0b11111;
4087 }
4088 }
4089
4090 /// PLLSAI division factor for SAIs clock
4091 pub mod PLLSAIDIVQ {
4092 /// Offset (8 bits)
4093 pub const offset: u32 = 8;
4094 /// Mask (5 bits: 0b11111 << 8)
4095 pub const mask: u32 = 0b11111 << offset;
4096 /// Read-only values (empty)
4097 pub mod R {}
4098 /// Write-only values (empty)
4099 pub mod W {}
4100 /// Read-write values
4101 pub mod RW {
4102
4103 /// 0b00000: PLLSAIDIVQ = /1
4104 pub const Div1: u32 = 0b00000;
4105
4106 /// 0b00001: PLLSAIDIVQ = /2
4107 pub const Div2: u32 = 0b00001;
4108
4109 /// 0b00010: PLLSAIDIVQ = /3
4110 pub const Div3: u32 = 0b00010;
4111
4112 /// 0b00011: PLLSAIDIVQ = /4
4113 pub const Div4: u32 = 0b00011;
4114
4115 /// 0b00100: PLLSAIDIVQ = /5
4116 pub const Div5: u32 = 0b00100;
4117
4118 /// 0b00101: PLLSAIDIVQ = /6
4119 pub const Div6: u32 = 0b00101;
4120
4121 /// 0b00110: PLLSAIDIVQ = /7
4122 pub const Div7: u32 = 0b00110;
4123
4124 /// 0b00111: PLLSAIDIVQ = /8
4125 pub const Div8: u32 = 0b00111;
4126
4127 /// 0b01000: PLLSAIDIVQ = /9
4128 pub const Div9: u32 = 0b01000;
4129
4130 /// 0b01001: PLLSAIDIVQ = /10
4131 pub const Div10: u32 = 0b01001;
4132
4133 /// 0b01010: PLLSAIDIVQ = /11
4134 pub const Div11: u32 = 0b01010;
4135
4136 /// 0b01011: PLLSAIDIVQ = /12
4137 pub const Div12: u32 = 0b01011;
4138
4139 /// 0b01100: PLLSAIDIVQ = /13
4140 pub const Div13: u32 = 0b01100;
4141
4142 /// 0b01101: PLLSAIDIVQ = /14
4143 pub const Div14: u32 = 0b01101;
4144
4145 /// 0b01110: PLLSAIDIVQ = /15
4146 pub const Div15: u32 = 0b01110;
4147
4148 /// 0b01111: PLLSAIDIVQ = /16
4149 pub const Div16: u32 = 0b01111;
4150
4151 /// 0b10000: PLLSAIDIVQ = /17
4152 pub const Div17: u32 = 0b10000;
4153
4154 /// 0b10001: PLLSAIDIVQ = /18
4155 pub const Div18: u32 = 0b10001;
4156
4157 /// 0b10010: PLLSAIDIVQ = /19
4158 pub const Div19: u32 = 0b10010;
4159
4160 /// 0b10011: PLLSAIDIVQ = /20
4161 pub const Div20: u32 = 0b10011;
4162
4163 /// 0b10100: PLLSAIDIVQ = /21
4164 pub const Div21: u32 = 0b10100;
4165
4166 /// 0b10101: PLLSAIDIVQ = /22
4167 pub const Div22: u32 = 0b10101;
4168
4169 /// 0b10110: PLLSAIDIVQ = /23
4170 pub const Div23: u32 = 0b10110;
4171
4172 /// 0b10111: PLLSAIDIVQ = /24
4173 pub const Div24: u32 = 0b10111;
4174
4175 /// 0b11000: PLLSAIDIVQ = /25
4176 pub const Div25: u32 = 0b11000;
4177
4178 /// 0b11001: PLLSAIDIVQ = /26
4179 pub const Div26: u32 = 0b11001;
4180
4181 /// 0b11010: PLLSAIDIVQ = /27
4182 pub const Div27: u32 = 0b11010;
4183
4184 /// 0b11011: PLLSAIDIVQ = /28
4185 pub const Div28: u32 = 0b11011;
4186
4187 /// 0b11100: PLLSAIDIVQ = /29
4188 pub const Div29: u32 = 0b11100;
4189
4190 /// 0b11101: PLLSAIDIVQ = /30
4191 pub const Div30: u32 = 0b11101;
4192
4193 /// 0b11110: PLLSAIDIVQ = /31
4194 pub const Div31: u32 = 0b11110;
4195
4196 /// 0b11111: PLLSAIDIVQ = /32
4197 pub const Div32: u32 = 0b11111;
4198 }
4199 }
4200
4201 /// SAI1 clock source selection
4202 pub mod SAI1SRC {
4203 /// Offset (20 bits)
4204 pub const offset: u32 = 20;
4205 /// Mask (2 bits: 0b11 << 20)
4206 pub const mask: u32 = 0b11 << offset;
4207 /// Read-only values (empty)
4208 pub mod R {}
4209 /// Write-only values (empty)
4210 pub mod W {}
4211 /// Read-write values
4212 pub mod RW {
4213
4214 /// 0b00: SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ
4215 pub const PLLSAI: u32 = 0b00;
4216
4217 /// 0b01: SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ
4218 pub const PLLI2S: u32 = 0b01;
4219
4220 /// 0b10: SAI1 clock frequency = f(PLL_R)
4221 pub const PLLR: u32 = 0b10;
4222
4223 /// 0b11: I2S_CKIN Alternate function input frequency
4224 pub const I2S_CKIN: u32 = 0b11;
4225 }
4226 }
4227
4228 /// SAI2 clock source selection
4229 pub mod SAI2SRC {
4230 /// Offset (22 bits)
4231 pub const offset: u32 = 22;
4232 /// Mask (2 bits: 0b11 << 22)
4233 pub const mask: u32 = 0b11 << offset;
4234 /// Read-only values (empty)
4235 pub mod R {}
4236 /// Write-only values (empty)
4237 pub mod W {}
4238 /// Read-write values
4239 pub mod RW {
4240
4241 /// 0b00: SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ
4242 pub const PLLSAI: u32 = 0b00;
4243
4244 /// 0b01: SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ
4245 pub const PLLI2S: u32 = 0b01;
4246
4247 /// 0b10: SAI2 clock frequency = f(PLL_R)
4248 pub const PLLR: u32 = 0b10;
4249
4250 /// 0b11: SAI2 clock frequency = Alternate function input frequency
4251 pub const HSI_HSE: u32 = 0b11;
4252 }
4253 }
4254
4255 /// Timers clocks prescalers selection
4256 pub mod TIMPRE {
4257 /// Offset (24 bits)
4258 pub const offset: u32 = 24;
4259 /// Mask (1 bit: 1 << 24)
4260 pub const mask: u32 = 1 << offset;
4261 /// Read-only values (empty)
4262 pub mod R {}
4263 /// Write-only values (empty)
4264 pub mod W {}
4265 /// Read-write values
4266 pub mod RW {
4267
4268 /// 0b0: If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx
4269 pub const Mul2: u32 = 0b0;
4270
4271 /// 0b1: If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx
4272 pub const Mul4: u32 = 0b1;
4273 }
4274 }
4275
4276 /// I2S APB1 clock source selection
4277 pub mod I2S1SRC {
4278 /// Offset (25 bits)
4279 pub const offset: u32 = 25;
4280 /// Mask (2 bits: 0b11 << 25)
4281 pub const mask: u32 = 0b11 << offset;
4282 /// Read-only values (empty)
4283 pub mod R {}
4284 /// Write-only values (empty)
4285 pub mod W {}
4286 /// Read-write values
4287 pub mod RW {
4288
4289 /// 0b00: I2Sx clock frequency = f(PLLI2S_R)
4290 pub const PLLI2SR: u32 = 0b00;
4291
4292 /// 0b01: I2Sx clock frequency = I2S_CKIN Alternate function input frequency
4293 pub const I2S_CKIN: u32 = 0b01;
4294
4295 /// 0b10: I2Sx clock frequency = f(PLL_R)
4296 pub const PLLR: u32 = 0b10;
4297
4298 /// 0b11: I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR\[22\])
4299 pub const HSI_HSE: u32 = 0b11;
4300 }
4301 }
4302
4303 /// I2S APB2 clock source selection
4304 pub mod I2S2SRC {
4305 /// Offset (27 bits)
4306 pub const offset: u32 = 27;
4307 /// Mask (2 bits: 0b11 << 27)
4308 pub const mask: u32 = 0b11 << offset;
4309 /// Read-only values (empty)
4310 pub mod R {}
4311 /// Write-only values (empty)
4312 pub mod W {}
4313 pub use super::I2S1SRC::RW;
4314 }
4315}
4316
4317/// clocks gated enable register
4318pub mod CKGATENR {
4319
4320 /// AHB to APB1 Bridge clock enable
4321 pub mod AHB2APB1_CKEN {
4322 /// Offset (0 bits)
4323 pub const offset: u32 = 0;
4324 /// Mask (1 bit: 1 << 0)
4325 pub const mask: u32 = 1 << offset;
4326 /// Read-only values (empty)
4327 pub mod R {}
4328 /// Write-only values (empty)
4329 pub mod W {}
4330 /// Read-write values
4331 pub mod RW {
4332
4333 /// 0b0: The clock gating is enabled
4334 pub const Enabled: u32 = 0b0;
4335
4336 /// 0b1: The clock gating is disabled, the clock is always enabled
4337 pub const Disabled: u32 = 0b1;
4338 }
4339 }
4340
4341 /// AHB to APB2 Bridge clock enable
4342 pub mod AHB2APB2_CKEN {
4343 /// Offset (1 bits)
4344 pub const offset: u32 = 1;
4345 /// Mask (1 bit: 1 << 1)
4346 pub const mask: u32 = 1 << offset;
4347 /// Read-only values (empty)
4348 pub mod R {}
4349 /// Write-only values (empty)
4350 pub mod W {}
4351 pub use super::AHB2APB1_CKEN::RW;
4352 }
4353
4354 /// Cortex M4 ETM clock enable
4355 pub mod CM4DBG_CKEN {
4356 /// Offset (2 bits)
4357 pub const offset: u32 = 2;
4358 /// Mask (1 bit: 1 << 2)
4359 pub const mask: u32 = 1 << offset;
4360 /// Read-only values (empty)
4361 pub mod R {}
4362 /// Write-only values (empty)
4363 pub mod W {}
4364 pub use super::AHB2APB1_CKEN::RW;
4365 }
4366
4367 /// Spare clock enable
4368 pub mod SPARE_CKEN {
4369 /// Offset (3 bits)
4370 pub const offset: u32 = 3;
4371 /// Mask (1 bit: 1 << 3)
4372 pub const mask: u32 = 1 << offset;
4373 /// Read-only values (empty)
4374 pub mod R {}
4375 /// Write-only values (empty)
4376 pub mod W {}
4377 pub use super::AHB2APB1_CKEN::RW;
4378 }
4379
4380 /// SRQAM controller clock enable
4381 pub mod SRAM_CKEN {
4382 /// Offset (4 bits)
4383 pub const offset: u32 = 4;
4384 /// Mask (1 bit: 1 << 4)
4385 pub const mask: u32 = 1 << offset;
4386 /// Read-only values (empty)
4387 pub mod R {}
4388 /// Write-only values (empty)
4389 pub mod W {}
4390 pub use super::AHB2APB1_CKEN::RW;
4391 }
4392
4393 /// Flash Interface clock enable
4394 pub mod FLITF_CKEN {
4395 /// Offset (5 bits)
4396 pub const offset: u32 = 5;
4397 /// Mask (1 bit: 1 << 5)
4398 pub const mask: u32 = 1 << offset;
4399 /// Read-only values (empty)
4400 pub mod R {}
4401 /// Write-only values (empty)
4402 pub mod W {}
4403 pub use super::AHB2APB1_CKEN::RW;
4404 }
4405
4406 /// RCC clock enable
4407 pub mod RCC_CKEN {
4408 /// Offset (6 bits)
4409 pub const offset: u32 = 6;
4410 /// Mask (1 bit: 1 << 6)
4411 pub const mask: u32 = 1 << offset;
4412 /// Read-only values (empty)
4413 pub mod R {}
4414 /// Write-only values (empty)
4415 pub mod W {}
4416 pub use super::AHB2APB1_CKEN::RW;
4417 }
4418}
4419
4420/// dedicated clocks configuration register 2
4421pub mod DCKCFGR2 {
4422
4423 /// I2C4 kernel clock source selection
4424 pub mod FMPI2C1SEL {
4425 /// Offset (22 bits)
4426 pub const offset: u32 = 22;
4427 /// Mask (2 bits: 0b11 << 22)
4428 pub const mask: u32 = 0b11 << offset;
4429 /// Read-only values (empty)
4430 pub mod R {}
4431 /// Write-only values (empty)
4432 pub mod W {}
4433 /// Read-write values
4434 pub mod RW {
4435
4436 /// 0b00: APB clock selected as I2C clock
4437 pub const APB: u32 = 0b00;
4438
4439 /// 0b01: System clock selected as I2C clock
4440 pub const SYSCLK: u32 = 0b01;
4441
4442 /// 0b10: HSI clock selected as I2C clock
4443 pub const HSI: u32 = 0b10;
4444 }
4445 }
4446
4447 /// HDMI CEC clock source selection
4448 pub mod CECSEL {
4449 /// Offset (26 bits)
4450 pub const offset: u32 = 26;
4451 /// Mask (1 bit: 1 << 26)
4452 pub const mask: u32 = 1 << offset;
4453 /// Read-only values (empty)
4454 pub mod R {}
4455 /// Write-only values (empty)
4456 pub mod W {}
4457 /// Read-write values
4458 pub mod RW {
4459
4460 /// 0b0: LSE clock is selected as HDMI-CEC clock
4461 pub const LSE: u32 = 0b0;
4462
4463 /// 0b1: HSI divided by 488 clock is selected as HDMI-CEC clock
4464 pub const HSI_Div488: u32 = 0b1;
4465 }
4466 }
4467
4468 /// SDIO/USBFS/HS clock selection
4469 pub mod CK48MSEL {
4470 /// Offset (27 bits)
4471 pub const offset: u32 = 27;
4472 /// Mask (1 bit: 1 << 27)
4473 pub const mask: u32 = 1 << offset;
4474 /// Read-only values (empty)
4475 pub mod R {}
4476 /// Write-only values (empty)
4477 pub mod W {}
4478 /// Read-write values
4479 pub mod RW {
4480
4481 /// 0b0: 48MHz clock from PLL is selected
4482 pub const PLL: u32 = 0b0;
4483
4484 /// 0b1: 48MHz clock from PLLSAI is selected
4485 pub const PLLSAI: u32 = 0b1;
4486 }
4487 }
4488
4489 /// SDIO clock selection
4490 pub mod SDIOSEL {
4491 /// Offset (28 bits)
4492 pub const offset: u32 = 28;
4493 /// Mask (1 bit: 1 << 28)
4494 pub const mask: u32 = 1 << offset;
4495 /// Read-only values (empty)
4496 pub mod R {}
4497 /// Write-only values (empty)
4498 pub mod W {}
4499 /// Read-write values
4500 pub mod RW {
4501
4502 /// 0b0: 48 MHz clock is selected as SD clock
4503 pub const CK48M: u32 = 0b0;
4504
4505 /// 0b1: System clock is selected as SD clock
4506 pub const SYSCLK: u32 = 0b1;
4507 }
4508 }
4509
4510 /// SPDIF clock selection
4511 pub mod SPDIFRXSEL {
4512 /// Offset (29 bits)
4513 pub const offset: u32 = 29;
4514 /// Mask (1 bit: 1 << 29)
4515 pub const mask: u32 = 1 << offset;
4516 /// Read-only values (empty)
4517 pub mod R {}
4518 /// Write-only values (empty)
4519 pub mod W {}
4520 /// Read-write values
4521 pub mod RW {
4522
4523 /// 0b0: SPDIF-Rx clock from PLL is selected
4524 pub const PLL: u32 = 0b0;
4525
4526 /// 0b1: SPDIF-Rx clock from PLLI2S is selected
4527 pub const PLLI2S: u32 = 0b1;
4528 }
4529 }
4530}
4531#[repr(C)]
4532pub struct RegisterBlock {
4533 /// clock control register
4534 pub CR: RWRegister<u32>,
4535
4536 /// PLL configuration register
4537 pub PLLCFGR: RWRegister<u32>,
4538
4539 /// clock configuration register
4540 pub CFGR: RWRegister<u32>,
4541
4542 /// clock interrupt register
4543 pub CIR: RWRegister<u32>,
4544
4545 /// AHB1 peripheral reset register
4546 pub AHB1RSTR: RWRegister<u32>,
4547
4548 /// AHB2 peripheral reset register
4549 pub AHB2RSTR: RWRegister<u32>,
4550
4551 /// AHB3 peripheral reset register
4552 pub AHB3RSTR: RWRegister<u32>,
4553
4554 _reserved1: [u8; 4],
4555
4556 /// APB1 peripheral reset register
4557 pub APB1RSTR: RWRegister<u32>,
4558
4559 /// APB2 peripheral reset register
4560 pub APB2RSTR: RWRegister<u32>,
4561
4562 _reserved2: [u8; 8],
4563
4564 /// AHB1 peripheral clock register
4565 pub AHB1ENR: RWRegister<u32>,
4566
4567 /// AHB2 peripheral clock enable register
4568 pub AHB2ENR: RWRegister<u32>,
4569
4570 /// AHB3 peripheral clock enable register
4571 pub AHB3ENR: RWRegister<u32>,
4572
4573 _reserved3: [u8; 4],
4574
4575 /// APB1 peripheral clock enable register
4576 pub APB1ENR: RWRegister<u32>,
4577
4578 /// APB2 peripheral clock enable register
4579 pub APB2ENR: RWRegister<u32>,
4580
4581 _reserved4: [u8; 8],
4582
4583 /// AHB1 peripheral clock enable in low power mode register
4584 pub AHB1LPENR: RWRegister<u32>,
4585
4586 /// AHB2 peripheral clock enable in low power mode register
4587 pub AHB2LPENR: RWRegister<u32>,
4588
4589 /// AHB3 peripheral clock enable in low power mode register
4590 pub AHB3LPENR: RWRegister<u32>,
4591
4592 _reserved5: [u8; 4],
4593
4594 /// APB1 peripheral clock enable in low power mode register
4595 pub APB1LPENR: RWRegister<u32>,
4596
4597 /// APB2 peripheral clock enabled in low power mode register
4598 pub APB2LPENR: RWRegister<u32>,
4599
4600 _reserved6: [u8; 8],
4601
4602 /// Backup domain control register
4603 pub BDCR: RWRegister<u32>,
4604
4605 /// clock control & status register
4606 pub CSR: RWRegister<u32>,
4607
4608 _reserved7: [u8; 8],
4609
4610 /// spread spectrum clock generation register
4611 pub SSCGR: RWRegister<u32>,
4612
4613 /// PLLI2S configuration register
4614 pub PLLI2SCFGR: RWRegister<u32>,
4615
4616 /// PLL configuration register
4617 pub PLLSAICFGR: RWRegister<u32>,
4618
4619 /// Dedicated Clock Configuration Register
4620 pub DCKCFGR: RWRegister<u32>,
4621
4622 /// clocks gated enable register
4623 pub CKGATENR: RWRegister<u32>,
4624
4625 /// dedicated clocks configuration register 2
4626 pub DCKCFGR2: RWRegister<u32>,
4627}
4628pub struct ResetValues {
4629 pub CR: u32,
4630 pub PLLCFGR: u32,
4631 pub CFGR: u32,
4632 pub CIR: u32,
4633 pub AHB1RSTR: u32,
4634 pub AHB2RSTR: u32,
4635 pub AHB3RSTR: u32,
4636 pub APB1RSTR: u32,
4637 pub APB2RSTR: u32,
4638 pub AHB1ENR: u32,
4639 pub AHB2ENR: u32,
4640 pub AHB3ENR: u32,
4641 pub APB1ENR: u32,
4642 pub APB2ENR: u32,
4643 pub AHB1LPENR: u32,
4644 pub AHB2LPENR: u32,
4645 pub AHB3LPENR: u32,
4646 pub APB1LPENR: u32,
4647 pub APB2LPENR: u32,
4648 pub BDCR: u32,
4649 pub CSR: u32,
4650 pub SSCGR: u32,
4651 pub PLLI2SCFGR: u32,
4652 pub PLLSAICFGR: u32,
4653 pub DCKCFGR: u32,
4654 pub CKGATENR: u32,
4655 pub DCKCFGR2: u32,
4656}
4657#[cfg(not(feature = "nosync"))]
4658pub struct Instance {
4659 pub(crate) addr: u32,
4660 pub(crate) _marker: PhantomData<*const RegisterBlock>,
4661}
4662#[cfg(not(feature = "nosync"))]
4663impl ::core::ops::Deref for Instance {
4664 type Target = RegisterBlock;
4665 #[inline(always)]
4666 fn deref(&self) -> &RegisterBlock {
4667 unsafe { &*(self.addr as *const _) }
4668 }
4669}
4670#[cfg(feature = "rtic")]
4671unsafe impl Send for Instance {}
4672
4673/// Access functions for the RCC peripheral instance
4674pub mod RCC {
4675 use super::ResetValues;
4676
4677 #[cfg(not(feature = "nosync"))]
4678 use super::Instance;
4679
4680 #[cfg(not(feature = "nosync"))]
4681 const INSTANCE: Instance = Instance {
4682 addr: 0x40023800,
4683 _marker: ::core::marker::PhantomData,
4684 };
4685
4686 /// Reset values for each field in RCC
4687 pub const reset: ResetValues = ResetValues {
4688 CR: 0x00000083,
4689 PLLCFGR: 0x24003010,
4690 CFGR: 0x00000000,
4691 CIR: 0x00000000,
4692 AHB1RSTR: 0x00000000,
4693 AHB2RSTR: 0x00000000,
4694 AHB3RSTR: 0x00000000,
4695 APB1RSTR: 0x00000000,
4696 APB2RSTR: 0x00000000,
4697 AHB1ENR: 0x00100000,
4698 AHB2ENR: 0x00000000,
4699 AHB3ENR: 0x00000000,
4700 APB1ENR: 0x00000000,
4701 APB2ENR: 0x00000000,
4702 AHB1LPENR: 0x7E6791FF,
4703 AHB2LPENR: 0x000000F1,
4704 AHB3LPENR: 0x00000001,
4705 APB1LPENR: 0x36FEC9FF,
4706 APB2LPENR: 0x00075F33,
4707 BDCR: 0x00000000,
4708 CSR: 0x0E000000,
4709 SSCGR: 0x00000000,
4710 PLLI2SCFGR: 0x20003000,
4711 PLLSAICFGR: 0x24003000,
4712 DCKCFGR: 0x00000000,
4713 CKGATENR: 0x00000000,
4714 DCKCFGR2: 0x00000000,
4715 };
4716
4717 #[cfg(not(feature = "nosync"))]
4718 #[allow(renamed_and_removed_lints)]
4719 #[allow(private_no_mangle_statics)]
4720 #[no_mangle]
4721 static mut RCC_TAKEN: bool = false;
4722
4723 /// Safe access to RCC
4724 ///
4725 /// This function returns `Some(Instance)` if this instance is not
4726 /// currently taken, and `None` if it is. This ensures that if you
4727 /// do get `Some(Instance)`, you are ensured unique access to
4728 /// the peripheral and there cannot be data races (unless other
4729 /// code uses `unsafe`, of course). You can then pass the
4730 /// `Instance` around to other functions as required. When you're
4731 /// done with it, you can call `release(instance)` to return it.
4732 ///
4733 /// `Instance` itself dereferences to a `RegisterBlock`, which
4734 /// provides access to the peripheral's registers.
4735 #[cfg(not(feature = "nosync"))]
4736 #[inline]
4737 pub fn take() -> Option<Instance> {
4738 external_cortex_m::interrupt::free(|_| unsafe {
4739 if RCC_TAKEN {
4740 None
4741 } else {
4742 RCC_TAKEN = true;
4743 Some(INSTANCE)
4744 }
4745 })
4746 }
4747
4748 /// Release exclusive access to RCC
4749 ///
4750 /// This function allows you to return an `Instance` so that it
4751 /// is available to `take()` again. This function will panic if
4752 /// you return a different `Instance` or if this instance is not
4753 /// already taken.
4754 #[cfg(not(feature = "nosync"))]
4755 #[inline]
4756 pub fn release(inst: Instance) {
4757 external_cortex_m::interrupt::free(|_| unsafe {
4758 if RCC_TAKEN && inst.addr == INSTANCE.addr {
4759 RCC_TAKEN = false;
4760 } else {
4761 panic!("Released a peripheral which was not taken");
4762 }
4763 });
4764 }
4765
4766 /// Unsafely steal RCC
4767 ///
4768 /// This function is similar to take() but forcibly takes the
4769 /// Instance, marking it as taken irregardless of its previous
4770 /// state.
4771 #[cfg(not(feature = "nosync"))]
4772 #[inline]
4773 pub unsafe fn steal() -> Instance {
4774 RCC_TAKEN = true;
4775 INSTANCE
4776 }
4777}
4778
4779/// Raw pointer to RCC
4780///
4781/// Dereferencing this is unsafe because you are not ensured unique
4782/// access to the peripheral, so you may encounter data races with
4783/// other users of this peripheral. It is up to you to ensure you
4784/// will not cause data races.
4785///
4786/// This constant is provided for ease of use in unsafe code: you can
4787/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
4788pub const RCC: *const RegisterBlock = 0x40023800 as *const _;