stm32ral/stm32f4/stm32f413/fmpi2c1.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! fast-mode Inter-integrated circuit
4
5use crate::{RORegister, RWRegister, WORegister};
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// Control register 1
10pub mod CR1 {
11
12 /// Peripheral enable
13 pub mod PE {
14 /// Offset (0 bits)
15 pub const offset: u32 = 0;
16 /// Mask (1 bit: 1 << 0)
17 pub const mask: u32 = 1 << offset;
18 /// Read-only values (empty)
19 pub mod R {}
20 /// Write-only values (empty)
21 pub mod W {}
22 /// Read-write values
23 pub mod RW {
24
25 /// 0b0: Peripheral disabled
26 pub const Disabled: u32 = 0b0;
27
28 /// 0b1: Peripheral enabled
29 pub const Enabled: u32 = 0b1;
30 }
31 }
32
33 /// TXIE
34 pub mod TXIE {
35 /// Offset (1 bits)
36 pub const offset: u32 = 1;
37 /// Mask (1 bit: 1 << 1)
38 pub const mask: u32 = 1 << offset;
39 /// Read-only values (empty)
40 pub mod R {}
41 /// Write-only values (empty)
42 pub mod W {}
43 /// Read-write values
44 pub mod RW {
45
46 /// 0b0: Transmit (TXIS) interrupt disabled
47 pub const Disabled: u32 = 0b0;
48
49 /// 0b1: Transmit (TXIS) interrupt enabled
50 pub const Enabled: u32 = 0b1;
51 }
52 }
53
54 /// RXIE
55 pub mod RXIE {
56 /// Offset (2 bits)
57 pub const offset: u32 = 2;
58 /// Mask (1 bit: 1 << 2)
59 pub const mask: u32 = 1 << offset;
60 /// Read-only values (empty)
61 pub mod R {}
62 /// Write-only values (empty)
63 pub mod W {}
64 /// Read-write values
65 pub mod RW {
66
67 /// 0b0: Receive (RXNE) interrupt disabled
68 pub const Disabled: u32 = 0b0;
69
70 /// 0b1: Receive (RXNE) interrupt enabled
71 pub const Enabled: u32 = 0b1;
72 }
73 }
74
75 /// ADDRE
76 pub mod ADDRIE {
77 /// Offset (3 bits)
78 pub const offset: u32 = 3;
79 /// Mask (1 bit: 1 << 3)
80 pub const mask: u32 = 1 << offset;
81 /// Read-only values (empty)
82 pub mod R {}
83 /// Write-only values (empty)
84 pub mod W {}
85 /// Read-write values
86 pub mod RW {
87
88 /// 0b0: Address match (ADDR) interrupts disabled
89 pub const Disabled: u32 = 0b0;
90
91 /// 0b1: Address match (ADDR) interrupts enabled
92 pub const Enabled: u32 = 0b1;
93 }
94 }
95
96 /// NACKIE
97 pub mod NACKIE {
98 /// Offset (4 bits)
99 pub const offset: u32 = 4;
100 /// Mask (1 bit: 1 << 4)
101 pub const mask: u32 = 1 << offset;
102 /// Read-only values (empty)
103 pub mod R {}
104 /// Write-only values (empty)
105 pub mod W {}
106 /// Read-write values
107 pub mod RW {
108
109 /// 0b0: Not acknowledge (NACKF) received interrupts disabled
110 pub const Disabled: u32 = 0b0;
111
112 /// 0b1: Not acknowledge (NACKF) received interrupts enabled
113 pub const Enabled: u32 = 0b1;
114 }
115 }
116
117 /// STOPIE
118 pub mod STOPIE {
119 /// Offset (5 bits)
120 pub const offset: u32 = 5;
121 /// Mask (1 bit: 1 << 5)
122 pub const mask: u32 = 1 << offset;
123 /// Read-only values (empty)
124 pub mod R {}
125 /// Write-only values (empty)
126 pub mod W {}
127 /// Read-write values
128 pub mod RW {
129
130 /// 0b0: Stop detection (STOPF) interrupt disabled
131 pub const Disabled: u32 = 0b0;
132
133 /// 0b1: Stop detection (STOPF) interrupt enabled
134 pub const Enabled: u32 = 0b1;
135 }
136 }
137
138 /// TCIE
139 pub mod TCIE {
140 /// Offset (6 bits)
141 pub const offset: u32 = 6;
142 /// Mask (1 bit: 1 << 6)
143 pub const mask: u32 = 1 << offset;
144 /// Read-only values (empty)
145 pub mod R {}
146 /// Write-only values (empty)
147 pub mod W {}
148 /// Read-write values
149 pub mod RW {
150
151 /// 0b0: Transfer Complete interrupt disabled
152 pub const Disabled: u32 = 0b0;
153
154 /// 0b1: Transfer Complete interrupt enabled
155 pub const Enabled: u32 = 0b1;
156 }
157 }
158
159 /// ERRIE
160 pub mod ERRIE {
161 /// Offset (7 bits)
162 pub const offset: u32 = 7;
163 /// Mask (1 bit: 1 << 7)
164 pub const mask: u32 = 1 << offset;
165 /// Read-only values (empty)
166 pub mod R {}
167 /// Write-only values (empty)
168 pub mod W {}
169 /// Read-write values
170 pub mod RW {
171
172 /// 0b0: Error detection interrupts disabled
173 pub const Disabled: u32 = 0b0;
174
175 /// 0b1: Error detection interrupts enabled
176 pub const Enabled: u32 = 0b1;
177 }
178 }
179
180 /// DNF
181 pub mod DNF {
182 /// Offset (8 bits)
183 pub const offset: u32 = 8;
184 /// Mask (4 bits: 0b1111 << 8)
185 pub const mask: u32 = 0b1111 << offset;
186 /// Read-only values (empty)
187 pub mod R {}
188 /// Write-only values (empty)
189 pub mod W {}
190 /// Read-write values
191 pub mod RW {
192
193 /// 0b0000: Digital filter disabled
194 pub const NoFilter: u32 = 0b0000;
195
196 /// 0b0001: Digital filter enabled and filtering capability up to 1 tI2CCLK
197 pub const Filter1: u32 = 0b0001;
198
199 /// 0b0010: Digital filter enabled and filtering capability up to 2 tI2CCLK
200 pub const Filter2: u32 = 0b0010;
201
202 /// 0b0011: Digital filter enabled and filtering capability up to 3 tI2CCLK
203 pub const Filter3: u32 = 0b0011;
204
205 /// 0b0100: Digital filter enabled and filtering capability up to 4 tI2CCLK
206 pub const Filter4: u32 = 0b0100;
207
208 /// 0b0101: Digital filter enabled and filtering capability up to 5 tI2CCLK
209 pub const Filter5: u32 = 0b0101;
210
211 /// 0b0110: Digital filter enabled and filtering capability up to 6 tI2CCLK
212 pub const Filter6: u32 = 0b0110;
213
214 /// 0b0111: Digital filter enabled and filtering capability up to 7 tI2CCLK
215 pub const Filter7: u32 = 0b0111;
216
217 /// 0b1000: Digital filter enabled and filtering capability up to 8 tI2CCLK
218 pub const Filter8: u32 = 0b1000;
219
220 /// 0b1001: Digital filter enabled and filtering capability up to 9 tI2CCLK
221 pub const Filter9: u32 = 0b1001;
222
223 /// 0b1010: Digital filter enabled and filtering capability up to 10 tI2CCLK
224 pub const Filter10: u32 = 0b1010;
225
226 /// 0b1011: Digital filter enabled and filtering capability up to 11 tI2CCLK
227 pub const Filter11: u32 = 0b1011;
228
229 /// 0b1100: Digital filter enabled and filtering capability up to 12 tI2CCLK
230 pub const Filter12: u32 = 0b1100;
231
232 /// 0b1101: Digital filter enabled and filtering capability up to 13 tI2CCLK
233 pub const Filter13: u32 = 0b1101;
234
235 /// 0b1110: Digital filter enabled and filtering capability up to 14 tI2CCLK
236 pub const Filter14: u32 = 0b1110;
237
238 /// 0b1111: Digital filter enabled and filtering capability up to 15 tI2CCLK
239 pub const Filter15: u32 = 0b1111;
240 }
241 }
242
243 /// ANFOFF
244 pub mod ANFOFF {
245 /// Offset (12 bits)
246 pub const offset: u32 = 12;
247 /// Mask (1 bit: 1 << 12)
248 pub const mask: u32 = 1 << offset;
249 /// Read-only values (empty)
250 pub mod R {}
251 /// Write-only values (empty)
252 pub mod W {}
253 /// Read-write values
254 pub mod RW {
255
256 /// 0b0: Analog noise filter enabled
257 pub const Enabled: u32 = 0b0;
258
259 /// 0b1: Analog noise filter disabled
260 pub const Disabled: u32 = 0b1;
261 }
262 }
263
264 /// TCDMAEN
265 pub mod TXDMAEN {
266 /// Offset (14 bits)
267 pub const offset: u32 = 14;
268 /// Mask (1 bit: 1 << 14)
269 pub const mask: u32 = 1 << offset;
270 /// Read-only values (empty)
271 pub mod R {}
272 /// Write-only values (empty)
273 pub mod W {}
274 /// Read-write values
275 pub mod RW {
276
277 /// 0b0: DMA mode disabled for transmission
278 pub const Disabled: u32 = 0b0;
279
280 /// 0b1: DMA mode enabled for transmission
281 pub const Enabled: u32 = 0b1;
282 }
283 }
284
285 /// RXDMAEN
286 pub mod RXDMAEN {
287 /// Offset (15 bits)
288 pub const offset: u32 = 15;
289 /// Mask (1 bit: 1 << 15)
290 pub const mask: u32 = 1 << offset;
291 /// Read-only values (empty)
292 pub mod R {}
293 /// Write-only values (empty)
294 pub mod W {}
295 /// Read-write values
296 pub mod RW {
297
298 /// 0b0: DMA mode disabled for reception
299 pub const Disabled: u32 = 0b0;
300
301 /// 0b1: DMA mode enabled for reception
302 pub const Enabled: u32 = 0b1;
303 }
304 }
305
306 /// SBC
307 pub mod SBC {
308 /// Offset (16 bits)
309 pub const offset: u32 = 16;
310 /// Mask (1 bit: 1 << 16)
311 pub const mask: u32 = 1 << offset;
312 /// Read-only values (empty)
313 pub mod R {}
314 /// Write-only values (empty)
315 pub mod W {}
316 /// Read-write values
317 pub mod RW {
318
319 /// 0b0: Slave byte control disabled
320 pub const Disabled: u32 = 0b0;
321
322 /// 0b1: Slave byte control enabled
323 pub const Enabled: u32 = 0b1;
324 }
325 }
326
327 /// NOSTRETCH
328 pub mod NOSTRETCH {
329 /// Offset (17 bits)
330 pub const offset: u32 = 17;
331 /// Mask (1 bit: 1 << 17)
332 pub const mask: u32 = 1 << offset;
333 /// Read-only values (empty)
334 pub mod R {}
335 /// Write-only values (empty)
336 pub mod W {}
337 /// Read-write values
338 pub mod RW {
339
340 /// 0b0: Clock stretching enabled
341 pub const Enabled: u32 = 0b0;
342
343 /// 0b1: Clock stretching disabled
344 pub const Disabled: u32 = 0b1;
345 }
346 }
347
348 /// GCEN
349 pub mod GCEN {
350 /// Offset (19 bits)
351 pub const offset: u32 = 19;
352 /// Mask (1 bit: 1 << 19)
353 pub const mask: u32 = 1 << offset;
354 /// Read-only values (empty)
355 pub mod R {}
356 /// Write-only values (empty)
357 pub mod W {}
358 /// Read-write values
359 pub mod RW {
360
361 /// 0b0: General call disabled. Address 0b00000000 is NACKed
362 pub const Disabled: u32 = 0b0;
363
364 /// 0b1: General call enabled. Address 0b00000000 is ACKed
365 pub const Enabled: u32 = 0b1;
366 }
367 }
368
369 /// SMBHEN
370 pub mod SMBHEN {
371 /// Offset (20 bits)
372 pub const offset: u32 = 20;
373 /// Mask (1 bit: 1 << 20)
374 pub const mask: u32 = 1 << offset;
375 /// Read-only values (empty)
376 pub mod R {}
377 /// Write-only values (empty)
378 pub mod W {}
379 /// Read-write values
380 pub mod RW {
381
382 /// 0b0: Host address disabled. Address 0b0001000x is NACKed
383 pub const Disabled: u32 = 0b0;
384
385 /// 0b1: Host address enabled. Address 0b0001000x is ACKed
386 pub const Enabled: u32 = 0b1;
387 }
388 }
389
390 /// SMBDEN
391 pub mod SMBDEN {
392 /// Offset (21 bits)
393 pub const offset: u32 = 21;
394 /// Mask (1 bit: 1 << 21)
395 pub const mask: u32 = 1 << offset;
396 /// Read-only values (empty)
397 pub mod R {}
398 /// Write-only values (empty)
399 pub mod W {}
400 /// Read-write values
401 pub mod RW {
402
403 /// 0b0: Device default address disabled. Address 0b1100001x is NACKed
404 pub const Disabled: u32 = 0b0;
405
406 /// 0b1: Device default address enabled. Address 0b1100001x is ACKed
407 pub const Enabled: u32 = 0b1;
408 }
409 }
410
411 /// ALERTEN
412 pub mod ALERTEN {
413 /// Offset (22 bits)
414 pub const offset: u32 = 22;
415 /// Mask (1 bit: 1 << 22)
416 pub const mask: u32 = 1 << offset;
417 /// Read-only values (empty)
418 pub mod R {}
419 /// Write-only values (empty)
420 pub mod W {}
421 /// Read-write values
422 pub mod RW {
423
424 /// 0b0: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
425 pub const Disabled: u32 = 0b0;
426
427 /// 0b1: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported
428 pub const Enabled: u32 = 0b1;
429 }
430 }
431
432 /// PECEN
433 pub mod PECEN {
434 /// Offset (23 bits)
435 pub const offset: u32 = 23;
436 /// Mask (1 bit: 1 << 23)
437 pub const mask: u32 = 1 << offset;
438 /// Read-only values (empty)
439 pub mod R {}
440 /// Write-only values (empty)
441 pub mod W {}
442 /// Read-write values
443 pub mod RW {
444
445 /// 0b0: PEC calculation disabled
446 pub const Disabled: u32 = 0b0;
447
448 /// 0b1: PEC calculation enabled
449 pub const Enabled: u32 = 0b1;
450 }
451 }
452}
453
454/// Control register 2
455pub mod CR2 {
456
457 /// Transfer direction
458 pub mod RD_WRN {
459 /// Offset (10 bits)
460 pub const offset: u32 = 10;
461 /// Mask (1 bit: 1 << 10)
462 pub const mask: u32 = 1 << offset;
463 /// Read-only values (empty)
464 pub mod R {}
465 /// Write-only values (empty)
466 pub mod W {}
467 /// Read-write values
468 pub mod RW {
469
470 /// 0b0: Master requests a write transfer
471 pub const Write: u32 = 0b0;
472
473 /// 0b1: Master requests a read transfer
474 pub const Read: u32 = 0b1;
475 }
476 }
477
478 /// 10-bit addressing mode
479 pub mod ADD10 {
480 /// Offset (11 bits)
481 pub const offset: u32 = 11;
482 /// Mask (1 bit: 1 << 11)
483 pub const mask: u32 = 1 << offset;
484 /// Read-only values (empty)
485 pub mod R {}
486 /// Write-only values (empty)
487 pub mod W {}
488 /// Read-write values
489 pub mod RW {
490
491 /// 0b0: The master operates in 7-bit addressing mode
492 pub const Bit7: u32 = 0b0;
493
494 /// 0b1: The master operates in 10-bit addressing mode
495 pub const Bit10: u32 = 0b1;
496 }
497 }
498
499 /// 10-bit address header only read direction
500 pub mod HEAD10R {
501 /// Offset (12 bits)
502 pub const offset: u32 = 12;
503 /// Mask (1 bit: 1 << 12)
504 pub const mask: u32 = 1 << offset;
505 /// Read-only values (empty)
506 pub mod R {}
507 /// Write-only values (empty)
508 pub mod W {}
509 /// Read-write values
510 pub mod RW {
511
512 /// 0b0: The master sends the complete 10 bit slave address read sequence
513 pub const Complete: u32 = 0b0;
514
515 /// 0b1: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction
516 pub const Partial: u32 = 0b1;
517 }
518 }
519
520 /// Start generation
521 pub mod START {
522 /// Offset (13 bits)
523 pub const offset: u32 = 13;
524 /// Mask (1 bit: 1 << 13)
525 pub const mask: u32 = 1 << offset;
526 /// Read-only values (empty)
527 pub mod R {}
528 /// Write-only values (empty)
529 pub mod W {}
530 /// Read-write values
531 pub mod RW {
532
533 /// 0b0: No Start generation
534 pub const NoStart: u32 = 0b0;
535
536 /// 0b1: Restart/Start generation
537 pub const Start: u32 = 0b1;
538 }
539 }
540
541 /// Stop generation
542 pub mod STOP {
543 /// Offset (14 bits)
544 pub const offset: u32 = 14;
545 /// Mask (1 bit: 1 << 14)
546 pub const mask: u32 = 1 << offset;
547 /// Read-only values (empty)
548 pub mod R {}
549 /// Write-only values (empty)
550 pub mod W {}
551 /// Read-write values
552 pub mod RW {
553
554 /// 0b0: No Stop generation
555 pub const NoStop: u32 = 0b0;
556
557 /// 0b1: Stop generation after current byte transfer
558 pub const Stop: u32 = 0b1;
559 }
560 }
561
562 /// NACK generation
563 pub mod NACK {
564 /// Offset (15 bits)
565 pub const offset: u32 = 15;
566 /// Mask (1 bit: 1 << 15)
567 pub const mask: u32 = 1 << offset;
568 /// Read-only values (empty)
569 pub mod R {}
570 /// Write-only values (empty)
571 pub mod W {}
572 /// Read-write values
573 pub mod RW {
574
575 /// 0b0: an ACK is sent after current received byte
576 pub const Ack: u32 = 0b0;
577
578 /// 0b1: a NACK is sent after current received byte
579 pub const Nack: u32 = 0b1;
580 }
581 }
582
583 /// Number of bytes
584 pub mod NBYTES {
585 /// Offset (16 bits)
586 pub const offset: u32 = 16;
587 /// Mask (8 bits: 0xff << 16)
588 pub const mask: u32 = 0xff << offset;
589 /// Read-only values (empty)
590 pub mod R {}
591 /// Write-only values (empty)
592 pub mod W {}
593 /// Read-write values (empty)
594 pub mod RW {}
595 }
596
597 /// NBYTES reload mode
598 pub mod RELOAD {
599 /// Offset (24 bits)
600 pub const offset: u32 = 24;
601 /// Mask (1 bit: 1 << 24)
602 pub const mask: u32 = 1 << offset;
603 /// Read-only values (empty)
604 pub mod R {}
605 /// Write-only values (empty)
606 pub mod W {}
607 /// Read-write values
608 pub mod RW {
609
610 /// 0b0: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
611 pub const Completed: u32 = 0b0;
612
613 /// 0b1: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)
614 pub const NotCompleted: u32 = 0b1;
615 }
616 }
617
618 /// Automatic end mode
619 pub mod AUTOEND {
620 /// Offset (25 bits)
621 pub const offset: u32 = 25;
622 /// Mask (1 bit: 1 << 25)
623 pub const mask: u32 = 1 << offset;
624 /// Read-only values (empty)
625 pub mod R {}
626 /// Write-only values (empty)
627 pub mod W {}
628 /// Read-write values
629 pub mod RW {
630
631 /// 0b0: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
632 pub const Software: u32 = 0b0;
633
634 /// 0b1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred
635 pub const Automatic: u32 = 0b1;
636 }
637 }
638
639 /// Packet error checking byte
640 pub mod PECBYTE {
641 /// Offset (26 bits)
642 pub const offset: u32 = 26;
643 /// Mask (1 bit: 1 << 26)
644 pub const mask: u32 = 1 << offset;
645 /// Read-only values (empty)
646 pub mod R {}
647 /// Write-only values (empty)
648 pub mod W {}
649 /// Read-write values
650 pub mod RW {
651
652 /// 0b0: No PEC transfer
653 pub const NoPec: u32 = 0b0;
654
655 /// 0b1: PEC transmission/reception is requested
656 pub const Pec: u32 = 0b1;
657 }
658 }
659
660 /// Slave address bit 0
661 pub mod SADD {
662 /// Offset (0 bits)
663 pub const offset: u32 = 0;
664 /// Mask (10 bits: 0x3ff << 0)
665 pub const mask: u32 = 0x3ff << offset;
666 /// Read-only values (empty)
667 pub mod R {}
668 /// Write-only values (empty)
669 pub mod W {}
670 /// Read-write values (empty)
671 pub mod RW {}
672 }
673}
674
675/// Own address register 1
676pub mod OAR1 {
677
678 /// OA1
679 pub mod OA1 {
680 /// Offset (0 bits)
681 pub const offset: u32 = 0;
682 /// Mask (1 bit: 1 << 0)
683 pub const mask: u32 = 1 << offset;
684 /// Read-only values (empty)
685 pub mod R {}
686 /// Write-only values (empty)
687 pub mod W {}
688 /// Read-write values (empty)
689 pub mod RW {}
690 }
691
692 /// OA11_7
693 pub mod OA11_7 {
694 /// Offset (1 bits)
695 pub const offset: u32 = 1;
696 /// Mask (7 bits: 0x7f << 1)
697 pub const mask: u32 = 0x7f << offset;
698 /// Read-only values (empty)
699 pub mod R {}
700 /// Write-only values (empty)
701 pub mod W {}
702 /// Read-write values (empty)
703 pub mod RW {}
704 }
705
706 /// OA18_9
707 pub mod OA18_9 {
708 /// Offset (8 bits)
709 pub const offset: u32 = 8;
710 /// Mask (2 bits: 0b11 << 8)
711 pub const mask: u32 = 0b11 << offset;
712 /// Read-only values (empty)
713 pub mod R {}
714 /// Write-only values (empty)
715 pub mod W {}
716 /// Read-write values (empty)
717 pub mod RW {}
718 }
719
720 /// OA1MODE
721 pub mod OA1MODE {
722 /// Offset (10 bits)
723 pub const offset: u32 = 10;
724 /// Mask (1 bit: 1 << 10)
725 pub const mask: u32 = 1 << offset;
726 /// Read-only values (empty)
727 pub mod R {}
728 /// Write-only values (empty)
729 pub mod W {}
730 /// Read-write values
731 pub mod RW {
732
733 /// 0b0: Own address 1 is a 7-bit address
734 pub const Bit7: u32 = 0b0;
735
736 /// 0b1: Own address 1 is a 10-bit address
737 pub const Bit10: u32 = 0b1;
738 }
739 }
740
741 /// OA1EN
742 pub mod OA1EN {
743 /// Offset (15 bits)
744 pub const offset: u32 = 15;
745 /// Mask (1 bit: 1 << 15)
746 pub const mask: u32 = 1 << offset;
747 /// Read-only values (empty)
748 pub mod R {}
749 /// Write-only values (empty)
750 pub mod W {}
751 /// Read-write values
752 pub mod RW {
753
754 /// 0b0: Own address 1 disabled. The received slave address OA1 is NACKed
755 pub const Disabled: u32 = 0b0;
756
757 /// 0b1: Own address 1 enabled. The received slave address OA1 is ACKed
758 pub const Enabled: u32 = 0b1;
759 }
760 }
761}
762
763/// Own address register 2
764pub mod OAR2 {
765
766 /// OA21_7
767 pub mod OA2 {
768 /// Offset (1 bits)
769 pub const offset: u32 = 1;
770 /// Mask (7 bits: 0x7f << 1)
771 pub const mask: u32 = 0x7f << offset;
772 /// Read-only values (empty)
773 pub mod R {}
774 /// Write-only values (empty)
775 pub mod W {}
776 /// Read-write values (empty)
777 pub mod RW {}
778 }
779
780 /// OA2MSK
781 pub mod OA2MSK {
782 /// Offset (8 bits)
783 pub const offset: u32 = 8;
784 /// Mask (3 bits: 0b111 << 8)
785 pub const mask: u32 = 0b111 << offset;
786 /// Read-only values (empty)
787 pub mod R {}
788 /// Write-only values (empty)
789 pub mod W {}
790 /// Read-write values
791 pub mod RW {
792
793 /// 0b000: No mask
794 pub const NoMask: u32 = 0b000;
795
796 /// 0b001: OA2\[1\] is masked and don’t care. Only OA2\[7:2\] are compared
797 pub const Mask1: u32 = 0b001;
798
799 /// 0b010: OA2\[2:1\] are masked and don’t care. Only OA2\[7:3\] are compared
800 pub const Mask2: u32 = 0b010;
801
802 /// 0b011: OA2\[3:1\] are masked and don’t care. Only OA2\[7:4\] are compared
803 pub const Mask3: u32 = 0b011;
804
805 /// 0b100: OA2\[4:1\] are masked and don’t care. Only OA2\[7:5\] are compared
806 pub const Mask4: u32 = 0b100;
807
808 /// 0b101: OA2\[5:1\] are masked and don’t care. Only OA2\[7:6\] are compared
809 pub const Mask5: u32 = 0b101;
810
811 /// 0b110: OA2\[6:1\] are masked and don’t care. Only OA2\[7\] is compared.
812 pub const Mask6: u32 = 0b110;
813
814 /// 0b111: OA2\[7:1\] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
815 pub const Mask7: u32 = 0b111;
816 }
817 }
818
819 /// OA2EN
820 pub mod OA2EN {
821 /// Offset (15 bits)
822 pub const offset: u32 = 15;
823 /// Mask (1 bit: 1 << 15)
824 pub const mask: u32 = 1 << offset;
825 /// Read-only values (empty)
826 pub mod R {}
827 /// Write-only values (empty)
828 pub mod W {}
829 /// Read-write values
830 pub mod RW {
831
832 /// 0b0: Own address 2 disabled. The received slave address OA2 is NACKed
833 pub const Disabled: u32 = 0b0;
834
835 /// 0b1: Own address 2 enabled. The received slave address OA2 is ACKed
836 pub const Enabled: u32 = 0b1;
837 }
838 }
839}
840
841/// Timing register
842pub mod TIMINGR {
843
844 /// SCLL
845 pub mod SCLL {
846 /// Offset (0 bits)
847 pub const offset: u32 = 0;
848 /// Mask (8 bits: 0xff << 0)
849 pub const mask: u32 = 0xff << offset;
850 /// Read-only values (empty)
851 pub mod R {}
852 /// Write-only values (empty)
853 pub mod W {}
854 /// Read-write values (empty)
855 pub mod RW {}
856 }
857
858 /// SCLH
859 pub mod SCLH {
860 /// Offset (8 bits)
861 pub const offset: u32 = 8;
862 /// Mask (8 bits: 0xff << 8)
863 pub const mask: u32 = 0xff << offset;
864 /// Read-only values (empty)
865 pub mod R {}
866 /// Write-only values (empty)
867 pub mod W {}
868 /// Read-write values (empty)
869 pub mod RW {}
870 }
871
872 /// SDADEL
873 pub mod SDADEL {
874 /// Offset (16 bits)
875 pub const offset: u32 = 16;
876 /// Mask (4 bits: 0b1111 << 16)
877 pub const mask: u32 = 0b1111 << offset;
878 /// Read-only values (empty)
879 pub mod R {}
880 /// Write-only values (empty)
881 pub mod W {}
882 /// Read-write values (empty)
883 pub mod RW {}
884 }
885
886 /// SCLDEL
887 pub mod SCLDEL {
888 /// Offset (20 bits)
889 pub const offset: u32 = 20;
890 /// Mask (4 bits: 0b1111 << 20)
891 pub const mask: u32 = 0b1111 << offset;
892 /// Read-only values (empty)
893 pub mod R {}
894 /// Write-only values (empty)
895 pub mod W {}
896 /// Read-write values (empty)
897 pub mod RW {}
898 }
899
900 /// PRESC
901 pub mod PRESC {
902 /// Offset (28 bits)
903 pub const offset: u32 = 28;
904 /// Mask (4 bits: 0b1111 << 28)
905 pub const mask: u32 = 0b1111 << offset;
906 /// Read-only values (empty)
907 pub mod R {}
908 /// Write-only values (empty)
909 pub mod W {}
910 /// Read-write values (empty)
911 pub mod RW {}
912 }
913}
914
915/// Timeout register
916pub mod TIMEOUTR {
917
918 /// TIMEOUTA
919 pub mod TIMEOUTA {
920 /// Offset (0 bits)
921 pub const offset: u32 = 0;
922 /// Mask (12 bits: 0xfff << 0)
923 pub const mask: u32 = 0xfff << offset;
924 /// Read-only values (empty)
925 pub mod R {}
926 /// Write-only values (empty)
927 pub mod W {}
928 /// Read-write values (empty)
929 pub mod RW {}
930 }
931
932 /// TIDLE
933 pub mod TIDLE {
934 /// Offset (12 bits)
935 pub const offset: u32 = 12;
936 /// Mask (1 bit: 1 << 12)
937 pub const mask: u32 = 1 << offset;
938 /// Read-only values (empty)
939 pub mod R {}
940 /// Write-only values (empty)
941 pub mod W {}
942 /// Read-write values
943 pub mod RW {
944
945 /// 0b0: TIMEOUTA is used to detect SCL low timeout
946 pub const Disabled: u32 = 0b0;
947
948 /// 0b1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
949 pub const Enabled: u32 = 0b1;
950 }
951 }
952
953 /// TIMOUTEN
954 pub mod TIMOUTEN {
955 /// Offset (15 bits)
956 pub const offset: u32 = 15;
957 /// Mask (1 bit: 1 << 15)
958 pub const mask: u32 = 1 << offset;
959 /// Read-only values (empty)
960 pub mod R {}
961 /// Write-only values (empty)
962 pub mod W {}
963 /// Read-write values
964 pub mod RW {
965
966 /// 0b0: SCL timeout detection is disabled
967 pub const Disabled: u32 = 0b0;
968
969 /// 0b1: SCL timeout detection is enabled
970 pub const Enabled: u32 = 0b1;
971 }
972 }
973
974 /// TIMEOUTB
975 pub mod TIMEOUTB {
976 /// Offset (16 bits)
977 pub const offset: u32 = 16;
978 /// Mask (12 bits: 0xfff << 16)
979 pub const mask: u32 = 0xfff << offset;
980 /// Read-only values (empty)
981 pub mod R {}
982 /// Write-only values (empty)
983 pub mod W {}
984 /// Read-write values (empty)
985 pub mod RW {}
986 }
987
988 /// TEXTEN
989 pub mod TEXTEN {
990 /// Offset (31 bits)
991 pub const offset: u32 = 31;
992 /// Mask (1 bit: 1 << 31)
993 pub const mask: u32 = 1 << offset;
994 /// Read-only values (empty)
995 pub mod R {}
996 /// Write-only values (empty)
997 pub mod W {}
998 /// Read-write values
999 pub mod RW {
1000
1001 /// 0b0: Extended clock timeout detection is disabled
1002 pub const Disabled: u32 = 0b0;
1003
1004 /// 0b1: Extended clock timeout detection is enabled
1005 pub const Enabled: u32 = 0b1;
1006 }
1007 }
1008}
1009
1010/// Interrupt and Status register
1011pub mod ISR {
1012
1013 /// TXE
1014 pub mod TXE {
1015 /// Offset (0 bits)
1016 pub const offset: u32 = 0;
1017 /// Mask (1 bit: 1 << 0)
1018 pub const mask: u32 = 1 << offset;
1019 /// Read-only values (empty)
1020 pub mod R {}
1021 /// Write-only values (empty)
1022 pub mod W {}
1023 /// Read-write values
1024 pub mod RW {
1025
1026 /// 0b0: TXDR register not empty
1027 pub const NotEmpty: u32 = 0b0;
1028
1029 /// 0b1: TXDR register empty
1030 pub const Empty: u32 = 0b1;
1031 }
1032 }
1033
1034 /// TXIS
1035 pub mod TXIS {
1036 /// Offset (1 bits)
1037 pub const offset: u32 = 1;
1038 /// Mask (1 bit: 1 << 1)
1039 pub const mask: u32 = 1 << offset;
1040 /// Read-only values (empty)
1041 pub mod R {}
1042 /// Write-only values (empty)
1043 pub mod W {}
1044 /// Read-write values
1045 pub mod RW {
1046
1047 /// 0b0: The TXDR register is not empty
1048 pub const NotEmpty: u32 = 0b0;
1049
1050 /// 0b1: The TXDR register is empty and the data to be transmitted must be written in the TXDR register
1051 pub const Empty: u32 = 0b1;
1052 }
1053 }
1054
1055 /// RXNE
1056 pub mod RXNE {
1057 /// Offset (2 bits)
1058 pub const offset: u32 = 2;
1059 /// Mask (1 bit: 1 << 2)
1060 pub const mask: u32 = 1 << offset;
1061 /// Read-only values
1062 pub mod R {
1063
1064 /// 0b0: The RXDR register is empty
1065 pub const Empty: u32 = 0b0;
1066
1067 /// 0b1: Received data is copied into the RXDR register, and is ready to be read
1068 pub const NotEmpty: u32 = 0b1;
1069 }
1070 /// Write-only values (empty)
1071 pub mod W {}
1072 /// Read-write values (empty)
1073 pub mod RW {}
1074 }
1075
1076 /// ADDR
1077 pub mod ADDR {
1078 /// Offset (3 bits)
1079 pub const offset: u32 = 3;
1080 /// Mask (1 bit: 1 << 3)
1081 pub const mask: u32 = 1 << offset;
1082 /// Read-only values
1083 pub mod R {
1084
1085 /// 0b0: Adress mismatched or not received
1086 pub const NotMatch: u32 = 0b0;
1087
1088 /// 0b1: Received slave address matched with one of the enabled slave addresses
1089 pub const Match: u32 = 0b1;
1090 }
1091 /// Write-only values (empty)
1092 pub mod W {}
1093 /// Read-write values (empty)
1094 pub mod RW {}
1095 }
1096
1097 /// NACKF
1098 pub mod NACKF {
1099 /// Offset (4 bits)
1100 pub const offset: u32 = 4;
1101 /// Mask (1 bit: 1 << 4)
1102 pub const mask: u32 = 1 << offset;
1103 /// Read-only values
1104 pub mod R {
1105
1106 /// 0b0: No NACK has been received
1107 pub const NoNack: u32 = 0b0;
1108
1109 /// 0b1: NACK has been received
1110 pub const Nack: u32 = 0b1;
1111 }
1112 /// Write-only values (empty)
1113 pub mod W {}
1114 /// Read-write values (empty)
1115 pub mod RW {}
1116 }
1117
1118 /// STOPF
1119 pub mod STOPF {
1120 /// Offset (5 bits)
1121 pub const offset: u32 = 5;
1122 /// Mask (1 bit: 1 << 5)
1123 pub const mask: u32 = 1 << offset;
1124 /// Read-only values
1125 pub mod R {
1126
1127 /// 0b0: No Stop condition detected
1128 pub const NoStop: u32 = 0b0;
1129
1130 /// 0b1: Stop condition detected
1131 pub const Stop: u32 = 0b1;
1132 }
1133 /// Write-only values (empty)
1134 pub mod W {}
1135 /// Read-write values (empty)
1136 pub mod RW {}
1137 }
1138
1139 /// TC
1140 pub mod TC {
1141 /// Offset (6 bits)
1142 pub const offset: u32 = 6;
1143 /// Mask (1 bit: 1 << 6)
1144 pub const mask: u32 = 1 << offset;
1145 /// Read-only values
1146 pub mod R {
1147
1148 /// 0b0: Transfer is not complete
1149 pub const NotComplete: u32 = 0b0;
1150
1151 /// 0b1: NBYTES has been transfered
1152 pub const Complete: u32 = 0b1;
1153 }
1154 /// Write-only values (empty)
1155 pub mod W {}
1156 /// Read-write values (empty)
1157 pub mod RW {}
1158 }
1159
1160 /// TCR
1161 pub mod TCR {
1162 /// Offset (7 bits)
1163 pub const offset: u32 = 7;
1164 /// Mask (1 bit: 1 << 7)
1165 pub const mask: u32 = 1 << offset;
1166 pub use super::TC::R;
1167 /// Write-only values (empty)
1168 pub mod W {}
1169 /// Read-write values (empty)
1170 pub mod RW {}
1171 }
1172
1173 /// BERR
1174 pub mod BERR {
1175 /// Offset (8 bits)
1176 pub const offset: u32 = 8;
1177 /// Mask (1 bit: 1 << 8)
1178 pub const mask: u32 = 1 << offset;
1179 /// Read-only values
1180 pub mod R {
1181
1182 /// 0b0: No bus error
1183 pub const NoError: u32 = 0b0;
1184
1185 /// 0b1: Misplaced Start and Stop condition is detected
1186 pub const Error: u32 = 0b1;
1187 }
1188 /// Write-only values (empty)
1189 pub mod W {}
1190 /// Read-write values (empty)
1191 pub mod RW {}
1192 }
1193
1194 /// ARLO
1195 pub mod ARLO {
1196 /// Offset (9 bits)
1197 pub const offset: u32 = 9;
1198 /// Mask (1 bit: 1 << 9)
1199 pub const mask: u32 = 1 << offset;
1200 /// Read-only values
1201 pub mod R {
1202
1203 /// 0b0: No arbitration lost
1204 pub const NotLost: u32 = 0b0;
1205
1206 /// 0b1: Arbitration lost
1207 pub const Lost: u32 = 0b1;
1208 }
1209 /// Write-only values (empty)
1210 pub mod W {}
1211 /// Read-write values (empty)
1212 pub mod RW {}
1213 }
1214
1215 /// OVR
1216 pub mod OVR {
1217 /// Offset (10 bits)
1218 pub const offset: u32 = 10;
1219 /// Mask (1 bit: 1 << 10)
1220 pub const mask: u32 = 1 << offset;
1221 /// Read-only values
1222 pub mod R {
1223
1224 /// 0b0: No overrun/underrun error occurs
1225 pub const NoOverrun: u32 = 0b0;
1226
1227 /// 0b1: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs
1228 pub const Overrun: u32 = 0b1;
1229 }
1230 /// Write-only values (empty)
1231 pub mod W {}
1232 /// Read-write values (empty)
1233 pub mod RW {}
1234 }
1235
1236 /// PECERR
1237 pub mod PECERR {
1238 /// Offset (11 bits)
1239 pub const offset: u32 = 11;
1240 /// Mask (1 bit: 1 << 11)
1241 pub const mask: u32 = 1 << offset;
1242 /// Read-only values
1243 pub mod R {
1244
1245 /// 0b0: Received PEC does match with PEC register
1246 pub const Match: u32 = 0b0;
1247
1248 /// 0b1: Received PEC does not match with PEC register
1249 pub const NoMatch: u32 = 0b1;
1250 }
1251 /// Write-only values (empty)
1252 pub mod W {}
1253 /// Read-write values (empty)
1254 pub mod RW {}
1255 }
1256
1257 /// TIMEOUT
1258 pub mod TIMEOUT {
1259 /// Offset (12 bits)
1260 pub const offset: u32 = 12;
1261 /// Mask (1 bit: 1 << 12)
1262 pub const mask: u32 = 1 << offset;
1263 /// Read-only values
1264 pub mod R {
1265
1266 /// 0b0: No timeout occured
1267 pub const NoTimeout: u32 = 0b0;
1268
1269 /// 0b1: Timeout occured
1270 pub const Timeout: u32 = 0b1;
1271 }
1272 /// Write-only values (empty)
1273 pub mod W {}
1274 /// Read-write values (empty)
1275 pub mod RW {}
1276 }
1277
1278 /// ALERT
1279 pub mod ALERT {
1280 /// Offset (13 bits)
1281 pub const offset: u32 = 13;
1282 /// Mask (1 bit: 1 << 13)
1283 pub const mask: u32 = 1 << offset;
1284 /// Read-only values
1285 pub mod R {
1286
1287 /// 0b0: SMBA alert is not detected
1288 pub const NoAlert: u32 = 0b0;
1289
1290 /// 0b1: SMBA alert event is detected on SMBA pin
1291 pub const Alert: u32 = 0b1;
1292 }
1293 /// Write-only values (empty)
1294 pub mod W {}
1295 /// Read-write values (empty)
1296 pub mod RW {}
1297 }
1298
1299 /// BUSY
1300 pub mod BUSY {
1301 /// Offset (15 bits)
1302 pub const offset: u32 = 15;
1303 /// Mask (1 bit: 1 << 15)
1304 pub const mask: u32 = 1 << offset;
1305 /// Read-only values
1306 pub mod R {
1307
1308 /// 0b0: No communication is in progress on the bus
1309 pub const NotBusy: u32 = 0b0;
1310
1311 /// 0b1: A communication is in progress on the bus
1312 pub const Busy: u32 = 0b1;
1313 }
1314 /// Write-only values (empty)
1315 pub mod W {}
1316 /// Read-write values (empty)
1317 pub mod RW {}
1318 }
1319
1320 /// DIR
1321 pub mod DIR {
1322 /// Offset (16 bits)
1323 pub const offset: u32 = 16;
1324 /// Mask (1 bit: 1 << 16)
1325 pub const mask: u32 = 1 << offset;
1326 /// Read-only values
1327 pub mod R {
1328
1329 /// 0b0: Write transfer, slave enters receiver mode
1330 pub const Write: u32 = 0b0;
1331
1332 /// 0b1: Read transfer, slave enters transmitter mode
1333 pub const Read: u32 = 0b1;
1334 }
1335 /// Write-only values (empty)
1336 pub mod W {}
1337 /// Read-write values (empty)
1338 pub mod RW {}
1339 }
1340
1341 /// ADDCODE
1342 pub mod ADDCODE {
1343 /// Offset (17 bits)
1344 pub const offset: u32 = 17;
1345 /// Mask (7 bits: 0x7f << 17)
1346 pub const mask: u32 = 0x7f << offset;
1347 /// Read-only values (empty)
1348 pub mod R {}
1349 /// Write-only values (empty)
1350 pub mod W {}
1351 /// Read-write values (empty)
1352 pub mod RW {}
1353 }
1354}
1355
1356/// Interrupt clear register
1357pub mod ICR {
1358
1359 /// Address matched flag clear
1360 pub mod ADDRCF {
1361 /// Offset (3 bits)
1362 pub const offset: u32 = 3;
1363 /// Mask (1 bit: 1 << 3)
1364 pub const mask: u32 = 1 << offset;
1365 /// Read-only values (empty)
1366 pub mod R {}
1367 /// Write-only values
1368 pub mod W {
1369
1370 /// 0b1: Clears the ADDR flag in ISR register
1371 pub const Clear: u32 = 0b1;
1372 }
1373 /// Read-write values (empty)
1374 pub mod RW {}
1375 }
1376
1377 /// Not Acknowledge flag clear
1378 pub mod NACKCF {
1379 /// Offset (4 bits)
1380 pub const offset: u32 = 4;
1381 /// Mask (1 bit: 1 << 4)
1382 pub const mask: u32 = 1 << offset;
1383 /// Read-only values (empty)
1384 pub mod R {}
1385 /// Write-only values
1386 pub mod W {
1387
1388 /// 0b1: Clears the NACK flag in ISR register
1389 pub const Clear: u32 = 0b1;
1390 }
1391 /// Read-write values (empty)
1392 pub mod RW {}
1393 }
1394
1395 /// Stop detection flag clear
1396 pub mod STOPCF {
1397 /// Offset (5 bits)
1398 pub const offset: u32 = 5;
1399 /// Mask (1 bit: 1 << 5)
1400 pub const mask: u32 = 1 << offset;
1401 /// Read-only values (empty)
1402 pub mod R {}
1403 /// Write-only values
1404 pub mod W {
1405
1406 /// 0b1: Clears the STOP flag in ISR register
1407 pub const Clear: u32 = 0b1;
1408 }
1409 /// Read-write values (empty)
1410 pub mod RW {}
1411 }
1412
1413 /// Bus error flag clear
1414 pub mod BERRCF {
1415 /// Offset (8 bits)
1416 pub const offset: u32 = 8;
1417 /// Mask (1 bit: 1 << 8)
1418 pub const mask: u32 = 1 << offset;
1419 /// Read-only values (empty)
1420 pub mod R {}
1421 /// Write-only values
1422 pub mod W {
1423
1424 /// 0b1: Clears the BERR flag in ISR register
1425 pub const Clear: u32 = 0b1;
1426 }
1427 /// Read-write values (empty)
1428 pub mod RW {}
1429 }
1430
1431 /// Arbitration Lost flag clear
1432 pub mod ARLOCF {
1433 /// Offset (9 bits)
1434 pub const offset: u32 = 9;
1435 /// Mask (1 bit: 1 << 9)
1436 pub const mask: u32 = 1 << offset;
1437 /// Read-only values (empty)
1438 pub mod R {}
1439 /// Write-only values
1440 pub mod W {
1441
1442 /// 0b1: Clears the ARLO flag in ISR register
1443 pub const Clear: u32 = 0b1;
1444 }
1445 /// Read-write values (empty)
1446 pub mod RW {}
1447 }
1448
1449 /// Overrun/Underrun flag clear
1450 pub mod OVRCF {
1451 /// Offset (10 bits)
1452 pub const offset: u32 = 10;
1453 /// Mask (1 bit: 1 << 10)
1454 pub const mask: u32 = 1 << offset;
1455 /// Read-only values (empty)
1456 pub mod R {}
1457 /// Write-only values
1458 pub mod W {
1459
1460 /// 0b1: Clears the OVR flag in ISR register
1461 pub const Clear: u32 = 0b1;
1462 }
1463 /// Read-write values (empty)
1464 pub mod RW {}
1465 }
1466
1467 /// PEC Error flag clear
1468 pub mod PECCF {
1469 /// Offset (11 bits)
1470 pub const offset: u32 = 11;
1471 /// Mask (1 bit: 1 << 11)
1472 pub const mask: u32 = 1 << offset;
1473 /// Read-only values (empty)
1474 pub mod R {}
1475 /// Write-only values
1476 pub mod W {
1477
1478 /// 0b1: Clears the PEC flag in ISR register
1479 pub const Clear: u32 = 0b1;
1480 }
1481 /// Read-write values (empty)
1482 pub mod RW {}
1483 }
1484
1485 /// Timeout detection flag clear
1486 pub mod TIMOUTCF {
1487 /// Offset (12 bits)
1488 pub const offset: u32 = 12;
1489 /// Mask (1 bit: 1 << 12)
1490 pub const mask: u32 = 1 << offset;
1491 /// Read-only values (empty)
1492 pub mod R {}
1493 /// Write-only values
1494 pub mod W {
1495
1496 /// 0b1: Clears the TIMOUT flag in ISR register
1497 pub const Clear: u32 = 0b1;
1498 }
1499 /// Read-write values (empty)
1500 pub mod RW {}
1501 }
1502
1503 /// Alert flag clear
1504 pub mod ALERTCF {
1505 /// Offset (13 bits)
1506 pub const offset: u32 = 13;
1507 /// Mask (1 bit: 1 << 13)
1508 pub const mask: u32 = 1 << offset;
1509 /// Read-only values (empty)
1510 pub mod R {}
1511 /// Write-only values
1512 pub mod W {
1513
1514 /// 0b1: Clears the ALERT flag in ISR register
1515 pub const Clear: u32 = 0b1;
1516 }
1517 /// Read-write values (empty)
1518 pub mod RW {}
1519 }
1520}
1521
1522/// PEC register
1523pub mod PECR {
1524
1525 /// PEC
1526 pub mod PEC {
1527 /// Offset (0 bits)
1528 pub const offset: u32 = 0;
1529 /// Mask (8 bits: 0xff << 0)
1530 pub const mask: u32 = 0xff << offset;
1531 /// Read-only values (empty)
1532 pub mod R {}
1533 /// Write-only values (empty)
1534 pub mod W {}
1535 /// Read-write values (empty)
1536 pub mod RW {}
1537 }
1538}
1539
1540/// Receive data register
1541pub mod RXDR {
1542
1543 /// RXDATA
1544 pub mod RXDATA {
1545 /// Offset (0 bits)
1546 pub const offset: u32 = 0;
1547 /// Mask (8 bits: 0xff << 0)
1548 pub const mask: u32 = 0xff << offset;
1549 /// Read-only values (empty)
1550 pub mod R {}
1551 /// Write-only values (empty)
1552 pub mod W {}
1553 /// Read-write values (empty)
1554 pub mod RW {}
1555 }
1556}
1557
1558/// Transmit data register
1559pub mod TXDR {
1560
1561 /// TXDATA
1562 pub mod TXDATA {
1563 /// Offset (0 bits)
1564 pub const offset: u32 = 0;
1565 /// Mask (8 bits: 0xff << 0)
1566 pub const mask: u32 = 0xff << offset;
1567 /// Read-only values (empty)
1568 pub mod R {}
1569 /// Write-only values (empty)
1570 pub mod W {}
1571 /// Read-write values (empty)
1572 pub mod RW {}
1573 }
1574}
1575#[repr(C)]
1576pub struct RegisterBlock {
1577 /// Control register 1
1578 pub CR1: RWRegister<u32>,
1579
1580 /// Control register 2
1581 pub CR2: RWRegister<u32>,
1582
1583 /// Own address register 1
1584 pub OAR1: RWRegister<u32>,
1585
1586 /// Own address register 2
1587 pub OAR2: RWRegister<u32>,
1588
1589 /// Timing register
1590 pub TIMINGR: RWRegister<u32>,
1591
1592 /// Timeout register
1593 pub TIMEOUTR: RWRegister<u32>,
1594
1595 /// Interrupt and Status register
1596 pub ISR: RWRegister<u32>,
1597
1598 /// Interrupt clear register
1599 pub ICR: WORegister<u32>,
1600
1601 /// PEC register
1602 pub PECR: RORegister<u32>,
1603
1604 /// Receive data register
1605 pub RXDR: RORegister<u32>,
1606
1607 /// Transmit data register
1608 pub TXDR: RWRegister<u32>,
1609}
1610pub struct ResetValues {
1611 pub CR1: u32,
1612 pub CR2: u32,
1613 pub OAR1: u32,
1614 pub OAR2: u32,
1615 pub TIMINGR: u32,
1616 pub TIMEOUTR: u32,
1617 pub ISR: u32,
1618 pub ICR: u32,
1619 pub PECR: u32,
1620 pub RXDR: u32,
1621 pub TXDR: u32,
1622}
1623#[cfg(not(feature = "nosync"))]
1624pub struct Instance {
1625 pub(crate) addr: u32,
1626 pub(crate) _marker: PhantomData<*const RegisterBlock>,
1627}
1628#[cfg(not(feature = "nosync"))]
1629impl ::core::ops::Deref for Instance {
1630 type Target = RegisterBlock;
1631 #[inline(always)]
1632 fn deref(&self) -> &RegisterBlock {
1633 unsafe { &*(self.addr as *const _) }
1634 }
1635}
1636#[cfg(feature = "rtic")]
1637unsafe impl Send for Instance {}
1638
1639/// Access functions for the FMPI2C1 peripheral instance
1640pub mod FMPI2C1 {
1641 use super::ResetValues;
1642
1643 #[cfg(not(feature = "nosync"))]
1644 use super::Instance;
1645
1646 #[cfg(not(feature = "nosync"))]
1647 const INSTANCE: Instance = Instance {
1648 addr: 0x40006000,
1649 _marker: ::core::marker::PhantomData,
1650 };
1651
1652 /// Reset values for each field in FMPI2C1
1653 pub const reset: ResetValues = ResetValues {
1654 CR1: 0x00000000,
1655 CR2: 0x00000000,
1656 OAR1: 0x00000000,
1657 OAR2: 0x00000000,
1658 TIMINGR: 0x00000000,
1659 TIMEOUTR: 0x00000000,
1660 ISR: 0x00000001,
1661 ICR: 0x00000000,
1662 PECR: 0x00000000,
1663 RXDR: 0x00000000,
1664 TXDR: 0x00000000,
1665 };
1666
1667 #[cfg(not(feature = "nosync"))]
1668 #[allow(renamed_and_removed_lints)]
1669 #[allow(private_no_mangle_statics)]
1670 #[no_mangle]
1671 static mut FMPI2C1_TAKEN: bool = false;
1672
1673 /// Safe access to FMPI2C1
1674 ///
1675 /// This function returns `Some(Instance)` if this instance is not
1676 /// currently taken, and `None` if it is. This ensures that if you
1677 /// do get `Some(Instance)`, you are ensured unique access to
1678 /// the peripheral and there cannot be data races (unless other
1679 /// code uses `unsafe`, of course). You can then pass the
1680 /// `Instance` around to other functions as required. When you're
1681 /// done with it, you can call `release(instance)` to return it.
1682 ///
1683 /// `Instance` itself dereferences to a `RegisterBlock`, which
1684 /// provides access to the peripheral's registers.
1685 #[cfg(not(feature = "nosync"))]
1686 #[inline]
1687 pub fn take() -> Option<Instance> {
1688 external_cortex_m::interrupt::free(|_| unsafe {
1689 if FMPI2C1_TAKEN {
1690 None
1691 } else {
1692 FMPI2C1_TAKEN = true;
1693 Some(INSTANCE)
1694 }
1695 })
1696 }
1697
1698 /// Release exclusive access to FMPI2C1
1699 ///
1700 /// This function allows you to return an `Instance` so that it
1701 /// is available to `take()` again. This function will panic if
1702 /// you return a different `Instance` or if this instance is not
1703 /// already taken.
1704 #[cfg(not(feature = "nosync"))]
1705 #[inline]
1706 pub fn release(inst: Instance) {
1707 external_cortex_m::interrupt::free(|_| unsafe {
1708 if FMPI2C1_TAKEN && inst.addr == INSTANCE.addr {
1709 FMPI2C1_TAKEN = false;
1710 } else {
1711 panic!("Released a peripheral which was not taken");
1712 }
1713 });
1714 }
1715
1716 /// Unsafely steal FMPI2C1
1717 ///
1718 /// This function is similar to take() but forcibly takes the
1719 /// Instance, marking it as taken irregardless of its previous
1720 /// state.
1721 #[cfg(not(feature = "nosync"))]
1722 #[inline]
1723 pub unsafe fn steal() -> Instance {
1724 FMPI2C1_TAKEN = true;
1725 INSTANCE
1726 }
1727}
1728
1729/// Raw pointer to FMPI2C1
1730///
1731/// Dereferencing this is unsafe because you are not ensured unique
1732/// access to the peripheral, so you may encounter data races with
1733/// other users of this peripheral. It is up to you to ensure you
1734/// will not cause data races.
1735///
1736/// This constant is provided for ease of use in unsafe code: you can
1737/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
1738pub const FMPI2C1: *const RegisterBlock = 0x40006000 as *const _;