stm32ral/stm32f4/peripherals/tim9_v2.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! General purpose timers
4//!
5//! Used by: stm32f412, stm32f413
6
7use crate::{RWRegister, WORegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// control register 1
12pub mod CR1 {
13
14 /// Clock division
15 pub mod CKD {
16 /// Offset (8 bits)
17 pub const offset: u32 = 8;
18 /// Mask (2 bits: 0b11 << 8)
19 pub const mask: u32 = 0b11 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values
25 pub mod RW {
26
27 /// 0b00: t_DTS = t_CK_INT
28 pub const Div1: u32 = 0b00;
29
30 /// 0b01: t_DTS = 2 × t_CK_INT
31 pub const Div2: u32 = 0b01;
32
33 /// 0b10: t_DTS = 4 × t_CK_INT
34 pub const Div4: u32 = 0b10;
35 }
36 }
37
38 /// Auto-reload preload enable
39 pub mod ARPE {
40 /// Offset (7 bits)
41 pub const offset: u32 = 7;
42 /// Mask (1 bit: 1 << 7)
43 pub const mask: u32 = 1 << offset;
44 /// Read-only values (empty)
45 pub mod R {}
46 /// Write-only values (empty)
47 pub mod W {}
48 /// Read-write values
49 pub mod RW {
50
51 /// 0b0: TIMx_APRR register is not buffered
52 pub const Disabled: u32 = 0b0;
53
54 /// 0b1: TIMx_APRR register is buffered
55 pub const Enabled: u32 = 0b1;
56 }
57 }
58
59 /// One-pulse mode
60 pub mod OPM {
61 /// Offset (3 bits)
62 pub const offset: u32 = 3;
63 /// Mask (1 bit: 1 << 3)
64 pub const mask: u32 = 1 << offset;
65 /// Read-only values (empty)
66 pub mod R {}
67 /// Write-only values (empty)
68 pub mod W {}
69 /// Read-write values
70 pub mod RW {
71
72 /// 0b0: Counter is not stopped at update event
73 pub const Disabled: u32 = 0b0;
74
75 /// 0b1: Counter stops counting at the next update event (clearing the CEN bit)
76 pub const Enabled: u32 = 0b1;
77 }
78 }
79
80 /// Update request source
81 pub mod URS {
82 /// Offset (2 bits)
83 pub const offset: u32 = 2;
84 /// Mask (1 bit: 1 << 2)
85 pub const mask: u32 = 1 << offset;
86 /// Read-only values (empty)
87 pub mod R {}
88 /// Write-only values (empty)
89 pub mod W {}
90 /// Read-write values
91 pub mod RW {
92
93 /// 0b0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
94 pub const AnyEvent: u32 = 0b0;
95
96 /// 0b1: Only counter overflow/underflow generates an update interrupt or DMA request
97 pub const CounterOnly: u32 = 0b1;
98 }
99 }
100
101 /// Update disable
102 pub mod UDIS {
103 /// Offset (1 bits)
104 pub const offset: u32 = 1;
105 /// Mask (1 bit: 1 << 1)
106 pub const mask: u32 = 1 << offset;
107 /// Read-only values (empty)
108 pub mod R {}
109 /// Write-only values (empty)
110 pub mod W {}
111 /// Read-write values
112 pub mod RW {
113
114 /// 0b0: Update event enabled
115 pub const Enabled: u32 = 0b0;
116
117 /// 0b1: Update event disabled
118 pub const Disabled: u32 = 0b1;
119 }
120 }
121
122 /// Counter enable
123 pub mod CEN {
124 /// Offset (0 bits)
125 pub const offset: u32 = 0;
126 /// Mask (1 bit: 1 << 0)
127 pub const mask: u32 = 1 << offset;
128 /// Read-only values (empty)
129 pub mod R {}
130 /// Write-only values (empty)
131 pub mod W {}
132 /// Read-write values
133 pub mod RW {
134
135 /// 0b0: Counter disabled
136 pub const Disabled: u32 = 0b0;
137
138 /// 0b1: Counter enabled
139 pub const Enabled: u32 = 0b1;
140 }
141 }
142}
143
144/// slave mode control register
145pub mod SMCR {
146
147 /// Master/Slave mode
148 pub mod MSM {
149 /// Offset (7 bits)
150 pub const offset: u32 = 7;
151 /// Mask (1 bit: 1 << 7)
152 pub const mask: u32 = 1 << offset;
153 /// Read-only values (empty)
154 pub mod R {}
155 /// Write-only values (empty)
156 pub mod W {}
157 /// Read-write values (empty)
158 pub mod RW {}
159 }
160
161 /// Trigger selection
162 pub mod TS {
163 /// Offset (4 bits)
164 pub const offset: u32 = 4;
165 /// Mask (3 bits: 0b111 << 4)
166 pub const mask: u32 = 0b111 << offset;
167 /// Read-only values (empty)
168 pub mod R {}
169 /// Write-only values (empty)
170 pub mod W {}
171 /// Read-write values (empty)
172 pub mod RW {}
173 }
174
175 /// Slave mode selection
176 pub mod SMS {
177 /// Offset (0 bits)
178 pub const offset: u32 = 0;
179 /// Mask (3 bits: 0b111 << 0)
180 pub const mask: u32 = 0b111 << offset;
181 /// Read-only values (empty)
182 pub mod R {}
183 /// Write-only values (empty)
184 pub mod W {}
185 /// Read-write values (empty)
186 pub mod RW {}
187 }
188}
189
190/// DMA/Interrupt enable register
191pub mod DIER {
192
193 /// Trigger interrupt enable
194 pub mod TIE {
195 /// Offset (6 bits)
196 pub const offset: u32 = 6;
197 /// Mask (1 bit: 1 << 6)
198 pub const mask: u32 = 1 << offset;
199 /// Read-only values (empty)
200 pub mod R {}
201 /// Write-only values (empty)
202 pub mod W {}
203 /// Read-write values (empty)
204 pub mod RW {}
205 }
206
207 /// Capture/Compare 2 interrupt enable
208 pub mod CC2IE {
209 /// Offset (2 bits)
210 pub const offset: u32 = 2;
211 /// Mask (1 bit: 1 << 2)
212 pub const mask: u32 = 1 << offset;
213 /// Read-only values (empty)
214 pub mod R {}
215 /// Write-only values (empty)
216 pub mod W {}
217 /// Read-write values (empty)
218 pub mod RW {}
219 }
220
221 /// Capture/Compare 1 interrupt enable
222 pub mod CC1IE {
223 /// Offset (1 bits)
224 pub const offset: u32 = 1;
225 /// Mask (1 bit: 1 << 1)
226 pub const mask: u32 = 1 << offset;
227 /// Read-only values (empty)
228 pub mod R {}
229 /// Write-only values (empty)
230 pub mod W {}
231 /// Read-write values (empty)
232 pub mod RW {}
233 }
234
235 /// Update interrupt enable
236 pub mod UIE {
237 /// Offset (0 bits)
238 pub const offset: u32 = 0;
239 /// Mask (1 bit: 1 << 0)
240 pub const mask: u32 = 1 << offset;
241 /// Read-only values (empty)
242 pub mod R {}
243 /// Write-only values (empty)
244 pub mod W {}
245 /// Read-write values
246 pub mod RW {
247
248 /// 0b0: Update interrupt disabled
249 pub const Disabled: u32 = 0b0;
250
251 /// 0b1: Update interrupt enabled
252 pub const Enabled: u32 = 0b1;
253 }
254 }
255}
256
257/// status register
258pub mod SR {
259
260 /// Capture/compare 2 overcapture flag
261 pub mod CC2OF {
262 /// Offset (10 bits)
263 pub const offset: u32 = 10;
264 /// Mask (1 bit: 1 << 10)
265 pub const mask: u32 = 1 << offset;
266 /// Read-only values (empty)
267 pub mod R {}
268 /// Write-only values (empty)
269 pub mod W {}
270 /// Read-write values (empty)
271 pub mod RW {}
272 }
273
274 /// Capture/Compare 1 overcapture flag
275 pub mod CC1OF {
276 /// Offset (9 bits)
277 pub const offset: u32 = 9;
278 /// Mask (1 bit: 1 << 9)
279 pub const mask: u32 = 1 << offset;
280 /// Read-only values (empty)
281 pub mod R {}
282 /// Write-only values (empty)
283 pub mod W {}
284 /// Read-write values (empty)
285 pub mod RW {}
286 }
287
288 /// Trigger interrupt flag
289 pub mod TIF {
290 /// Offset (6 bits)
291 pub const offset: u32 = 6;
292 /// Mask (1 bit: 1 << 6)
293 pub const mask: u32 = 1 << offset;
294 /// Read-only values (empty)
295 pub mod R {}
296 /// Write-only values (empty)
297 pub mod W {}
298 /// Read-write values (empty)
299 pub mod RW {}
300 }
301
302 /// Capture/Compare 2 interrupt flag
303 pub mod CC2IF {
304 /// Offset (2 bits)
305 pub const offset: u32 = 2;
306 /// Mask (1 bit: 1 << 2)
307 pub const mask: u32 = 1 << offset;
308 /// Read-only values (empty)
309 pub mod R {}
310 /// Write-only values (empty)
311 pub mod W {}
312 /// Read-write values (empty)
313 pub mod RW {}
314 }
315
316 /// Capture/compare 1 interrupt flag
317 pub mod CC1IF {
318 /// Offset (1 bits)
319 pub const offset: u32 = 1;
320 /// Mask (1 bit: 1 << 1)
321 pub const mask: u32 = 1 << offset;
322 /// Read-only values (empty)
323 pub mod R {}
324 /// Write-only values (empty)
325 pub mod W {}
326 /// Read-write values (empty)
327 pub mod RW {}
328 }
329
330 /// Update interrupt flag
331 pub mod UIF {
332 /// Offset (0 bits)
333 pub const offset: u32 = 0;
334 /// Mask (1 bit: 1 << 0)
335 pub const mask: u32 = 1 << offset;
336 /// Read-only values (empty)
337 pub mod R {}
338 /// Write-only values (empty)
339 pub mod W {}
340 /// Read-write values
341 pub mod RW {
342
343 /// 0b0: No update occurred
344 pub const Clear: u32 = 0b0;
345
346 /// 0b1: Update interrupt pending.
347 pub const UpdatePending: u32 = 0b1;
348 }
349 }
350}
351
352/// event generation register
353pub mod EGR {
354
355 /// Trigger generation
356 pub mod TG {
357 /// Offset (6 bits)
358 pub const offset: u32 = 6;
359 /// Mask (1 bit: 1 << 6)
360 pub const mask: u32 = 1 << offset;
361 /// Read-only values (empty)
362 pub mod R {}
363 /// Write-only values (empty)
364 pub mod W {}
365 /// Read-write values (empty)
366 pub mod RW {}
367 }
368
369 /// Capture/compare 2 generation
370 pub mod CC2G {
371 /// Offset (2 bits)
372 pub const offset: u32 = 2;
373 /// Mask (1 bit: 1 << 2)
374 pub const mask: u32 = 1 << offset;
375 /// Read-only values (empty)
376 pub mod R {}
377 /// Write-only values (empty)
378 pub mod W {}
379 /// Read-write values (empty)
380 pub mod RW {}
381 }
382
383 /// Capture/compare 1 generation
384 pub mod CC1G {
385 /// Offset (1 bits)
386 pub const offset: u32 = 1;
387 /// Mask (1 bit: 1 << 1)
388 pub const mask: u32 = 1 << offset;
389 /// Read-only values (empty)
390 pub mod R {}
391 /// Write-only values (empty)
392 pub mod W {}
393 /// Read-write values (empty)
394 pub mod RW {}
395 }
396
397 /// Update generation
398 pub mod UG {
399 /// Offset (0 bits)
400 pub const offset: u32 = 0;
401 /// Mask (1 bit: 1 << 0)
402 pub const mask: u32 = 1 << offset;
403 /// Read-only values (empty)
404 pub mod R {}
405 /// Write-only values
406 pub mod W {
407
408 /// 0b1: Re-initializes the timer counter and generates an update of the registers.
409 pub const Update: u32 = 0b1;
410 }
411 /// Read-write values (empty)
412 pub mod RW {}
413 }
414}
415
416/// CCMR1_Output and CCMR1_Input
417/// CCMR1_Output: capture/compare mode register (output mode)
418/// CCMR1_Input: capture/compare mode register 1 (input mode)
419pub mod CCMR1 {
420
421 /// Output Compare 2 mode
422 pub mod OC2M {
423 /// Offset (12 bits)
424 pub const offset: u32 = 12;
425 /// Mask (3 bits: 0b111 << 12)
426 pub const mask: u32 = 0b111 << offset;
427 /// Read-only values (empty)
428 pub mod R {}
429 /// Write-only values (empty)
430 pub mod W {}
431 /// Read-write values
432 pub mod RW {
433
434 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
435 pub const Frozen: u32 = 0b000;
436
437 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
438 pub const ActiveOnMatch: u32 = 0b001;
439
440 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
441 pub const InactiveOnMatch: u32 = 0b010;
442
443 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy
444 pub const Toggle: u32 = 0b011;
445
446 /// 0b100: OCyREF is forced low
447 pub const ForceInactive: u32 = 0b100;
448
449 /// 0b101: OCyREF is forced high
450 pub const ForceActive: u32 = 0b101;
451
452 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
453 pub const PwmMode1: u32 = 0b110;
454
455 /// 0b111: Inversely to PwmMode1
456 pub const PwmMode2: u32 = 0b111;
457 }
458 }
459
460 /// Output Compare 2 preload enable
461 pub mod OC2PE {
462 /// Offset (11 bits)
463 pub const offset: u32 = 11;
464 /// Mask (1 bit: 1 << 11)
465 pub const mask: u32 = 1 << offset;
466 /// Read-only values (empty)
467 pub mod R {}
468 /// Write-only values (empty)
469 pub mod W {}
470 /// Read-write values (empty)
471 pub mod RW {}
472 }
473
474 /// Output Compare 2 fast enable
475 pub mod OC2FE {
476 /// Offset (10 bits)
477 pub const offset: u32 = 10;
478 /// Mask (1 bit: 1 << 10)
479 pub const mask: u32 = 1 << offset;
480 /// Read-only values (empty)
481 pub mod R {}
482 /// Write-only values (empty)
483 pub mod W {}
484 /// Read-write values (empty)
485 pub mod RW {}
486 }
487
488 /// Capture/Compare 2 selection
489 pub mod CC2S {
490 /// Offset (8 bits)
491 pub const offset: u32 = 8;
492 /// Mask (2 bits: 0b11 << 8)
493 pub const mask: u32 = 0b11 << offset;
494 /// Read-only values (empty)
495 pub mod R {}
496 /// Write-only values (empty)
497 pub mod W {}
498 /// Read-write values (empty)
499 pub mod RW {}
500 }
501
502 /// Output Compare 1 mode
503 pub mod OC1M {
504 /// Offset (4 bits)
505 pub const offset: u32 = 4;
506 /// Mask (3 bits: 0b111 << 4)
507 pub const mask: u32 = 0b111 << offset;
508 /// Read-only values (empty)
509 pub mod R {}
510 /// Write-only values (empty)
511 pub mod W {}
512 pub use super::OC2M::RW;
513 }
514
515 /// Output Compare 1 preload enable
516 pub mod OC1PE {
517 /// Offset (3 bits)
518 pub const offset: u32 = 3;
519 /// Mask (1 bit: 1 << 3)
520 pub const mask: u32 = 1 << offset;
521 /// Read-only values (empty)
522 pub mod R {}
523 /// Write-only values (empty)
524 pub mod W {}
525 /// Read-write values (empty)
526 pub mod RW {}
527 }
528
529 /// Output Compare 1 fast enable
530 pub mod OC1FE {
531 /// Offset (2 bits)
532 pub const offset: u32 = 2;
533 /// Mask (1 bit: 1 << 2)
534 pub const mask: u32 = 1 << offset;
535 /// Read-only values (empty)
536 pub mod R {}
537 /// Write-only values (empty)
538 pub mod W {}
539 /// Read-write values (empty)
540 pub mod RW {}
541 }
542
543 /// Capture/Compare 1 selection
544 pub mod CC1S {
545 /// Offset (0 bits)
546 pub const offset: u32 = 0;
547 /// Mask (2 bits: 0b11 << 0)
548 pub const mask: u32 = 0b11 << offset;
549 /// Read-only values (empty)
550 pub mod R {}
551 /// Write-only values (empty)
552 pub mod W {}
553 /// Read-write values (empty)
554 pub mod RW {}
555 }
556
557 /// Input capture 2 filter
558 pub mod IC2F {
559 /// Offset (12 bits)
560 pub const offset: u32 = 12;
561 /// Mask (4 bits: 0b1111 << 12)
562 pub const mask: u32 = 0b1111 << offset;
563 /// Read-only values (empty)
564 pub mod R {}
565 /// Write-only values (empty)
566 pub mod W {}
567 /// Read-write values (empty)
568 pub mod RW {}
569 }
570
571 /// Input capture 2 prescaler
572 pub mod IC2PSC {
573 /// Offset (10 bits)
574 pub const offset: u32 = 10;
575 /// Mask (2 bits: 0b11 << 10)
576 pub const mask: u32 = 0b11 << offset;
577 /// Read-only values (empty)
578 pub mod R {}
579 /// Write-only values (empty)
580 pub mod W {}
581 /// Read-write values (empty)
582 pub mod RW {}
583 }
584
585 /// Input capture 1 filter
586 pub mod IC1F {
587 /// Offset (4 bits)
588 pub const offset: u32 = 4;
589 /// Mask (3 bits: 0b111 << 4)
590 pub const mask: u32 = 0b111 << offset;
591 /// Read-only values (empty)
592 pub mod R {}
593 /// Write-only values (empty)
594 pub mod W {}
595 /// Read-write values (empty)
596 pub mod RW {}
597 }
598
599 /// Input capture 1 prescaler
600 pub mod IC1PSC {
601 /// Offset (2 bits)
602 pub const offset: u32 = 2;
603 /// Mask (2 bits: 0b11 << 2)
604 pub const mask: u32 = 0b11 << offset;
605 /// Read-only values (empty)
606 pub mod R {}
607 /// Write-only values (empty)
608 pub mod W {}
609 /// Read-write values (empty)
610 pub mod RW {}
611 }
612}
613
614/// capture/compare enable register
615pub mod CCER {
616
617 /// Capture/Compare 2 output Polarity
618 pub mod CC2NP {
619 /// Offset (7 bits)
620 pub const offset: u32 = 7;
621 /// Mask (1 bit: 1 << 7)
622 pub const mask: u32 = 1 << offset;
623 /// Read-only values (empty)
624 pub mod R {}
625 /// Write-only values (empty)
626 pub mod W {}
627 /// Read-write values (empty)
628 pub mod RW {}
629 }
630
631 /// Capture/Compare 2 output Polarity
632 pub mod CC2P {
633 /// Offset (5 bits)
634 pub const offset: u32 = 5;
635 /// Mask (1 bit: 1 << 5)
636 pub const mask: u32 = 1 << offset;
637 /// Read-only values (empty)
638 pub mod R {}
639 /// Write-only values (empty)
640 pub mod W {}
641 /// Read-write values (empty)
642 pub mod RW {}
643 }
644
645 /// Capture/Compare 2 output enable
646 pub mod CC2E {
647 /// Offset (4 bits)
648 pub const offset: u32 = 4;
649 /// Mask (1 bit: 1 << 4)
650 pub const mask: u32 = 1 << offset;
651 /// Read-only values (empty)
652 pub mod R {}
653 /// Write-only values (empty)
654 pub mod W {}
655 /// Read-write values (empty)
656 pub mod RW {}
657 }
658
659 /// Capture/Compare 1 output Polarity
660 pub mod CC1NP {
661 /// Offset (3 bits)
662 pub const offset: u32 = 3;
663 /// Mask (1 bit: 1 << 3)
664 pub const mask: u32 = 1 << offset;
665 /// Read-only values (empty)
666 pub mod R {}
667 /// Write-only values (empty)
668 pub mod W {}
669 /// Read-write values (empty)
670 pub mod RW {}
671 }
672
673 /// Capture/Compare 1 output Polarity
674 pub mod CC1P {
675 /// Offset (1 bits)
676 pub const offset: u32 = 1;
677 /// Mask (1 bit: 1 << 1)
678 pub const mask: u32 = 1 << offset;
679 /// Read-only values (empty)
680 pub mod R {}
681 /// Write-only values (empty)
682 pub mod W {}
683 /// Read-write values (empty)
684 pub mod RW {}
685 }
686
687 /// Capture/Compare 1 output enable
688 pub mod CC1E {
689 /// Offset (0 bits)
690 pub const offset: u32 = 0;
691 /// Mask (1 bit: 1 << 0)
692 pub const mask: u32 = 1 << offset;
693 /// Read-only values (empty)
694 pub mod R {}
695 /// Write-only values (empty)
696 pub mod W {}
697 /// Read-write values (empty)
698 pub mod RW {}
699 }
700}
701
702/// counter
703pub mod CNT {
704
705 /// counter value
706 pub mod CNT {
707 /// Offset (0 bits)
708 pub const offset: u32 = 0;
709 /// Mask (16 bits: 0xffff << 0)
710 pub const mask: u32 = 0xffff << offset;
711 /// Read-only values (empty)
712 pub mod R {}
713 /// Write-only values (empty)
714 pub mod W {}
715 /// Read-write values (empty)
716 pub mod RW {}
717 }
718}
719
720/// prescaler
721pub mod PSC {
722
723 /// Prescaler value
724 pub mod PSC {
725 /// Offset (0 bits)
726 pub const offset: u32 = 0;
727 /// Mask (16 bits: 0xffff << 0)
728 pub const mask: u32 = 0xffff << offset;
729 /// Read-only values (empty)
730 pub mod R {}
731 /// Write-only values (empty)
732 pub mod W {}
733 /// Read-write values (empty)
734 pub mod RW {}
735 }
736}
737
738/// auto-reload register
739pub mod ARR {
740
741 /// Auto-reload value
742 pub mod ARR {
743 /// Offset (0 bits)
744 pub const offset: u32 = 0;
745 /// Mask (16 bits: 0xffff << 0)
746 pub const mask: u32 = 0xffff << offset;
747 /// Read-only values (empty)
748 pub mod R {}
749 /// Write-only values (empty)
750 pub mod W {}
751 /// Read-write values (empty)
752 pub mod RW {}
753 }
754}
755
756/// capture/compare register
757pub mod CCR1 {
758
759 /// Capture/Compare value
760 pub mod CCR {
761 /// Offset (0 bits)
762 pub const offset: u32 = 0;
763 /// Mask (16 bits: 0xffff << 0)
764 pub const mask: u32 = 0xffff << offset;
765 /// Read-only values (empty)
766 pub mod R {}
767 /// Write-only values (empty)
768 pub mod W {}
769 /// Read-write values (empty)
770 pub mod RW {}
771 }
772}
773
774/// capture/compare register
775pub mod CCR2 {
776 pub use super::CCR1::CCR;
777}
778#[repr(C)]
779pub struct RegisterBlock {
780 /// control register 1
781 pub CR1: RWRegister<u32>,
782
783 _reserved1: [u8; 4],
784
785 /// slave mode control register
786 pub SMCR: RWRegister<u32>,
787
788 /// DMA/Interrupt enable register
789 pub DIER: RWRegister<u32>,
790
791 /// status register
792 pub SR: RWRegister<u32>,
793
794 /// event generation register
795 pub EGR: WORegister<u32>,
796
797 /// CCMR1_Output and CCMR1_Input
798 /// CCMR1_Output: capture/compare mode register (output mode)
799 /// CCMR1_Input: capture/compare mode register 1 (input mode)
800 pub CCMR1: RWRegister<u32>,
801
802 _reserved2: [u8; 4],
803
804 /// capture/compare enable register
805 pub CCER: RWRegister<u32>,
806
807 /// counter
808 pub CNT: RWRegister<u32>,
809
810 /// prescaler
811 pub PSC: RWRegister<u32>,
812
813 /// auto-reload register
814 pub ARR: RWRegister<u32>,
815
816 _reserved3: [u8; 4],
817
818 /// capture/compare register
819 pub CCR1: RWRegister<u32>,
820
821 /// capture/compare register
822 pub CCR2: RWRegister<u32>,
823}
824pub struct ResetValues {
825 pub CR1: u32,
826 pub SMCR: u32,
827 pub DIER: u32,
828 pub SR: u32,
829 pub EGR: u32,
830 pub CCMR1: u32,
831 pub CCER: u32,
832 pub CNT: u32,
833 pub PSC: u32,
834 pub ARR: u32,
835 pub CCR1: u32,
836 pub CCR2: u32,
837}
838#[cfg(not(feature = "nosync"))]
839pub struct Instance {
840 pub(crate) addr: u32,
841 pub(crate) _marker: PhantomData<*const RegisterBlock>,
842}
843#[cfg(not(feature = "nosync"))]
844impl ::core::ops::Deref for Instance {
845 type Target = RegisterBlock;
846 #[inline(always)]
847 fn deref(&self) -> &RegisterBlock {
848 unsafe { &*(self.addr as *const _) }
849 }
850}
851#[cfg(feature = "rtic")]
852unsafe impl Send for Instance {}