stm32ral/stm32f4/peripherals/tim5.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! General-purpose-timers
4//!
5//! Used by: stm32f401, stm32f405, stm32f407, stm32f411, stm32f412, stm32f413, stm32f427, stm32f429, stm32f446, stm32f469
6
7use crate::{RWRegister, WORegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// control register 1
12pub mod CR1 {
13
14 /// Clock division
15 pub mod CKD {
16 /// Offset (8 bits)
17 pub const offset: u32 = 8;
18 /// Mask (2 bits: 0b11 << 8)
19 pub const mask: u32 = 0b11 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values
25 pub mod RW {
26
27 /// 0b00: t_DTS = t_CK_INT
28 pub const Div1: u32 = 0b00;
29
30 /// 0b01: t_DTS = 2 × t_CK_INT
31 pub const Div2: u32 = 0b01;
32
33 /// 0b10: t_DTS = 4 × t_CK_INT
34 pub const Div4: u32 = 0b10;
35 }
36 }
37
38 /// Auto-reload preload enable
39 pub mod ARPE {
40 /// Offset (7 bits)
41 pub const offset: u32 = 7;
42 /// Mask (1 bit: 1 << 7)
43 pub const mask: u32 = 1 << offset;
44 /// Read-only values (empty)
45 pub mod R {}
46 /// Write-only values (empty)
47 pub mod W {}
48 /// Read-write values
49 pub mod RW {
50
51 /// 0b0: TIMx_APRR register is not buffered
52 pub const Disabled: u32 = 0b0;
53
54 /// 0b1: TIMx_APRR register is buffered
55 pub const Enabled: u32 = 0b1;
56 }
57 }
58
59 /// Center-aligned mode selection
60 pub mod CMS {
61 /// Offset (5 bits)
62 pub const offset: u32 = 5;
63 /// Mask (2 bits: 0b11 << 5)
64 pub const mask: u32 = 0b11 << offset;
65 /// Read-only values (empty)
66 pub mod R {}
67 /// Write-only values (empty)
68 pub mod W {}
69 /// Read-write values
70 pub mod RW {
71
72 /// 0b00: The counter counts up or down depending on the direction bit
73 pub const EdgeAligned: u32 = 0b00;
74
75 /// 0b01: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
76 pub const CenterAligned1: u32 = 0b01;
77
78 /// 0b10: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
79 pub const CenterAligned2: u32 = 0b10;
80
81 /// 0b11: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
82 pub const CenterAligned3: u32 = 0b11;
83 }
84 }
85
86 /// Direction
87 pub mod DIR {
88 /// Offset (4 bits)
89 pub const offset: u32 = 4;
90 /// Mask (1 bit: 1 << 4)
91 pub const mask: u32 = 1 << offset;
92 /// Read-only values (empty)
93 pub mod R {}
94 /// Write-only values (empty)
95 pub mod W {}
96 /// Read-write values
97 pub mod RW {
98
99 /// 0b0: Counter used as upcounter
100 pub const Up: u32 = 0b0;
101
102 /// 0b1: Counter used as downcounter
103 pub const Down: u32 = 0b1;
104 }
105 }
106
107 /// One-pulse mode
108 pub mod OPM {
109 /// Offset (3 bits)
110 pub const offset: u32 = 3;
111 /// Mask (1 bit: 1 << 3)
112 pub const mask: u32 = 1 << offset;
113 /// Read-only values (empty)
114 pub mod R {}
115 /// Write-only values (empty)
116 pub mod W {}
117 /// Read-write values
118 pub mod RW {
119
120 /// 0b0: Counter is not stopped at update event
121 pub const Disabled: u32 = 0b0;
122
123 /// 0b1: Counter stops counting at the next update event (clearing the CEN bit)
124 pub const Enabled: u32 = 0b1;
125 }
126 }
127
128 /// Update request source
129 pub mod URS {
130 /// Offset (2 bits)
131 pub const offset: u32 = 2;
132 /// Mask (1 bit: 1 << 2)
133 pub const mask: u32 = 1 << offset;
134 /// Read-only values (empty)
135 pub mod R {}
136 /// Write-only values (empty)
137 pub mod W {}
138 /// Read-write values
139 pub mod RW {
140
141 /// 0b0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
142 pub const AnyEvent: u32 = 0b0;
143
144 /// 0b1: Only counter overflow/underflow generates an update interrupt or DMA request
145 pub const CounterOnly: u32 = 0b1;
146 }
147 }
148
149 /// Update disable
150 pub mod UDIS {
151 /// Offset (1 bits)
152 pub const offset: u32 = 1;
153 /// Mask (1 bit: 1 << 1)
154 pub const mask: u32 = 1 << offset;
155 /// Read-only values (empty)
156 pub mod R {}
157 /// Write-only values (empty)
158 pub mod W {}
159 /// Read-write values
160 pub mod RW {
161
162 /// 0b0: Update event enabled
163 pub const Enabled: u32 = 0b0;
164
165 /// 0b1: Update event disabled
166 pub const Disabled: u32 = 0b1;
167 }
168 }
169
170 /// Counter enable
171 pub mod CEN {
172 /// Offset (0 bits)
173 pub const offset: u32 = 0;
174 /// Mask (1 bit: 1 << 0)
175 pub const mask: u32 = 1 << offset;
176 /// Read-only values (empty)
177 pub mod R {}
178 /// Write-only values (empty)
179 pub mod W {}
180 /// Read-write values
181 pub mod RW {
182
183 /// 0b0: Counter disabled
184 pub const Disabled: u32 = 0b0;
185
186 /// 0b1: Counter enabled
187 pub const Enabled: u32 = 0b1;
188 }
189 }
190}
191
192/// control register 2
193pub mod CR2 {
194
195 /// TI1 selection
196 pub mod TI1S {
197 /// Offset (7 bits)
198 pub const offset: u32 = 7;
199 /// Mask (1 bit: 1 << 7)
200 pub const mask: u32 = 1 << offset;
201 /// Read-only values (empty)
202 pub mod R {}
203 /// Write-only values (empty)
204 pub mod W {}
205 /// Read-write values
206 pub mod RW {
207
208 /// 0b0: The TIMx_CH1 pin is connected to TI1 input
209 pub const Normal: u32 = 0b0;
210
211 /// 0b1: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
212 pub const XOR: u32 = 0b1;
213 }
214 }
215
216 /// Master mode selection
217 pub mod MMS {
218 /// Offset (4 bits)
219 pub const offset: u32 = 4;
220 /// Mask (3 bits: 0b111 << 4)
221 pub const mask: u32 = 0b111 << offset;
222 /// Read-only values (empty)
223 pub mod R {}
224 /// Write-only values (empty)
225 pub mod W {}
226 /// Read-write values
227 pub mod RW {
228
229 /// 0b000: The UG bit from the TIMx_EGR register is used as trigger output
230 pub const Reset: u32 = 0b000;
231
232 /// 0b001: The counter enable signal, CNT_EN, is used as trigger output
233 pub const Enable: u32 = 0b001;
234
235 /// 0b010: The update event is selected as trigger output
236 pub const Update: u32 = 0b010;
237
238 /// 0b011: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
239 pub const ComparePulse: u32 = 0b011;
240
241 /// 0b100: OC1REF signal is used as trigger output
242 pub const CompareOC1: u32 = 0b100;
243
244 /// 0b101: OC2REF signal is used as trigger output
245 pub const CompareOC2: u32 = 0b101;
246
247 /// 0b110: OC3REF signal is used as trigger output
248 pub const CompareOC3: u32 = 0b110;
249
250 /// 0b111: OC4REF signal is used as trigger output
251 pub const CompareOC4: u32 = 0b111;
252 }
253 }
254
255 /// Capture/compare DMA selection
256 pub mod CCDS {
257 /// Offset (3 bits)
258 pub const offset: u32 = 3;
259 /// Mask (1 bit: 1 << 3)
260 pub const mask: u32 = 1 << offset;
261 /// Read-only values (empty)
262 pub mod R {}
263 /// Write-only values (empty)
264 pub mod W {}
265 /// Read-write values
266 pub mod RW {
267
268 /// 0b0: CCx DMA request sent when CCx event occurs
269 pub const OnCompare: u32 = 0b0;
270
271 /// 0b1: CCx DMA request sent when update event occurs
272 pub const OnUpdate: u32 = 0b1;
273 }
274 }
275}
276
277/// slave mode control register
278pub mod SMCR {
279
280 /// External trigger polarity
281 pub mod ETP {
282 /// Offset (15 bits)
283 pub const offset: u32 = 15;
284 /// Mask (1 bit: 1 << 15)
285 pub const mask: u32 = 1 << offset;
286 /// Read-only values (empty)
287 pub mod R {}
288 /// Write-only values (empty)
289 pub mod W {}
290 /// Read-write values
291 pub mod RW {
292
293 /// 0b0: ETR is noninverted, active at high level or rising edge
294 pub const NotInverted: u32 = 0b0;
295
296 /// 0b1: ETR is inverted, active at low level or falling edge
297 pub const Inverted: u32 = 0b1;
298 }
299 }
300
301 /// External clock enable
302 pub mod ECE {
303 /// Offset (14 bits)
304 pub const offset: u32 = 14;
305 /// Mask (1 bit: 1 << 14)
306 pub const mask: u32 = 1 << offset;
307 /// Read-only values (empty)
308 pub mod R {}
309 /// Write-only values (empty)
310 pub mod W {}
311 /// Read-write values
312 pub mod RW {
313
314 /// 0b0: External clock mode 2 disabled
315 pub const Disabled: u32 = 0b0;
316
317 /// 0b1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
318 pub const Enabled: u32 = 0b1;
319 }
320 }
321
322 /// External trigger prescaler
323 pub mod ETPS {
324 /// Offset (12 bits)
325 pub const offset: u32 = 12;
326 /// Mask (2 bits: 0b11 << 12)
327 pub const mask: u32 = 0b11 << offset;
328 /// Read-only values (empty)
329 pub mod R {}
330 /// Write-only values (empty)
331 pub mod W {}
332 /// Read-write values
333 pub mod RW {
334
335 /// 0b00: Prescaler OFF
336 pub const Div1: u32 = 0b00;
337
338 /// 0b01: ETRP frequency divided by 2
339 pub const Div2: u32 = 0b01;
340
341 /// 0b10: ETRP frequency divided by 4
342 pub const Div4: u32 = 0b10;
343
344 /// 0b11: ETRP frequency divided by 8
345 pub const Div8: u32 = 0b11;
346 }
347 }
348
349 /// External trigger filter
350 pub mod ETF {
351 /// Offset (8 bits)
352 pub const offset: u32 = 8;
353 /// Mask (4 bits: 0b1111 << 8)
354 pub const mask: u32 = 0b1111 << offset;
355 /// Read-only values (empty)
356 pub mod R {}
357 /// Write-only values (empty)
358 pub mod W {}
359 /// Read-write values
360 pub mod RW {
361
362 /// 0b0000: No filter, sampling is done at fDTS
363 pub const NoFilter: u32 = 0b0000;
364
365 /// 0b0001: fSAMPLING=fCK_INT, N=2
366 pub const FCK_INT_N2: u32 = 0b0001;
367
368 /// 0b0010: fSAMPLING=fCK_INT, N=4
369 pub const FCK_INT_N4: u32 = 0b0010;
370
371 /// 0b0011: fSAMPLING=fCK_INT, N=8
372 pub const FCK_INT_N8: u32 = 0b0011;
373
374 /// 0b0100: fSAMPLING=fDTS/2, N=6
375 pub const FDTS_Div2_N6: u32 = 0b0100;
376
377 /// 0b0101: fSAMPLING=fDTS/2, N=8
378 pub const FDTS_Div2_N8: u32 = 0b0101;
379
380 /// 0b0110: fSAMPLING=fDTS/4, N=6
381 pub const FDTS_Div4_N6: u32 = 0b0110;
382
383 /// 0b0111: fSAMPLING=fDTS/4, N=8
384 pub const FDTS_Div4_N8: u32 = 0b0111;
385
386 /// 0b1000: fSAMPLING=fDTS/8, N=6
387 pub const FDTS_Div8_N6: u32 = 0b1000;
388
389 /// 0b1001: fSAMPLING=fDTS/8, N=8
390 pub const FDTS_Div8_N8: u32 = 0b1001;
391
392 /// 0b1010: fSAMPLING=fDTS/16, N=5
393 pub const FDTS_Div16_N5: u32 = 0b1010;
394
395 /// 0b1011: fSAMPLING=fDTS/16, N=6
396 pub const FDTS_Div16_N6: u32 = 0b1011;
397
398 /// 0b1100: fSAMPLING=fDTS/16, N=8
399 pub const FDTS_Div16_N8: u32 = 0b1100;
400
401 /// 0b1101: fSAMPLING=fDTS/32, N=5
402 pub const FDTS_Div32_N5: u32 = 0b1101;
403
404 /// 0b1110: fSAMPLING=fDTS/32, N=6
405 pub const FDTS_Div32_N6: u32 = 0b1110;
406
407 /// 0b1111: fSAMPLING=fDTS/32, N=8
408 pub const FDTS_Div32_N8: u32 = 0b1111;
409 }
410 }
411
412 /// Master/Slave mode
413 pub mod MSM {
414 /// Offset (7 bits)
415 pub const offset: u32 = 7;
416 /// Mask (1 bit: 1 << 7)
417 pub const mask: u32 = 1 << offset;
418 /// Read-only values (empty)
419 pub mod R {}
420 /// Write-only values (empty)
421 pub mod W {}
422 /// Read-write values
423 pub mod RW {
424
425 /// 0b0: No action
426 pub const NoSync: u32 = 0b0;
427
428 /// 0b1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
429 pub const Sync: u32 = 0b1;
430 }
431 }
432
433 /// Trigger selection
434 pub mod TS {
435 /// Offset (4 bits)
436 pub const offset: u32 = 4;
437 /// Mask (3 bits: 0b111 << 4)
438 pub const mask: u32 = 0b111 << offset;
439 /// Read-only values (empty)
440 pub mod R {}
441 /// Write-only values (empty)
442 pub mod W {}
443 /// Read-write values
444 pub mod RW {
445
446 /// 0b000: Internal Trigger 0 (ITR0)
447 pub const ITR0: u32 = 0b000;
448
449 /// 0b001: Internal Trigger 1 (ITR1)
450 pub const ITR1: u32 = 0b001;
451
452 /// 0b010: Internal Trigger 2 (ITR2)
453 pub const ITR2: u32 = 0b010;
454
455 /// 0b100: TI1 Edge Detector (TI1F_ED)
456 pub const TI1F_ED: u32 = 0b100;
457
458 /// 0b101: Filtered Timer Input 1 (TI1FP1)
459 pub const TI1FP1: u32 = 0b101;
460
461 /// 0b110: Filtered Timer Input 2 (TI2FP2)
462 pub const TI2FP2: u32 = 0b110;
463
464 /// 0b111: External Trigger input (ETRF)
465 pub const ETRF: u32 = 0b111;
466 }
467 }
468
469 /// Slave mode selection
470 pub mod SMS {
471 /// Offset (0 bits)
472 pub const offset: u32 = 0;
473 /// Mask (3 bits: 0b111 << 0)
474 pub const mask: u32 = 0b111 << offset;
475 /// Read-only values (empty)
476 pub mod R {}
477 /// Write-only values (empty)
478 pub mod W {}
479 /// Read-write values
480 pub mod RW {
481
482 /// 0b000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
483 pub const Disabled: u32 = 0b000;
484
485 /// 0b001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
486 pub const Encoder_Mode_1: u32 = 0b001;
487
488 /// 0b010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
489 pub const Encoder_Mode_2: u32 = 0b010;
490
491 /// 0b011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
492 pub const Encoder_Mode_3: u32 = 0b011;
493
494 /// 0b100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
495 pub const Reset_Mode: u32 = 0b100;
496
497 /// 0b101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
498 pub const Gated_Mode: u32 = 0b101;
499
500 /// 0b110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
501 pub const Trigger_Mode: u32 = 0b110;
502
503 /// 0b111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
504 pub const Ext_Clock_Mode: u32 = 0b111;
505 }
506 }
507}
508
509/// DMA/Interrupt enable register
510pub mod DIER {
511
512 /// Trigger DMA request enable
513 pub mod TDE {
514 /// Offset (14 bits)
515 pub const offset: u32 = 14;
516 /// Mask (1 bit: 1 << 14)
517 pub const mask: u32 = 1 << offset;
518 /// Read-only values (empty)
519 pub mod R {}
520 /// Write-only values (empty)
521 pub mod W {}
522 /// Read-write values
523 pub mod RW {
524
525 /// 0b0: Trigger DMA request disabled
526 pub const Disabled: u32 = 0b0;
527
528 /// 0b1: Trigger DMA request enabled
529 pub const Enabled: u32 = 0b1;
530 }
531 }
532
533 /// Capture/Compare 4 DMA request enable
534 pub mod CC4DE {
535 /// Offset (12 bits)
536 pub const offset: u32 = 12;
537 /// Mask (1 bit: 1 << 12)
538 pub const mask: u32 = 1 << offset;
539 /// Read-only values (empty)
540 pub mod R {}
541 /// Write-only values (empty)
542 pub mod W {}
543 /// Read-write values
544 pub mod RW {
545
546 /// 0b0: CCx DMA request disabled
547 pub const Disabled: u32 = 0b0;
548
549 /// 0b1: CCx DMA request enabled
550 pub const Enabled: u32 = 0b1;
551 }
552 }
553
554 /// Capture/Compare 3 DMA request enable
555 pub mod CC3DE {
556 /// Offset (11 bits)
557 pub const offset: u32 = 11;
558 /// Mask (1 bit: 1 << 11)
559 pub const mask: u32 = 1 << offset;
560 /// Read-only values (empty)
561 pub mod R {}
562 /// Write-only values (empty)
563 pub mod W {}
564 pub use super::CC4DE::RW;
565 }
566
567 /// Capture/Compare 2 DMA request enable
568 pub mod CC2DE {
569 /// Offset (10 bits)
570 pub const offset: u32 = 10;
571 /// Mask (1 bit: 1 << 10)
572 pub const mask: u32 = 1 << offset;
573 /// Read-only values (empty)
574 pub mod R {}
575 /// Write-only values (empty)
576 pub mod W {}
577 pub use super::CC4DE::RW;
578 }
579
580 /// Capture/Compare 1 DMA request enable
581 pub mod CC1DE {
582 /// Offset (9 bits)
583 pub const offset: u32 = 9;
584 /// Mask (1 bit: 1 << 9)
585 pub const mask: u32 = 1 << offset;
586 /// Read-only values (empty)
587 pub mod R {}
588 /// Write-only values (empty)
589 pub mod W {}
590 pub use super::CC4DE::RW;
591 }
592
593 /// Update DMA request enable
594 pub mod UDE {
595 /// Offset (8 bits)
596 pub const offset: u32 = 8;
597 /// Mask (1 bit: 1 << 8)
598 pub const mask: u32 = 1 << offset;
599 /// Read-only values (empty)
600 pub mod R {}
601 /// Write-only values (empty)
602 pub mod W {}
603 /// Read-write values
604 pub mod RW {
605
606 /// 0b0: Update DMA request disabled
607 pub const Disabled: u32 = 0b0;
608
609 /// 0b1: Update DMA request enabled
610 pub const Enabled: u32 = 0b1;
611 }
612 }
613
614 /// Trigger interrupt enable
615 pub mod TIE {
616 /// Offset (6 bits)
617 pub const offset: u32 = 6;
618 /// Mask (1 bit: 1 << 6)
619 pub const mask: u32 = 1 << offset;
620 /// Read-only values (empty)
621 pub mod R {}
622 /// Write-only values (empty)
623 pub mod W {}
624 /// Read-write values
625 pub mod RW {
626
627 /// 0b0: Trigger interrupt disabled
628 pub const Disabled: u32 = 0b0;
629
630 /// 0b1: Trigger interrupt enabled
631 pub const Enabled: u32 = 0b1;
632 }
633 }
634
635 /// Capture/Compare 4 interrupt enable
636 pub mod CC4IE {
637 /// Offset (4 bits)
638 pub const offset: u32 = 4;
639 /// Mask (1 bit: 1 << 4)
640 pub const mask: u32 = 1 << offset;
641 /// Read-only values (empty)
642 pub mod R {}
643 /// Write-only values (empty)
644 pub mod W {}
645 /// Read-write values
646 pub mod RW {
647
648 /// 0b0: CCx interrupt disabled
649 pub const Disabled: u32 = 0b0;
650
651 /// 0b1: CCx interrupt enabled
652 pub const Enabled: u32 = 0b1;
653 }
654 }
655
656 /// Capture/Compare 3 interrupt enable
657 pub mod CC3IE {
658 /// Offset (3 bits)
659 pub const offset: u32 = 3;
660 /// Mask (1 bit: 1 << 3)
661 pub const mask: u32 = 1 << offset;
662 /// Read-only values (empty)
663 pub mod R {}
664 /// Write-only values (empty)
665 pub mod W {}
666 pub use super::CC4IE::RW;
667 }
668
669 /// Capture/Compare 2 interrupt enable
670 pub mod CC2IE {
671 /// Offset (2 bits)
672 pub const offset: u32 = 2;
673 /// Mask (1 bit: 1 << 2)
674 pub const mask: u32 = 1 << offset;
675 /// Read-only values (empty)
676 pub mod R {}
677 /// Write-only values (empty)
678 pub mod W {}
679 pub use super::CC4IE::RW;
680 }
681
682 /// Capture/Compare 1 interrupt enable
683 pub mod CC1IE {
684 /// Offset (1 bits)
685 pub const offset: u32 = 1;
686 /// Mask (1 bit: 1 << 1)
687 pub const mask: u32 = 1 << offset;
688 /// Read-only values (empty)
689 pub mod R {}
690 /// Write-only values (empty)
691 pub mod W {}
692 pub use super::CC4IE::RW;
693 }
694
695 /// Update interrupt enable
696 pub mod UIE {
697 /// Offset (0 bits)
698 pub const offset: u32 = 0;
699 /// Mask (1 bit: 1 << 0)
700 pub const mask: u32 = 1 << offset;
701 /// Read-only values (empty)
702 pub mod R {}
703 /// Write-only values (empty)
704 pub mod W {}
705 /// Read-write values
706 pub mod RW {
707
708 /// 0b0: Update interrupt disabled
709 pub const Disabled: u32 = 0b0;
710
711 /// 0b1: Update interrupt enabled
712 pub const Enabled: u32 = 0b1;
713 }
714 }
715}
716
717/// status register
718pub mod SR {
719
720 /// Capture/Compare 4 overcapture flag
721 pub mod CC4OF {
722 /// Offset (12 bits)
723 pub const offset: u32 = 12;
724 /// Mask (1 bit: 1 << 12)
725 pub const mask: u32 = 1 << offset;
726 /// Read-only values
727 pub mod R {
728
729 /// 0b1: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
730 pub const Overcapture: u32 = 0b1;
731 }
732 /// Write-only values
733 pub mod W {
734
735 /// 0b0: Clear flag
736 pub const Clear: u32 = 0b0;
737 }
738 /// Read-write values (empty)
739 pub mod RW {}
740 }
741
742 /// Capture/Compare 3 overcapture flag
743 pub mod CC3OF {
744 /// Offset (11 bits)
745 pub const offset: u32 = 11;
746 /// Mask (1 bit: 1 << 11)
747 pub const mask: u32 = 1 << offset;
748 pub use super::CC4OF::R;
749 pub use super::CC4OF::W;
750 /// Read-write values (empty)
751 pub mod RW {}
752 }
753
754 /// Capture/compare 2 overcapture flag
755 pub mod CC2OF {
756 /// Offset (10 bits)
757 pub const offset: u32 = 10;
758 /// Mask (1 bit: 1 << 10)
759 pub const mask: u32 = 1 << offset;
760 pub use super::CC4OF::R;
761 pub use super::CC4OF::W;
762 /// Read-write values (empty)
763 pub mod RW {}
764 }
765
766 /// Capture/Compare 1 overcapture flag
767 pub mod CC1OF {
768 /// Offset (9 bits)
769 pub const offset: u32 = 9;
770 /// Mask (1 bit: 1 << 9)
771 pub const mask: u32 = 1 << offset;
772 pub use super::CC4OF::R;
773 pub use super::CC4OF::W;
774 /// Read-write values (empty)
775 pub mod RW {}
776 }
777
778 /// Trigger interrupt flag
779 pub mod TIF {
780 /// Offset (6 bits)
781 pub const offset: u32 = 6;
782 /// Mask (1 bit: 1 << 6)
783 pub const mask: u32 = 1 << offset;
784 /// Read-only values
785 pub mod R {
786
787 /// 0b0: No trigger event occurred
788 pub const NoTrigger: u32 = 0b0;
789
790 /// 0b1: Trigger interrupt pending
791 pub const Trigger: u32 = 0b1;
792 }
793 pub use super::CC4OF::W;
794 /// Read-write values (empty)
795 pub mod RW {}
796 }
797
798 /// Capture/Compare 4 interrupt flag
799 pub mod CC4IF {
800 /// Offset (4 bits)
801 pub const offset: u32 = 4;
802 /// Mask (1 bit: 1 << 4)
803 pub const mask: u32 = 1 << offset;
804 /// Read-only values
805 pub mod R {
806
807 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
808 pub const Match: u32 = 0b1;
809 }
810 pub use super::CC4OF::W;
811 /// Read-write values (empty)
812 pub mod RW {}
813 }
814
815 /// Capture/Compare 3 interrupt flag
816 pub mod CC3IF {
817 /// Offset (3 bits)
818 pub const offset: u32 = 3;
819 /// Mask (1 bit: 1 << 3)
820 pub const mask: u32 = 1 << offset;
821 /// Read-only values
822 pub mod R {
823
824 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
825 pub const Match: u32 = 0b1;
826 }
827 pub use super::CC4OF::W;
828 /// Read-write values (empty)
829 pub mod RW {}
830 }
831
832 /// Capture/Compare 2 interrupt flag
833 pub mod CC2IF {
834 /// Offset (2 bits)
835 pub const offset: u32 = 2;
836 /// Mask (1 bit: 1 << 2)
837 pub const mask: u32 = 1 << offset;
838 /// Read-only values
839 pub mod R {
840
841 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
842 pub const Match: u32 = 0b1;
843 }
844 pub use super::CC4OF::W;
845 /// Read-write values (empty)
846 pub mod RW {}
847 }
848
849 /// Capture/compare 1 interrupt flag
850 pub mod CC1IF {
851 /// Offset (1 bits)
852 pub const offset: u32 = 1;
853 /// Mask (1 bit: 1 << 1)
854 pub const mask: u32 = 1 << offset;
855 /// Read-only values
856 pub mod R {
857
858 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
859 pub const Match: u32 = 0b1;
860 }
861 pub use super::CC4OF::W;
862 /// Read-write values (empty)
863 pub mod RW {}
864 }
865
866 /// Update interrupt flag
867 pub mod UIF {
868 /// Offset (0 bits)
869 pub const offset: u32 = 0;
870 /// Mask (1 bit: 1 << 0)
871 pub const mask: u32 = 1 << offset;
872 /// Read-only values (empty)
873 pub mod R {}
874 /// Write-only values (empty)
875 pub mod W {}
876 /// Read-write values
877 pub mod RW {
878
879 /// 0b0: No update occurred
880 pub const Clear: u32 = 0b0;
881
882 /// 0b1: Update interrupt pending.
883 pub const UpdatePending: u32 = 0b1;
884 }
885 }
886}
887
888/// event generation register
889pub mod EGR {
890
891 /// Trigger generation
892 pub mod TG {
893 /// Offset (6 bits)
894 pub const offset: u32 = 6;
895 /// Mask (1 bit: 1 << 6)
896 pub const mask: u32 = 1 << offset;
897 /// Read-only values (empty)
898 pub mod R {}
899 /// Write-only values
900 pub mod W {
901
902 /// 0b1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
903 pub const Trigger: u32 = 0b1;
904 }
905 /// Read-write values (empty)
906 pub mod RW {}
907 }
908
909 /// Capture/compare 4 generation
910 pub mod CC4G {
911 /// Offset (4 bits)
912 pub const offset: u32 = 4;
913 /// Mask (1 bit: 1 << 4)
914 pub const mask: u32 = 1 << offset;
915 /// Read-only values (empty)
916 pub mod R {}
917 /// Write-only values
918 pub mod W {
919
920 /// 0b1: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
921 pub const Trigger: u32 = 0b1;
922 }
923 /// Read-write values (empty)
924 pub mod RW {}
925 }
926
927 /// Capture/compare 3 generation
928 pub mod CC3G {
929 /// Offset (3 bits)
930 pub const offset: u32 = 3;
931 /// Mask (1 bit: 1 << 3)
932 pub const mask: u32 = 1 << offset;
933 /// Read-only values (empty)
934 pub mod R {}
935 pub use super::CC4G::W;
936 /// Read-write values (empty)
937 pub mod RW {}
938 }
939
940 /// Capture/compare 2 generation
941 pub mod CC2G {
942 /// Offset (2 bits)
943 pub const offset: u32 = 2;
944 /// Mask (1 bit: 1 << 2)
945 pub const mask: u32 = 1 << offset;
946 /// Read-only values (empty)
947 pub mod R {}
948 pub use super::CC4G::W;
949 /// Read-write values (empty)
950 pub mod RW {}
951 }
952
953 /// Capture/compare 1 generation
954 pub mod CC1G {
955 /// Offset (1 bits)
956 pub const offset: u32 = 1;
957 /// Mask (1 bit: 1 << 1)
958 pub const mask: u32 = 1 << offset;
959 /// Read-only values (empty)
960 pub mod R {}
961 pub use super::CC4G::W;
962 /// Read-write values (empty)
963 pub mod RW {}
964 }
965
966 /// Update generation
967 pub mod UG {
968 /// Offset (0 bits)
969 pub const offset: u32 = 0;
970 /// Mask (1 bit: 1 << 0)
971 pub const mask: u32 = 1 << offset;
972 /// Read-only values (empty)
973 pub mod R {}
974 /// Write-only values
975 pub mod W {
976
977 /// 0b1: Re-initializes the timer counter and generates an update of the registers.
978 pub const Update: u32 = 0b1;
979 }
980 /// Read-write values (empty)
981 pub mod RW {}
982 }
983}
984
985/// CCMR1_Output and CCMR1_Input
986/// CCMR1_Output: capture/compare mode register 1 (output mode)
987/// CCMR1_Input: capture/compare mode register 1 (input mode)
988pub mod CCMR1 {
989
990 /// OC2CE
991 pub mod OC2CE {
992 /// Offset (15 bits)
993 pub const offset: u32 = 15;
994 /// Mask (1 bit: 1 << 15)
995 pub const mask: u32 = 1 << offset;
996 /// Read-only values (empty)
997 pub mod R {}
998 /// Write-only values (empty)
999 pub mod W {}
1000 /// Read-write values (empty)
1001 pub mod RW {}
1002 }
1003
1004 /// OC2M
1005 pub mod OC2M {
1006 /// Offset (12 bits)
1007 pub const offset: u32 = 12;
1008 /// Mask (3 bits: 0b111 << 12)
1009 pub const mask: u32 = 0b111 << offset;
1010 /// Read-only values (empty)
1011 pub mod R {}
1012 /// Write-only values (empty)
1013 pub mod W {}
1014 /// Read-write values
1015 pub mod RW {
1016
1017 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1018 pub const Frozen: u32 = 0b000;
1019
1020 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1021 pub const ActiveOnMatch: u32 = 0b001;
1022
1023 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
1024 pub const InactiveOnMatch: u32 = 0b010;
1025
1026 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy
1027 pub const Toggle: u32 = 0b011;
1028
1029 /// 0b100: OCyREF is forced low
1030 pub const ForceInactive: u32 = 0b100;
1031
1032 /// 0b101: OCyREF is forced high
1033 pub const ForceActive: u32 = 0b101;
1034
1035 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
1036 pub const PwmMode1: u32 = 0b110;
1037
1038 /// 0b111: Inversely to PwmMode1
1039 pub const PwmMode2: u32 = 0b111;
1040 }
1041 }
1042
1043 /// OC2PE
1044 pub mod OC2PE {
1045 /// Offset (11 bits)
1046 pub const offset: u32 = 11;
1047 /// Mask (1 bit: 1 << 11)
1048 pub const mask: u32 = 1 << offset;
1049 /// Read-only values (empty)
1050 pub mod R {}
1051 /// Write-only values (empty)
1052 pub mod W {}
1053 /// Read-write values
1054 pub mod RW {
1055
1056 /// 0b0: Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately
1057 pub const Disabled: u32 = 0b0;
1058
1059 /// 0b1: Preload register on CCR2 enabled. Preload value is loaded into active register on each update event
1060 pub const Enabled: u32 = 0b1;
1061 }
1062 }
1063
1064 /// OC2FE
1065 pub mod OC2FE {
1066 /// Offset (10 bits)
1067 pub const offset: u32 = 10;
1068 /// Mask (1 bit: 1 << 10)
1069 pub const mask: u32 = 1 << offset;
1070 /// Read-only values (empty)
1071 pub mod R {}
1072 /// Write-only values (empty)
1073 pub mod W {}
1074 /// Read-write values (empty)
1075 pub mod RW {}
1076 }
1077
1078 /// CC2S
1079 pub mod CC2S {
1080 /// Offset (8 bits)
1081 pub const offset: u32 = 8;
1082 /// Mask (2 bits: 0b11 << 8)
1083 pub const mask: u32 = 0b11 << offset;
1084 /// Read-only values (empty)
1085 pub mod R {}
1086 /// Write-only values (empty)
1087 pub mod W {}
1088 /// Read-write values
1089 pub mod RW {
1090
1091 /// 0b00: CC2 channel is configured as output
1092 pub const Output: u32 = 0b00;
1093 }
1094 }
1095
1096 /// OC1CE
1097 pub mod OC1CE {
1098 /// Offset (7 bits)
1099 pub const offset: u32 = 7;
1100 /// Mask (1 bit: 1 << 7)
1101 pub const mask: u32 = 1 << offset;
1102 /// Read-only values (empty)
1103 pub mod R {}
1104 /// Write-only values (empty)
1105 pub mod W {}
1106 /// Read-write values (empty)
1107 pub mod RW {}
1108 }
1109
1110 /// OC1M
1111 pub mod OC1M {
1112 /// Offset (4 bits)
1113 pub const offset: u32 = 4;
1114 /// Mask (3 bits: 0b111 << 4)
1115 pub const mask: u32 = 0b111 << offset;
1116 /// Read-only values (empty)
1117 pub mod R {}
1118 /// Write-only values (empty)
1119 pub mod W {}
1120 pub use super::OC2M::RW;
1121 }
1122
1123 /// OC1PE
1124 pub mod OC1PE {
1125 /// Offset (3 bits)
1126 pub const offset: u32 = 3;
1127 /// Mask (1 bit: 1 << 3)
1128 pub const mask: u32 = 1 << offset;
1129 /// Read-only values (empty)
1130 pub mod R {}
1131 /// Write-only values (empty)
1132 pub mod W {}
1133 /// Read-write values
1134 pub mod RW {
1135
1136 /// 0b0: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1137 pub const Disabled: u32 = 0b0;
1138
1139 /// 0b1: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
1140 pub const Enabled: u32 = 0b1;
1141 }
1142 }
1143
1144 /// OC1FE
1145 pub mod OC1FE {
1146 /// Offset (2 bits)
1147 pub const offset: u32 = 2;
1148 /// Mask (1 bit: 1 << 2)
1149 pub const mask: u32 = 1 << offset;
1150 /// Read-only values (empty)
1151 pub mod R {}
1152 /// Write-only values (empty)
1153 pub mod W {}
1154 /// Read-write values (empty)
1155 pub mod RW {}
1156 }
1157
1158 /// CC1S
1159 pub mod CC1S {
1160 /// Offset (0 bits)
1161 pub const offset: u32 = 0;
1162 /// Mask (2 bits: 0b11 << 0)
1163 pub const mask: u32 = 0b11 << offset;
1164 /// Read-only values (empty)
1165 pub mod R {}
1166 /// Write-only values (empty)
1167 pub mod W {}
1168 /// Read-write values
1169 pub mod RW {
1170
1171 /// 0b00: CC1 channel is configured as output
1172 pub const Output: u32 = 0b00;
1173 }
1174 }
1175
1176 /// Input capture 2 filter
1177 pub mod IC2F {
1178 /// Offset (12 bits)
1179 pub const offset: u32 = 12;
1180 /// Mask (4 bits: 0b1111 << 12)
1181 pub const mask: u32 = 0b1111 << offset;
1182 /// Read-only values (empty)
1183 pub mod R {}
1184 /// Write-only values (empty)
1185 pub mod W {}
1186 /// Read-write values (empty)
1187 pub mod RW {}
1188 }
1189
1190 /// Input capture 2 prescaler
1191 pub mod IC2PSC {
1192 /// Offset (10 bits)
1193 pub const offset: u32 = 10;
1194 /// Mask (2 bits: 0b11 << 10)
1195 pub const mask: u32 = 0b11 << offset;
1196 /// Read-only values (empty)
1197 pub mod R {}
1198 /// Write-only values (empty)
1199 pub mod W {}
1200 /// Read-write values (empty)
1201 pub mod RW {}
1202 }
1203
1204 /// Input capture 1 filter
1205 pub mod IC1F {
1206 /// Offset (4 bits)
1207 pub const offset: u32 = 4;
1208 /// Mask (4 bits: 0b1111 << 4)
1209 pub const mask: u32 = 0b1111 << offset;
1210 /// Read-only values (empty)
1211 pub mod R {}
1212 /// Write-only values (empty)
1213 pub mod W {}
1214 /// Read-write values
1215 pub mod RW {
1216
1217 /// 0b0000: No filter, sampling is done at fDTS
1218 pub const NoFilter: u32 = 0b0000;
1219
1220 /// 0b0001: fSAMPLING=fCK_INT, N=2
1221 pub const FCK_INT_N2: u32 = 0b0001;
1222
1223 /// 0b0010: fSAMPLING=fCK_INT, N=4
1224 pub const FCK_INT_N4: u32 = 0b0010;
1225
1226 /// 0b0011: fSAMPLING=fCK_INT, N=8
1227 pub const FCK_INT_N8: u32 = 0b0011;
1228
1229 /// 0b0100: fSAMPLING=fDTS/2, N=6
1230 pub const FDTS_Div2_N6: u32 = 0b0100;
1231
1232 /// 0b0101: fSAMPLING=fDTS/2, N=8
1233 pub const FDTS_Div2_N8: u32 = 0b0101;
1234
1235 /// 0b0110: fSAMPLING=fDTS/4, N=6
1236 pub const FDTS_Div4_N6: u32 = 0b0110;
1237
1238 /// 0b0111: fSAMPLING=fDTS/4, N=8
1239 pub const FDTS_Div4_N8: u32 = 0b0111;
1240
1241 /// 0b1000: fSAMPLING=fDTS/8, N=6
1242 pub const FDTS_Div8_N6: u32 = 0b1000;
1243
1244 /// 0b1001: fSAMPLING=fDTS/8, N=8
1245 pub const FDTS_Div8_N8: u32 = 0b1001;
1246
1247 /// 0b1010: fSAMPLING=fDTS/16, N=5
1248 pub const FDTS_Div16_N5: u32 = 0b1010;
1249
1250 /// 0b1011: fSAMPLING=fDTS/16, N=6
1251 pub const FDTS_Div16_N6: u32 = 0b1011;
1252
1253 /// 0b1100: fSAMPLING=fDTS/16, N=8
1254 pub const FDTS_Div16_N8: u32 = 0b1100;
1255
1256 /// 0b1101: fSAMPLING=fDTS/32, N=5
1257 pub const FDTS_Div32_N5: u32 = 0b1101;
1258
1259 /// 0b1110: fSAMPLING=fDTS/32, N=6
1260 pub const FDTS_Div32_N6: u32 = 0b1110;
1261
1262 /// 0b1111: fSAMPLING=fDTS/32, N=8
1263 pub const FDTS_Div32_N8: u32 = 0b1111;
1264 }
1265 }
1266
1267 /// Input capture 1 prescaler
1268 pub mod IC1PSC {
1269 /// Offset (2 bits)
1270 pub const offset: u32 = 2;
1271 /// Mask (2 bits: 0b11 << 2)
1272 pub const mask: u32 = 0b11 << offset;
1273 /// Read-only values (empty)
1274 pub mod R {}
1275 /// Write-only values (empty)
1276 pub mod W {}
1277 /// Read-write values (empty)
1278 pub mod RW {}
1279 }
1280}
1281
1282/// CCMR2_Output and CCMR2_Input
1283/// CCMR2_Output: capture/compare mode register 2 (output mode)
1284/// CCMR2_Input: capture/compare mode register 2 (input mode)
1285pub mod CCMR2 {
1286
1287 /// O24CE
1288 pub mod OC4CE {
1289 /// Offset (15 bits)
1290 pub const offset: u32 = 15;
1291 /// Mask (1 bit: 1 << 15)
1292 pub const mask: u32 = 1 << offset;
1293 /// Read-only values (empty)
1294 pub mod R {}
1295 /// Write-only values (empty)
1296 pub mod W {}
1297 /// Read-write values (empty)
1298 pub mod RW {}
1299 }
1300
1301 /// OC4M
1302 pub mod OC4M {
1303 /// Offset (12 bits)
1304 pub const offset: u32 = 12;
1305 /// Mask (3 bits: 0b111 << 12)
1306 pub const mask: u32 = 0b111 << offset;
1307 /// Read-only values (empty)
1308 pub mod R {}
1309 /// Write-only values (empty)
1310 pub mod W {}
1311 /// Read-write values
1312 pub mod RW {
1313
1314 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1315 pub const Frozen: u32 = 0b000;
1316
1317 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1318 pub const ActiveOnMatch: u32 = 0b001;
1319
1320 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
1321 pub const InactiveOnMatch: u32 = 0b010;
1322
1323 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy
1324 pub const Toggle: u32 = 0b011;
1325
1326 /// 0b100: OCyREF is forced low
1327 pub const ForceInactive: u32 = 0b100;
1328
1329 /// 0b101: OCyREF is forced high
1330 pub const ForceActive: u32 = 0b101;
1331
1332 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
1333 pub const PwmMode1: u32 = 0b110;
1334
1335 /// 0b111: Inversely to PwmMode1
1336 pub const PwmMode2: u32 = 0b111;
1337 }
1338 }
1339
1340 /// OC4PE
1341 pub mod OC4PE {
1342 /// Offset (11 bits)
1343 pub const offset: u32 = 11;
1344 /// Mask (1 bit: 1 << 11)
1345 pub const mask: u32 = 1 << offset;
1346 /// Read-only values (empty)
1347 pub mod R {}
1348 /// Write-only values (empty)
1349 pub mod W {}
1350 /// Read-write values
1351 pub mod RW {
1352
1353 /// 0b0: Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately
1354 pub const Disabled: u32 = 0b0;
1355
1356 /// 0b1: Preload register on CCR4 enabled. Preload value is loaded into active register on each update event
1357 pub const Enabled: u32 = 0b1;
1358 }
1359 }
1360
1361 /// OC4FE
1362 pub mod OC4FE {
1363 /// Offset (10 bits)
1364 pub const offset: u32 = 10;
1365 /// Mask (1 bit: 1 << 10)
1366 pub const mask: u32 = 1 << offset;
1367 /// Read-only values (empty)
1368 pub mod R {}
1369 /// Write-only values (empty)
1370 pub mod W {}
1371 /// Read-write values (empty)
1372 pub mod RW {}
1373 }
1374
1375 /// CC4S
1376 pub mod CC4S {
1377 /// Offset (8 bits)
1378 pub const offset: u32 = 8;
1379 /// Mask (2 bits: 0b11 << 8)
1380 pub const mask: u32 = 0b11 << offset;
1381 /// Read-only values (empty)
1382 pub mod R {}
1383 /// Write-only values (empty)
1384 pub mod W {}
1385 /// Read-write values
1386 pub mod RW {
1387
1388 /// 0b00: CC4 channel is configured as output
1389 pub const Output: u32 = 0b00;
1390 }
1391 }
1392
1393 /// OC3CE
1394 pub mod OC3CE {
1395 /// Offset (7 bits)
1396 pub const offset: u32 = 7;
1397 /// Mask (1 bit: 1 << 7)
1398 pub const mask: u32 = 1 << offset;
1399 /// Read-only values (empty)
1400 pub mod R {}
1401 /// Write-only values (empty)
1402 pub mod W {}
1403 /// Read-write values (empty)
1404 pub mod RW {}
1405 }
1406
1407 /// OC3M
1408 pub mod OC3M {
1409 /// Offset (4 bits)
1410 pub const offset: u32 = 4;
1411 /// Mask (3 bits: 0b111 << 4)
1412 pub const mask: u32 = 0b111 << offset;
1413 /// Read-only values (empty)
1414 pub mod R {}
1415 /// Write-only values (empty)
1416 pub mod W {}
1417 pub use super::OC4M::RW;
1418 }
1419
1420 /// OC3PE
1421 pub mod OC3PE {
1422 /// Offset (3 bits)
1423 pub const offset: u32 = 3;
1424 /// Mask (1 bit: 1 << 3)
1425 pub const mask: u32 = 1 << offset;
1426 /// Read-only values (empty)
1427 pub mod R {}
1428 /// Write-only values (empty)
1429 pub mod W {}
1430 /// Read-write values
1431 pub mod RW {
1432
1433 /// 0b0: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1434 pub const Disabled: u32 = 0b0;
1435
1436 /// 0b1: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
1437 pub const Enabled: u32 = 0b1;
1438 }
1439 }
1440
1441 /// OC3FE
1442 pub mod OC3FE {
1443 /// Offset (2 bits)
1444 pub const offset: u32 = 2;
1445 /// Mask (1 bit: 1 << 2)
1446 pub const mask: u32 = 1 << offset;
1447 /// Read-only values (empty)
1448 pub mod R {}
1449 /// Write-only values (empty)
1450 pub mod W {}
1451 /// Read-write values (empty)
1452 pub mod RW {}
1453 }
1454
1455 /// CC3S
1456 pub mod CC3S {
1457 /// Offset (0 bits)
1458 pub const offset: u32 = 0;
1459 /// Mask (2 bits: 0b11 << 0)
1460 pub const mask: u32 = 0b11 << offset;
1461 /// Read-only values (empty)
1462 pub mod R {}
1463 /// Write-only values (empty)
1464 pub mod W {}
1465 /// Read-write values
1466 pub mod RW {
1467
1468 /// 0b00: CC3 channel is configured as output
1469 pub const Output: u32 = 0b00;
1470 }
1471 }
1472
1473 /// Input capture 4 filter
1474 pub mod IC4F {
1475 /// Offset (12 bits)
1476 pub const offset: u32 = 12;
1477 /// Mask (4 bits: 0b1111 << 12)
1478 pub const mask: u32 = 0b1111 << offset;
1479 /// Read-only values (empty)
1480 pub mod R {}
1481 /// Write-only values (empty)
1482 pub mod W {}
1483 /// Read-write values (empty)
1484 pub mod RW {}
1485 }
1486
1487 /// Input capture 4 prescaler
1488 pub mod IC4PSC {
1489 /// Offset (10 bits)
1490 pub const offset: u32 = 10;
1491 /// Mask (2 bits: 0b11 << 10)
1492 pub const mask: u32 = 0b11 << offset;
1493 /// Read-only values (empty)
1494 pub mod R {}
1495 /// Write-only values (empty)
1496 pub mod W {}
1497 /// Read-write values (empty)
1498 pub mod RW {}
1499 }
1500
1501 /// Input capture 3 filter
1502 pub mod IC3F {
1503 /// Offset (4 bits)
1504 pub const offset: u32 = 4;
1505 /// Mask (4 bits: 0b1111 << 4)
1506 pub const mask: u32 = 0b1111 << offset;
1507 /// Read-only values (empty)
1508 pub mod R {}
1509 /// Write-only values (empty)
1510 pub mod W {}
1511 /// Read-write values (empty)
1512 pub mod RW {}
1513 }
1514
1515 /// Input capture 3 prescaler
1516 pub mod IC3PSC {
1517 /// Offset (2 bits)
1518 pub const offset: u32 = 2;
1519 /// Mask (2 bits: 0b11 << 2)
1520 pub const mask: u32 = 0b11 << offset;
1521 /// Read-only values (empty)
1522 pub mod R {}
1523 /// Write-only values (empty)
1524 pub mod W {}
1525 /// Read-write values (empty)
1526 pub mod RW {}
1527 }
1528}
1529
1530/// capture/compare enable register
1531pub mod CCER {
1532
1533 /// Capture/Compare 4 output Polarity
1534 pub mod CC4NP {
1535 /// Offset (15 bits)
1536 pub const offset: u32 = 15;
1537 /// Mask (1 bit: 1 << 15)
1538 pub const mask: u32 = 1 << offset;
1539 /// Read-only values (empty)
1540 pub mod R {}
1541 /// Write-only values (empty)
1542 pub mod W {}
1543 /// Read-write values (empty)
1544 pub mod RW {}
1545 }
1546
1547 /// Capture/Compare 3 output Polarity
1548 pub mod CC4P {
1549 /// Offset (13 bits)
1550 pub const offset: u32 = 13;
1551 /// Mask (1 bit: 1 << 13)
1552 pub const mask: u32 = 1 << offset;
1553 /// Read-only values (empty)
1554 pub mod R {}
1555 /// Write-only values (empty)
1556 pub mod W {}
1557 /// Read-write values (empty)
1558 pub mod RW {}
1559 }
1560
1561 /// Capture/Compare 4 output enable
1562 pub mod CC4E {
1563 /// Offset (12 bits)
1564 pub const offset: u32 = 12;
1565 /// Mask (1 bit: 1 << 12)
1566 pub const mask: u32 = 1 << offset;
1567 /// Read-only values (empty)
1568 pub mod R {}
1569 /// Write-only values (empty)
1570 pub mod W {}
1571 /// Read-write values (empty)
1572 pub mod RW {}
1573 }
1574
1575 /// Capture/Compare 3 output Polarity
1576 pub mod CC3NP {
1577 /// Offset (11 bits)
1578 pub const offset: u32 = 11;
1579 /// Mask (1 bit: 1 << 11)
1580 pub const mask: u32 = 1 << offset;
1581 /// Read-only values (empty)
1582 pub mod R {}
1583 /// Write-only values (empty)
1584 pub mod W {}
1585 /// Read-write values (empty)
1586 pub mod RW {}
1587 }
1588
1589 /// Capture/Compare 3 output Polarity
1590 pub mod CC3P {
1591 /// Offset (9 bits)
1592 pub const offset: u32 = 9;
1593 /// Mask (1 bit: 1 << 9)
1594 pub const mask: u32 = 1 << offset;
1595 /// Read-only values (empty)
1596 pub mod R {}
1597 /// Write-only values (empty)
1598 pub mod W {}
1599 /// Read-write values (empty)
1600 pub mod RW {}
1601 }
1602
1603 /// Capture/Compare 3 output enable
1604 pub mod CC3E {
1605 /// Offset (8 bits)
1606 pub const offset: u32 = 8;
1607 /// Mask (1 bit: 1 << 8)
1608 pub const mask: u32 = 1 << offset;
1609 /// Read-only values (empty)
1610 pub mod R {}
1611 /// Write-only values (empty)
1612 pub mod W {}
1613 /// Read-write values (empty)
1614 pub mod RW {}
1615 }
1616
1617 /// Capture/Compare 2 output Polarity
1618 pub mod CC2NP {
1619 /// Offset (7 bits)
1620 pub const offset: u32 = 7;
1621 /// Mask (1 bit: 1 << 7)
1622 pub const mask: u32 = 1 << offset;
1623 /// Read-only values (empty)
1624 pub mod R {}
1625 /// Write-only values (empty)
1626 pub mod W {}
1627 /// Read-write values (empty)
1628 pub mod RW {}
1629 }
1630
1631 /// Capture/Compare 2 output Polarity
1632 pub mod CC2P {
1633 /// Offset (5 bits)
1634 pub const offset: u32 = 5;
1635 /// Mask (1 bit: 1 << 5)
1636 pub const mask: u32 = 1 << offset;
1637 /// Read-only values (empty)
1638 pub mod R {}
1639 /// Write-only values (empty)
1640 pub mod W {}
1641 /// Read-write values (empty)
1642 pub mod RW {}
1643 }
1644
1645 /// Capture/Compare 2 output enable
1646 pub mod CC2E {
1647 /// Offset (4 bits)
1648 pub const offset: u32 = 4;
1649 /// Mask (1 bit: 1 << 4)
1650 pub const mask: u32 = 1 << offset;
1651 /// Read-only values (empty)
1652 pub mod R {}
1653 /// Write-only values (empty)
1654 pub mod W {}
1655 /// Read-write values (empty)
1656 pub mod RW {}
1657 }
1658
1659 /// Capture/Compare 1 output Polarity
1660 pub mod CC1NP {
1661 /// Offset (3 bits)
1662 pub const offset: u32 = 3;
1663 /// Mask (1 bit: 1 << 3)
1664 pub const mask: u32 = 1 << offset;
1665 /// Read-only values (empty)
1666 pub mod R {}
1667 /// Write-only values (empty)
1668 pub mod W {}
1669 /// Read-write values (empty)
1670 pub mod RW {}
1671 }
1672
1673 /// Capture/Compare 1 output Polarity
1674 pub mod CC1P {
1675 /// Offset (1 bits)
1676 pub const offset: u32 = 1;
1677 /// Mask (1 bit: 1 << 1)
1678 pub const mask: u32 = 1 << offset;
1679 /// Read-only values (empty)
1680 pub mod R {}
1681 /// Write-only values (empty)
1682 pub mod W {}
1683 /// Read-write values (empty)
1684 pub mod RW {}
1685 }
1686
1687 /// Capture/Compare 1 output enable
1688 pub mod CC1E {
1689 /// Offset (0 bits)
1690 pub const offset: u32 = 0;
1691 /// Mask (1 bit: 1 << 0)
1692 pub const mask: u32 = 1 << offset;
1693 /// Read-only values (empty)
1694 pub mod R {}
1695 /// Write-only values (empty)
1696 pub mod W {}
1697 /// Read-write values (empty)
1698 pub mod RW {}
1699 }
1700}
1701
1702/// counter
1703pub mod CNT {
1704
1705 /// Counter value
1706 pub mod CNT {
1707 /// Offset (0 bits)
1708 pub const offset: u32 = 0;
1709 /// Mask (32 bits: 0xffffffff << 0)
1710 pub const mask: u32 = 0xffffffff << offset;
1711 /// Read-only values (empty)
1712 pub mod R {}
1713 /// Write-only values (empty)
1714 pub mod W {}
1715 /// Read-write values (empty)
1716 pub mod RW {}
1717 }
1718}
1719
1720/// prescaler
1721pub mod PSC {
1722
1723 /// Prescaler value
1724 pub mod PSC {
1725 /// Offset (0 bits)
1726 pub const offset: u32 = 0;
1727 /// Mask (16 bits: 0xffff << 0)
1728 pub const mask: u32 = 0xffff << offset;
1729 /// Read-only values (empty)
1730 pub mod R {}
1731 /// Write-only values (empty)
1732 pub mod W {}
1733 /// Read-write values (empty)
1734 pub mod RW {}
1735 }
1736}
1737
1738/// auto-reload register
1739pub mod ARR {
1740
1741 /// Auto-reload value
1742 pub mod ARR {
1743 /// Offset (0 bits)
1744 pub const offset: u32 = 0;
1745 /// Mask (32 bits: 0xffffffff << 0)
1746 pub const mask: u32 = 0xffffffff << offset;
1747 /// Read-only values (empty)
1748 pub mod R {}
1749 /// Write-only values (empty)
1750 pub mod W {}
1751 /// Read-write values (empty)
1752 pub mod RW {}
1753 }
1754}
1755
1756/// capture/compare register
1757pub mod CCR1 {
1758
1759 /// Capture/Compare value
1760 pub mod CCR {
1761 /// Offset (0 bits)
1762 pub const offset: u32 = 0;
1763 /// Mask (32 bits: 0xffffffff << 0)
1764 pub const mask: u32 = 0xffffffff << offset;
1765 /// Read-only values (empty)
1766 pub mod R {}
1767 /// Write-only values (empty)
1768 pub mod W {}
1769 /// Read-write values (empty)
1770 pub mod RW {}
1771 }
1772}
1773
1774/// capture/compare register
1775pub mod CCR2 {
1776 pub use super::CCR1::CCR;
1777}
1778
1779/// capture/compare register
1780pub mod CCR3 {
1781 pub use super::CCR1::CCR;
1782}
1783
1784/// capture/compare register
1785pub mod CCR4 {
1786 pub use super::CCR1::CCR;
1787}
1788
1789/// DMA control register
1790pub mod DCR {
1791
1792 /// DMA burst length
1793 pub mod DBL {
1794 /// Offset (8 bits)
1795 pub const offset: u32 = 8;
1796 /// Mask (5 bits: 0b11111 << 8)
1797 pub const mask: u32 = 0b11111 << offset;
1798 /// Read-only values (empty)
1799 pub mod R {}
1800 /// Write-only values (empty)
1801 pub mod W {}
1802 /// Read-write values (empty)
1803 pub mod RW {}
1804 }
1805
1806 /// DMA base address
1807 pub mod DBA {
1808 /// Offset (0 bits)
1809 pub const offset: u32 = 0;
1810 /// Mask (5 bits: 0b11111 << 0)
1811 pub const mask: u32 = 0b11111 << offset;
1812 /// Read-only values (empty)
1813 pub mod R {}
1814 /// Write-only values (empty)
1815 pub mod W {}
1816 /// Read-write values (empty)
1817 pub mod RW {}
1818 }
1819}
1820
1821/// DMA address for full transfer
1822pub mod DMAR {
1823
1824 /// DMA register for burst accesses
1825 pub mod DMAB {
1826 /// Offset (0 bits)
1827 pub const offset: u32 = 0;
1828 /// Mask (16 bits: 0xffff << 0)
1829 pub const mask: u32 = 0xffff << offset;
1830 /// Read-only values (empty)
1831 pub mod R {}
1832 /// Write-only values (empty)
1833 pub mod W {}
1834 /// Read-write values (empty)
1835 pub mod RW {}
1836 }
1837}
1838
1839/// TIM5 option register
1840pub mod OR {
1841
1842 /// Timer Input 4 remap
1843 pub mod IT4_RMP {
1844 /// Offset (6 bits)
1845 pub const offset: u32 = 6;
1846 /// Mask (2 bits: 0b11 << 6)
1847 pub const mask: u32 = 0b11 << offset;
1848 /// Read-only values (empty)
1849 pub mod R {}
1850 /// Write-only values (empty)
1851 pub mod W {}
1852 /// Read-write values (empty)
1853 pub mod RW {}
1854 }
1855}
1856#[repr(C)]
1857pub struct RegisterBlock {
1858 /// control register 1
1859 pub CR1: RWRegister<u32>,
1860
1861 /// control register 2
1862 pub CR2: RWRegister<u32>,
1863
1864 /// slave mode control register
1865 pub SMCR: RWRegister<u32>,
1866
1867 /// DMA/Interrupt enable register
1868 pub DIER: RWRegister<u32>,
1869
1870 /// status register
1871 pub SR: RWRegister<u32>,
1872
1873 /// event generation register
1874 pub EGR: WORegister<u32>,
1875
1876 /// CCMR1_Output and CCMR1_Input
1877 /// CCMR1_Output: capture/compare mode register 1 (output mode)
1878 /// CCMR1_Input: capture/compare mode register 1 (input mode)
1879 pub CCMR1: RWRegister<u32>,
1880
1881 /// CCMR2_Output and CCMR2_Input
1882 /// CCMR2_Output: capture/compare mode register 2 (output mode)
1883 /// CCMR2_Input: capture/compare mode register 2 (input mode)
1884 pub CCMR2: RWRegister<u32>,
1885
1886 /// capture/compare enable register
1887 pub CCER: RWRegister<u32>,
1888
1889 /// counter
1890 pub CNT: RWRegister<u32>,
1891
1892 /// prescaler
1893 pub PSC: RWRegister<u32>,
1894
1895 /// auto-reload register
1896 pub ARR: RWRegister<u32>,
1897
1898 _reserved1: [u8; 4],
1899
1900 /// capture/compare register
1901 pub CCR1: RWRegister<u32>,
1902
1903 /// capture/compare register
1904 pub CCR2: RWRegister<u32>,
1905
1906 /// capture/compare register
1907 pub CCR3: RWRegister<u32>,
1908
1909 /// capture/compare register
1910 pub CCR4: RWRegister<u32>,
1911
1912 _reserved2: [u8; 4],
1913
1914 /// DMA control register
1915 pub DCR: RWRegister<u32>,
1916
1917 /// DMA address for full transfer
1918 pub DMAR: RWRegister<u32>,
1919
1920 /// TIM5 option register
1921 pub OR: RWRegister<u32>,
1922}
1923pub struct ResetValues {
1924 pub CR1: u32,
1925 pub CR2: u32,
1926 pub SMCR: u32,
1927 pub DIER: u32,
1928 pub SR: u32,
1929 pub EGR: u32,
1930 pub CCMR1: u32,
1931 pub CCMR2: u32,
1932 pub CCER: u32,
1933 pub CNT: u32,
1934 pub PSC: u32,
1935 pub ARR: u32,
1936 pub CCR1: u32,
1937 pub CCR2: u32,
1938 pub CCR3: u32,
1939 pub CCR4: u32,
1940 pub DCR: u32,
1941 pub DMAR: u32,
1942 pub OR: u32,
1943}
1944#[cfg(not(feature = "nosync"))]
1945pub struct Instance {
1946 pub(crate) addr: u32,
1947 pub(crate) _marker: PhantomData<*const RegisterBlock>,
1948}
1949#[cfg(not(feature = "nosync"))]
1950impl ::core::ops::Deref for Instance {
1951 type Target = RegisterBlock;
1952 #[inline(always)]
1953 fn deref(&self) -> &RegisterBlock {
1954 unsafe { &*(self.addr as *const _) }
1955 }
1956}
1957#[cfg(feature = "rtic")]
1958unsafe impl Send for Instance {}