stm32ral/stm32f4/peripherals/tim11_v1.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! General-purpose-timers
4//!
5//! Used by: stm32f401, stm32f405, stm32f407, stm32f411, stm32f427, stm32f429
6
7use crate::{RWRegister, WORegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// control register 1
12pub mod CR1 {
13
14 /// Clock division
15 pub mod CKD {
16 /// Offset (8 bits)
17 pub const offset: u32 = 8;
18 /// Mask (2 bits: 0b11 << 8)
19 pub const mask: u32 = 0b11 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values
25 pub mod RW {
26
27 /// 0b00: t_DTS = t_CK_INT
28 pub const Div1: u32 = 0b00;
29
30 /// 0b01: t_DTS = 2 × t_CK_INT
31 pub const Div2: u32 = 0b01;
32
33 /// 0b10: t_DTS = 4 × t_CK_INT
34 pub const Div4: u32 = 0b10;
35 }
36 }
37
38 /// Auto-reload preload enable
39 pub mod ARPE {
40 /// Offset (7 bits)
41 pub const offset: u32 = 7;
42 /// Mask (1 bit: 1 << 7)
43 pub const mask: u32 = 1 << offset;
44 /// Read-only values (empty)
45 pub mod R {}
46 /// Write-only values (empty)
47 pub mod W {}
48 /// Read-write values
49 pub mod RW {
50
51 /// 0b0: TIMx_APRR register is not buffered
52 pub const Disabled: u32 = 0b0;
53
54 /// 0b1: TIMx_APRR register is buffered
55 pub const Enabled: u32 = 0b1;
56 }
57 }
58
59 /// Update request source
60 pub mod URS {
61 /// Offset (2 bits)
62 pub const offset: u32 = 2;
63 /// Mask (1 bit: 1 << 2)
64 pub const mask: u32 = 1 << offset;
65 /// Read-only values (empty)
66 pub mod R {}
67 /// Write-only values (empty)
68 pub mod W {}
69 /// Read-write values
70 pub mod RW {
71
72 /// 0b0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
73 pub const AnyEvent: u32 = 0b0;
74
75 /// 0b1: Only counter overflow/underflow generates an update interrupt or DMA request
76 pub const CounterOnly: u32 = 0b1;
77 }
78 }
79
80 /// Update disable
81 pub mod UDIS {
82 /// Offset (1 bits)
83 pub const offset: u32 = 1;
84 /// Mask (1 bit: 1 << 1)
85 pub const mask: u32 = 1 << offset;
86 /// Read-only values (empty)
87 pub mod R {}
88 /// Write-only values (empty)
89 pub mod W {}
90 /// Read-write values
91 pub mod RW {
92
93 /// 0b0: Update event enabled
94 pub const Enabled: u32 = 0b0;
95
96 /// 0b1: Update event disabled
97 pub const Disabled: u32 = 0b1;
98 }
99 }
100
101 /// Counter enable
102 pub mod CEN {
103 /// Offset (0 bits)
104 pub const offset: u32 = 0;
105 /// Mask (1 bit: 1 << 0)
106 pub const mask: u32 = 1 << offset;
107 /// Read-only values (empty)
108 pub mod R {}
109 /// Write-only values (empty)
110 pub mod W {}
111 /// Read-write values
112 pub mod RW {
113
114 /// 0b0: Counter disabled
115 pub const Disabled: u32 = 0b0;
116
117 /// 0b1: Counter enabled
118 pub const Enabled: u32 = 0b1;
119 }
120 }
121
122 /// One-pulse mode
123 pub mod OPM {
124 /// Offset (3 bits)
125 pub const offset: u32 = 3;
126 /// Mask (1 bit: 1 << 3)
127 pub const mask: u32 = 1 << offset;
128 /// Read-only values (empty)
129 pub mod R {}
130 /// Write-only values (empty)
131 pub mod W {}
132 /// Read-write values
133 pub mod RW {
134
135 /// 0b0: Counter is not stopped at update event
136 pub const Disabled: u32 = 0b0;
137
138 /// 0b1: Counter stops counting at the next update event (clearing the CEN bit)
139 pub const Enabled: u32 = 0b1;
140 }
141 }
142}
143
144/// DMA/Interrupt enable register
145pub mod DIER {
146
147 /// Capture/Compare 1 interrupt enable
148 pub mod CC1IE {
149 /// Offset (1 bits)
150 pub const offset: u32 = 1;
151 /// Mask (1 bit: 1 << 1)
152 pub const mask: u32 = 1 << offset;
153 /// Read-only values (empty)
154 pub mod R {}
155 /// Write-only values (empty)
156 pub mod W {}
157 /// Read-write values (empty)
158 pub mod RW {}
159 }
160
161 /// Update interrupt enable
162 pub mod UIE {
163 /// Offset (0 bits)
164 pub const offset: u32 = 0;
165 /// Mask (1 bit: 1 << 0)
166 pub const mask: u32 = 1 << offset;
167 /// Read-only values (empty)
168 pub mod R {}
169 /// Write-only values (empty)
170 pub mod W {}
171 /// Read-write values
172 pub mod RW {
173
174 /// 0b0: Update interrupt disabled
175 pub const Disabled: u32 = 0b0;
176
177 /// 0b1: Update interrupt enabled
178 pub const Enabled: u32 = 0b1;
179 }
180 }
181}
182
183/// status register
184pub mod SR {
185
186 /// Capture/Compare 1 overcapture flag
187 pub mod CC1OF {
188 /// Offset (9 bits)
189 pub const offset: u32 = 9;
190 /// Mask (1 bit: 1 << 9)
191 pub const mask: u32 = 1 << offset;
192 /// Read-only values (empty)
193 pub mod R {}
194 /// Write-only values (empty)
195 pub mod W {}
196 /// Read-write values (empty)
197 pub mod RW {}
198 }
199
200 /// Capture/compare 1 interrupt flag
201 pub mod CC1IF {
202 /// Offset (1 bits)
203 pub const offset: u32 = 1;
204 /// Mask (1 bit: 1 << 1)
205 pub const mask: u32 = 1 << offset;
206 /// Read-only values (empty)
207 pub mod R {}
208 /// Write-only values (empty)
209 pub mod W {}
210 /// Read-write values (empty)
211 pub mod RW {}
212 }
213
214 /// Update interrupt flag
215 pub mod UIF {
216 /// Offset (0 bits)
217 pub const offset: u32 = 0;
218 /// Mask (1 bit: 1 << 0)
219 pub const mask: u32 = 1 << offset;
220 /// Read-only values (empty)
221 pub mod R {}
222 /// Write-only values (empty)
223 pub mod W {}
224 /// Read-write values
225 pub mod RW {
226
227 /// 0b0: No update occurred
228 pub const Clear: u32 = 0b0;
229
230 /// 0b1: Update interrupt pending.
231 pub const UpdatePending: u32 = 0b1;
232 }
233 }
234}
235
236/// event generation register
237pub mod EGR {
238
239 /// Capture/compare 1 generation
240 pub mod CC1G {
241 /// Offset (1 bits)
242 pub const offset: u32 = 1;
243 /// Mask (1 bit: 1 << 1)
244 pub const mask: u32 = 1 << offset;
245 /// Read-only values (empty)
246 pub mod R {}
247 /// Write-only values (empty)
248 pub mod W {}
249 /// Read-write values (empty)
250 pub mod RW {}
251 }
252
253 /// Update generation
254 pub mod UG {
255 /// Offset (0 bits)
256 pub const offset: u32 = 0;
257 /// Mask (1 bit: 1 << 0)
258 pub const mask: u32 = 1 << offset;
259 /// Read-only values (empty)
260 pub mod R {}
261 /// Write-only values
262 pub mod W {
263
264 /// 0b1: Re-initializes the timer counter and generates an update of the registers.
265 pub const Update: u32 = 0b1;
266 }
267 /// Read-write values (empty)
268 pub mod RW {}
269 }
270}
271
272/// CCMR1_Output and CCMR1_Input
273/// CCMR1_Output: capture/compare mode register 1 (output mode)
274/// CCMR1_Input: capture/compare mode register 1 (input mode)
275pub mod CCMR1 {
276
277 /// Output Compare 1 mode
278 pub mod OC1M {
279 /// Offset (4 bits)
280 pub const offset: u32 = 4;
281 /// Mask (3 bits: 0b111 << 4)
282 pub const mask: u32 = 0b111 << offset;
283 /// Read-only values (empty)
284 pub mod R {}
285 /// Write-only values (empty)
286 pub mod W {}
287 /// Read-write values
288 pub mod RW {
289
290 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
291 pub const Frozen: u32 = 0b000;
292
293 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
294 pub const ActiveOnMatch: u32 = 0b001;
295
296 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
297 pub const InactiveOnMatch: u32 = 0b010;
298
299 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy
300 pub const Toggle: u32 = 0b011;
301
302 /// 0b100: OCyREF is forced low
303 pub const ForceInactive: u32 = 0b100;
304
305 /// 0b101: OCyREF is forced high
306 pub const ForceActive: u32 = 0b101;
307
308 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
309 pub const PwmMode1: u32 = 0b110;
310
311 /// 0b111: Inversely to PwmMode1
312 pub const PwmMode2: u32 = 0b111;
313 }
314 }
315
316 /// Output Compare 1 preload enable
317 pub mod OC1PE {
318 /// Offset (3 bits)
319 pub const offset: u32 = 3;
320 /// Mask (1 bit: 1 << 3)
321 pub const mask: u32 = 1 << offset;
322 /// Read-only values (empty)
323 pub mod R {}
324 /// Write-only values (empty)
325 pub mod W {}
326 /// Read-write values (empty)
327 pub mod RW {}
328 }
329
330 /// Output Compare 1 fast enable
331 pub mod OC1FE {
332 /// Offset (2 bits)
333 pub const offset: u32 = 2;
334 /// Mask (1 bit: 1 << 2)
335 pub const mask: u32 = 1 << offset;
336 /// Read-only values (empty)
337 pub mod R {}
338 /// Write-only values (empty)
339 pub mod W {}
340 /// Read-write values (empty)
341 pub mod RW {}
342 }
343
344 /// Capture/Compare 1 selection
345 pub mod CC1S {
346 /// Offset (0 bits)
347 pub const offset: u32 = 0;
348 /// Mask (2 bits: 0b11 << 0)
349 pub const mask: u32 = 0b11 << offset;
350 /// Read-only values (empty)
351 pub mod R {}
352 /// Write-only values (empty)
353 pub mod W {}
354 /// Read-write values (empty)
355 pub mod RW {}
356 }
357
358 /// Input capture 1 filter
359 pub mod IC1F {
360 /// Offset (4 bits)
361 pub const offset: u32 = 4;
362 /// Mask (4 bits: 0b1111 << 4)
363 pub const mask: u32 = 0b1111 << offset;
364 /// Read-only values (empty)
365 pub mod R {}
366 /// Write-only values (empty)
367 pub mod W {}
368 /// Read-write values (empty)
369 pub mod RW {}
370 }
371
372 /// Input capture 1 prescaler
373 pub mod IC1PSC {
374 /// Offset (2 bits)
375 pub const offset: u32 = 2;
376 /// Mask (2 bits: 0b11 << 2)
377 pub const mask: u32 = 0b11 << offset;
378 /// Read-only values (empty)
379 pub mod R {}
380 /// Write-only values (empty)
381 pub mod W {}
382 /// Read-write values (empty)
383 pub mod RW {}
384 }
385}
386
387/// capture/compare enable register
388pub mod CCER {
389
390 /// Capture/Compare 1 output Polarity
391 pub mod CC1NP {
392 /// Offset (3 bits)
393 pub const offset: u32 = 3;
394 /// Mask (1 bit: 1 << 3)
395 pub const mask: u32 = 1 << offset;
396 /// Read-only values (empty)
397 pub mod R {}
398 /// Write-only values (empty)
399 pub mod W {}
400 /// Read-write values (empty)
401 pub mod RW {}
402 }
403
404 /// Capture/Compare 1 output Polarity
405 pub mod CC1P {
406 /// Offset (1 bits)
407 pub const offset: u32 = 1;
408 /// Mask (1 bit: 1 << 1)
409 pub const mask: u32 = 1 << offset;
410 /// Read-only values (empty)
411 pub mod R {}
412 /// Write-only values (empty)
413 pub mod W {}
414 /// Read-write values (empty)
415 pub mod RW {}
416 }
417
418 /// Capture/Compare 1 output enable
419 pub mod CC1E {
420 /// Offset (0 bits)
421 pub const offset: u32 = 0;
422 /// Mask (1 bit: 1 << 0)
423 pub const mask: u32 = 1 << offset;
424 /// Read-only values (empty)
425 pub mod R {}
426 /// Write-only values (empty)
427 pub mod W {}
428 /// Read-write values (empty)
429 pub mod RW {}
430 }
431}
432
433/// counter
434pub mod CNT {
435
436 /// counter value
437 pub mod CNT {
438 /// Offset (0 bits)
439 pub const offset: u32 = 0;
440 /// Mask (16 bits: 0xffff << 0)
441 pub const mask: u32 = 0xffff << offset;
442 /// Read-only values (empty)
443 pub mod R {}
444 /// Write-only values (empty)
445 pub mod W {}
446 /// Read-write values (empty)
447 pub mod RW {}
448 }
449}
450
451/// prescaler
452pub mod PSC {
453
454 /// Prescaler value
455 pub mod PSC {
456 /// Offset (0 bits)
457 pub const offset: u32 = 0;
458 /// Mask (16 bits: 0xffff << 0)
459 pub const mask: u32 = 0xffff << offset;
460 /// Read-only values (empty)
461 pub mod R {}
462 /// Write-only values (empty)
463 pub mod W {}
464 /// Read-write values (empty)
465 pub mod RW {}
466 }
467}
468
469/// auto-reload register
470pub mod ARR {
471
472 /// Auto-reload value
473 pub mod ARR {
474 /// Offset (0 bits)
475 pub const offset: u32 = 0;
476 /// Mask (16 bits: 0xffff << 0)
477 pub const mask: u32 = 0xffff << offset;
478 /// Read-only values (empty)
479 pub mod R {}
480 /// Write-only values (empty)
481 pub mod W {}
482 /// Read-write values (empty)
483 pub mod RW {}
484 }
485}
486
487/// capture/compare register
488pub mod CCR1 {
489
490 /// Capture/Compare value
491 pub mod CCR {
492 /// Offset (0 bits)
493 pub const offset: u32 = 0;
494 /// Mask (16 bits: 0xffff << 0)
495 pub const mask: u32 = 0xffff << offset;
496 /// Read-only values (empty)
497 pub mod R {}
498 /// Write-only values (empty)
499 pub mod W {}
500 /// Read-write values (empty)
501 pub mod RW {}
502 }
503}
504
505/// option register
506pub mod OR {
507
508 /// Input 1 remapping capability
509 pub mod RMP {
510 /// Offset (0 bits)
511 pub const offset: u32 = 0;
512 /// Mask (2 bits: 0b11 << 0)
513 pub const mask: u32 = 0b11 << offset;
514 /// Read-only values (empty)
515 pub mod R {}
516 /// Write-only values (empty)
517 pub mod W {}
518 /// Read-write values (empty)
519 pub mod RW {}
520 }
521}
522#[repr(C)]
523pub struct RegisterBlock {
524 /// control register 1
525 pub CR1: RWRegister<u32>,
526
527 _reserved1: [u8; 8],
528
529 /// DMA/Interrupt enable register
530 pub DIER: RWRegister<u32>,
531
532 /// status register
533 pub SR: RWRegister<u32>,
534
535 /// event generation register
536 pub EGR: WORegister<u32>,
537
538 /// CCMR1_Output and CCMR1_Input
539 /// CCMR1_Output: capture/compare mode register 1 (output mode)
540 /// CCMR1_Input: capture/compare mode register 1 (input mode)
541 pub CCMR1: RWRegister<u32>,
542
543 _reserved2: [u8; 4],
544
545 /// capture/compare enable register
546 pub CCER: RWRegister<u32>,
547
548 /// counter
549 pub CNT: RWRegister<u32>,
550
551 /// prescaler
552 pub PSC: RWRegister<u32>,
553
554 /// auto-reload register
555 pub ARR: RWRegister<u32>,
556
557 _reserved3: [u8; 4],
558
559 /// capture/compare register
560 pub CCR1: RWRegister<u32>,
561
562 _reserved4: [u8; 24],
563
564 /// option register
565 pub OR: RWRegister<u32>,
566}
567pub struct ResetValues {
568 pub CR1: u32,
569 pub DIER: u32,
570 pub SR: u32,
571 pub EGR: u32,
572 pub CCMR1: u32,
573 pub CCER: u32,
574 pub CNT: u32,
575 pub PSC: u32,
576 pub ARR: u32,
577 pub CCR1: u32,
578 pub OR: u32,
579}
580#[cfg(not(feature = "nosync"))]
581pub struct Instance {
582 pub(crate) addr: u32,
583 pub(crate) _marker: PhantomData<*const RegisterBlock>,
584}
585#[cfg(not(feature = "nosync"))]
586impl ::core::ops::Deref for Instance {
587 type Target = RegisterBlock;
588 #[inline(always)]
589 fn deref(&self) -> &RegisterBlock {
590 unsafe { &*(self.addr as *const _) }
591 }
592}
593#[cfg(feature = "rtic")]
594unsafe impl Send for Instance {}