stm32ral/stm32f4/instances/
tim5.rs

1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! General-purpose-timers
4//!
5//! Used by: stm32f401, stm32f405, stm32f407, stm32f411, stm32f412, stm32f413, stm32f427, stm32f429, stm32f446, stm32f469
6
7#[cfg(not(feature = "nosync"))]
8pub use crate::stm32f4::peripherals::tim5::Instance;
9pub use crate::stm32f4::peripherals::tim5::{RegisterBlock, ResetValues};
10pub use crate::stm32f4::peripherals::tim5::{
11    ARR, CCER, CCMR1, CCMR2, CCR1, CCR2, CCR3, CCR4, CNT, CR1, CR2, DCR, DIER, DMAR, EGR, OR, PSC,
12    SMCR, SR,
13};
14
15/// Access functions for the TIM5 peripheral instance
16pub mod TIM5 {
17    use super::ResetValues;
18
19    #[cfg(not(feature = "nosync"))]
20    use super::Instance;
21
22    #[cfg(not(feature = "nosync"))]
23    const INSTANCE: Instance = Instance {
24        addr: 0x40000c00,
25        _marker: ::core::marker::PhantomData,
26    };
27
28    /// Reset values for each field in TIM5
29    pub const reset: ResetValues = ResetValues {
30        CR1: 0x00000000,
31        CR2: 0x00000000,
32        SMCR: 0x00000000,
33        DIER: 0x00000000,
34        SR: 0x00000000,
35        EGR: 0x00000000,
36        CCMR1: 0x00000000,
37        CCMR2: 0x00000000,
38        CCER: 0x00000000,
39        CNT: 0x00000000,
40        PSC: 0x00000000,
41        ARR: 0x00000000,
42        CCR1: 0x00000000,
43        CCR2: 0x00000000,
44        CCR3: 0x00000000,
45        CCR4: 0x00000000,
46        DCR: 0x00000000,
47        DMAR: 0x00000000,
48        OR: 0x00000000,
49    };
50
51    #[cfg(not(feature = "nosync"))]
52    #[allow(renamed_and_removed_lints)]
53    #[allow(private_no_mangle_statics)]
54    #[no_mangle]
55    static mut TIM5_TAKEN: bool = false;
56
57    /// Safe access to TIM5
58    ///
59    /// This function returns `Some(Instance)` if this instance is not
60    /// currently taken, and `None` if it is. This ensures that if you
61    /// do get `Some(Instance)`, you are ensured unique access to
62    /// the peripheral and there cannot be data races (unless other
63    /// code uses `unsafe`, of course). You can then pass the
64    /// `Instance` around to other functions as required. When you're
65    /// done with it, you can call `release(instance)` to return it.
66    ///
67    /// `Instance` itself dereferences to a `RegisterBlock`, which
68    /// provides access to the peripheral's registers.
69    #[cfg(not(feature = "nosync"))]
70    #[inline]
71    pub fn take() -> Option<Instance> {
72        external_cortex_m::interrupt::free(|_| unsafe {
73            if TIM5_TAKEN {
74                None
75            } else {
76                TIM5_TAKEN = true;
77                Some(INSTANCE)
78            }
79        })
80    }
81
82    /// Release exclusive access to TIM5
83    ///
84    /// This function allows you to return an `Instance` so that it
85    /// is available to `take()` again. This function will panic if
86    /// you return a different `Instance` or if this instance is not
87    /// already taken.
88    #[cfg(not(feature = "nosync"))]
89    #[inline]
90    pub fn release(inst: Instance) {
91        external_cortex_m::interrupt::free(|_| unsafe {
92            if TIM5_TAKEN && inst.addr == INSTANCE.addr {
93                TIM5_TAKEN = false;
94            } else {
95                panic!("Released a peripheral which was not taken");
96            }
97        });
98    }
99
100    /// Unsafely steal TIM5
101    ///
102    /// This function is similar to take() but forcibly takes the
103    /// Instance, marking it as taken irregardless of its previous
104    /// state.
105    #[cfg(not(feature = "nosync"))]
106    #[inline]
107    pub unsafe fn steal() -> Instance {
108        TIM5_TAKEN = true;
109        INSTANCE
110    }
111}
112
113/// Raw pointer to TIM5
114///
115/// Dereferencing this is unsafe because you are not ensured unique
116/// access to the peripheral, so you may encounter data races with
117/// other users of this peripheral. It is up to you to ensure you
118/// will not cause data races.
119///
120/// This constant is provided for ease of use in unsafe code: you can
121/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
122pub const TIM5: *const RegisterBlock = 0x40000c00 as *const _;
stm32ral/stm32f4/instances/tim5.rs

stm32ral/stm32f4/instances/
tim5.rs
