stm32ral/stm32f3/stm32f373/tim15.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! General purpose timers
4
5use crate::{RWRegister, WORegister};
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// control register 1
10pub mod CR1 {
11
12 /// Clock division
13 pub mod CKD {
14 /// Offset (8 bits)
15 pub const offset: u32 = 8;
16 /// Mask (2 bits: 0b11 << 8)
17 pub const mask: u32 = 0b11 << offset;
18 /// Read-only values (empty)
19 pub mod R {}
20 /// Write-only values (empty)
21 pub mod W {}
22 /// Read-write values
23 pub mod RW {
24
25 /// 0b00: t_DTS = t_CK_INT
26 pub const Div1: u32 = 0b00;
27
28 /// 0b01: t_DTS = 2 × t_CK_INT
29 pub const Div2: u32 = 0b01;
30
31 /// 0b10: t_DTS = 4 × t_CK_INT
32 pub const Div4: u32 = 0b10;
33 }
34 }
35
36 /// Auto-reload preload enable
37 pub mod ARPE {
38 /// Offset (7 bits)
39 pub const offset: u32 = 7;
40 /// Mask (1 bit: 1 << 7)
41 pub const mask: u32 = 1 << offset;
42 /// Read-only values (empty)
43 pub mod R {}
44 /// Write-only values (empty)
45 pub mod W {}
46 /// Read-write values
47 pub mod RW {
48
49 /// 0b0: TIMx_APRR register is not buffered
50 pub const Disabled: u32 = 0b0;
51
52 /// 0b1: TIMx_APRR register is buffered
53 pub const Enabled: u32 = 0b1;
54 }
55 }
56
57 /// One-pulse mode
58 pub mod OPM {
59 /// Offset (3 bits)
60 pub const offset: u32 = 3;
61 /// Mask (1 bit: 1 << 3)
62 pub const mask: u32 = 1 << offset;
63 /// Read-only values (empty)
64 pub mod R {}
65 /// Write-only values (empty)
66 pub mod W {}
67 /// Read-write values
68 pub mod RW {
69
70 /// 0b0: Counter is not stopped at update event
71 pub const Disabled: u32 = 0b0;
72
73 /// 0b1: Counter stops counting at the next update event (clearing the CEN bit)
74 pub const Enabled: u32 = 0b1;
75 }
76 }
77
78 /// Update request source
79 pub mod URS {
80 /// Offset (2 bits)
81 pub const offset: u32 = 2;
82 /// Mask (1 bit: 1 << 2)
83 pub const mask: u32 = 1 << offset;
84 /// Read-only values (empty)
85 pub mod R {}
86 /// Write-only values (empty)
87 pub mod W {}
88 /// Read-write values
89 pub mod RW {
90
91 /// 0b0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
92 pub const AnyEvent: u32 = 0b0;
93
94 /// 0b1: Only counter overflow/underflow generates an update interrupt or DMA request
95 pub const CounterOnly: u32 = 0b1;
96 }
97 }
98
99 /// Update disable
100 pub mod UDIS {
101 /// Offset (1 bits)
102 pub const offset: u32 = 1;
103 /// Mask (1 bit: 1 << 1)
104 pub const mask: u32 = 1 << offset;
105 /// Read-only values (empty)
106 pub mod R {}
107 /// Write-only values (empty)
108 pub mod W {}
109 /// Read-write values
110 pub mod RW {
111
112 /// 0b0: Update event enabled
113 pub const Enabled: u32 = 0b0;
114
115 /// 0b1: Update event disabled
116 pub const Disabled: u32 = 0b1;
117 }
118 }
119
120 /// Counter enable
121 pub mod CEN {
122 /// Offset (0 bits)
123 pub const offset: u32 = 0;
124 /// Mask (1 bit: 1 << 0)
125 pub const mask: u32 = 1 << offset;
126 /// Read-only values (empty)
127 pub mod R {}
128 /// Write-only values (empty)
129 pub mod W {}
130 /// Read-write values
131 pub mod RW {
132
133 /// 0b0: Counter disabled
134 pub const Disabled: u32 = 0b0;
135
136 /// 0b1: Counter enabled
137 pub const Enabled: u32 = 0b1;
138 }
139 }
140}
141
142/// control register 2
143pub mod CR2 {
144
145 /// Output Idle state 2
146 pub mod OIS2 {
147 /// Offset (10 bits)
148 pub const offset: u32 = 10;
149 /// Mask (1 bit: 1 << 10)
150 pub const mask: u32 = 1 << offset;
151 /// Read-only values (empty)
152 pub mod R {}
153 /// Write-only values (empty)
154 pub mod W {}
155 /// Read-write values (empty)
156 pub mod RW {}
157 }
158
159 /// Output Idle state 1
160 pub mod OIS1N {
161 /// Offset (9 bits)
162 pub const offset: u32 = 9;
163 /// Mask (1 bit: 1 << 9)
164 pub const mask: u32 = 1 << offset;
165 /// Read-only values (empty)
166 pub mod R {}
167 /// Write-only values (empty)
168 pub mod W {}
169 /// Read-write values (empty)
170 pub mod RW {}
171 }
172
173 /// Output Idle state 1
174 pub mod OIS1 {
175 /// Offset (8 bits)
176 pub const offset: u32 = 8;
177 /// Mask (1 bit: 1 << 8)
178 pub const mask: u32 = 1 << offset;
179 /// Read-only values (empty)
180 pub mod R {}
181 /// Write-only values (empty)
182 pub mod W {}
183 /// Read-write values (empty)
184 pub mod RW {}
185 }
186
187 /// Master mode selection
188 pub mod MMS {
189 /// Offset (4 bits)
190 pub const offset: u32 = 4;
191 /// Mask (3 bits: 0b111 << 4)
192 pub const mask: u32 = 0b111 << offset;
193 /// Read-only values (empty)
194 pub mod R {}
195 /// Write-only values (empty)
196 pub mod W {}
197 /// Read-write values (empty)
198 pub mod RW {}
199 }
200
201 /// Capture/compare DMA selection
202 pub mod CCDS {
203 /// Offset (3 bits)
204 pub const offset: u32 = 3;
205 /// Mask (1 bit: 1 << 3)
206 pub const mask: u32 = 1 << offset;
207 /// Read-only values (empty)
208 pub mod R {}
209 /// Write-only values (empty)
210 pub mod W {}
211 /// Read-write values (empty)
212 pub mod RW {}
213 }
214
215 /// Capture/compare control update selection
216 pub mod CCUS {
217 /// Offset (2 bits)
218 pub const offset: u32 = 2;
219 /// Mask (1 bit: 1 << 2)
220 pub const mask: u32 = 1 << offset;
221 /// Read-only values (empty)
222 pub mod R {}
223 /// Write-only values (empty)
224 pub mod W {}
225 /// Read-write values (empty)
226 pub mod RW {}
227 }
228
229 /// Capture/compare preloaded control
230 pub mod CCPC {
231 /// Offset (0 bits)
232 pub const offset: u32 = 0;
233 /// Mask (1 bit: 1 << 0)
234 pub const mask: u32 = 1 << offset;
235 /// Read-only values (empty)
236 pub mod R {}
237 /// Write-only values (empty)
238 pub mod W {}
239 /// Read-write values (empty)
240 pub mod RW {}
241 }
242}
243
244/// slave mode control register
245pub mod SMCR {
246
247 /// Master/Slave mode
248 pub mod MSM {
249 /// Offset (7 bits)
250 pub const offset: u32 = 7;
251 /// Mask (1 bit: 1 << 7)
252 pub const mask: u32 = 1 << offset;
253 /// Read-only values (empty)
254 pub mod R {}
255 /// Write-only values (empty)
256 pub mod W {}
257 /// Read-write values (empty)
258 pub mod RW {}
259 }
260
261 /// Trigger selection
262 pub mod TS {
263 /// Offset (4 bits)
264 pub const offset: u32 = 4;
265 /// Mask (3 bits: 0b111 << 4)
266 pub const mask: u32 = 0b111 << offset;
267 /// Read-only values (empty)
268 pub mod R {}
269 /// Write-only values (empty)
270 pub mod W {}
271 /// Read-write values (empty)
272 pub mod RW {}
273 }
274
275 /// Slave mode selection
276 pub mod SMS {
277 /// Offset (0 bits)
278 pub const offset: u32 = 0;
279 /// Mask (3 bits: 0b111 << 0)
280 pub const mask: u32 = 0b111 << offset;
281 /// Read-only values (empty)
282 pub mod R {}
283 /// Write-only values (empty)
284 pub mod W {}
285 /// Read-write values (empty)
286 pub mod RW {}
287 }
288}
289
290/// DMA/Interrupt enable register
291pub mod DIER {
292
293 /// Trigger DMA request enable
294 pub mod TDE {
295 /// Offset (14 bits)
296 pub const offset: u32 = 14;
297 /// Mask (1 bit: 1 << 14)
298 pub const mask: u32 = 1 << offset;
299 /// Read-only values (empty)
300 pub mod R {}
301 /// Write-only values (empty)
302 pub mod W {}
303 /// Read-write values (empty)
304 pub mod RW {}
305 }
306
307 /// Capture/Compare 2 DMA request enable
308 pub mod CC2DE {
309 /// Offset (10 bits)
310 pub const offset: u32 = 10;
311 /// Mask (1 bit: 1 << 10)
312 pub const mask: u32 = 1 << offset;
313 /// Read-only values (empty)
314 pub mod R {}
315 /// Write-only values (empty)
316 pub mod W {}
317 /// Read-write values (empty)
318 pub mod RW {}
319 }
320
321 /// Capture/Compare 1 DMA request enable
322 pub mod CC1DE {
323 /// Offset (9 bits)
324 pub const offset: u32 = 9;
325 /// Mask (1 bit: 1 << 9)
326 pub const mask: u32 = 1 << offset;
327 /// Read-only values (empty)
328 pub mod R {}
329 /// Write-only values (empty)
330 pub mod W {}
331 /// Read-write values (empty)
332 pub mod RW {}
333 }
334
335 /// Update DMA request enable
336 pub mod UDE {
337 /// Offset (8 bits)
338 pub const offset: u32 = 8;
339 /// Mask (1 bit: 1 << 8)
340 pub const mask: u32 = 1 << offset;
341 /// Read-only values (empty)
342 pub mod R {}
343 /// Write-only values (empty)
344 pub mod W {}
345 /// Read-write values (empty)
346 pub mod RW {}
347 }
348
349 /// Break interrupt enable
350 pub mod BIE {
351 /// Offset (7 bits)
352 pub const offset: u32 = 7;
353 /// Mask (1 bit: 1 << 7)
354 pub const mask: u32 = 1 << offset;
355 /// Read-only values (empty)
356 pub mod R {}
357 /// Write-only values (empty)
358 pub mod W {}
359 /// Read-write values (empty)
360 pub mod RW {}
361 }
362
363 /// Trigger interrupt enable
364 pub mod TIE {
365 /// Offset (6 bits)
366 pub const offset: u32 = 6;
367 /// Mask (1 bit: 1 << 6)
368 pub const mask: u32 = 1 << offset;
369 /// Read-only values (empty)
370 pub mod R {}
371 /// Write-only values (empty)
372 pub mod W {}
373 /// Read-write values (empty)
374 pub mod RW {}
375 }
376
377 /// COM interrupt enable
378 pub mod COMIE {
379 /// Offset (5 bits)
380 pub const offset: u32 = 5;
381 /// Mask (1 bit: 1 << 5)
382 pub const mask: u32 = 1 << offset;
383 /// Read-only values (empty)
384 pub mod R {}
385 /// Write-only values (empty)
386 pub mod W {}
387 /// Read-write values (empty)
388 pub mod RW {}
389 }
390
391 /// Capture/Compare 2 interrupt enable
392 pub mod CC2IE {
393 /// Offset (2 bits)
394 pub const offset: u32 = 2;
395 /// Mask (1 bit: 1 << 2)
396 pub const mask: u32 = 1 << offset;
397 /// Read-only values (empty)
398 pub mod R {}
399 /// Write-only values (empty)
400 pub mod W {}
401 /// Read-write values (empty)
402 pub mod RW {}
403 }
404
405 /// Capture/Compare 1 interrupt enable
406 pub mod CC1IE {
407 /// Offset (1 bits)
408 pub const offset: u32 = 1;
409 /// Mask (1 bit: 1 << 1)
410 pub const mask: u32 = 1 << offset;
411 /// Read-only values (empty)
412 pub mod R {}
413 /// Write-only values (empty)
414 pub mod W {}
415 /// Read-write values (empty)
416 pub mod RW {}
417 }
418
419 /// Update interrupt enable
420 pub mod UIE {
421 /// Offset (0 bits)
422 pub const offset: u32 = 0;
423 /// Mask (1 bit: 1 << 0)
424 pub const mask: u32 = 1 << offset;
425 /// Read-only values (empty)
426 pub mod R {}
427 /// Write-only values (empty)
428 pub mod W {}
429 /// Read-write values
430 pub mod RW {
431
432 /// 0b0: Update interrupt disabled
433 pub const Disabled: u32 = 0b0;
434
435 /// 0b1: Update interrupt enabled
436 pub const Enabled: u32 = 0b1;
437 }
438 }
439}
440
441/// status register
442pub mod SR {
443
444 /// Capture/compare 2 overcapture flag
445 pub mod CC2OF {
446 /// Offset (10 bits)
447 pub const offset: u32 = 10;
448 /// Mask (1 bit: 1 << 10)
449 pub const mask: u32 = 1 << offset;
450 /// Read-only values (empty)
451 pub mod R {}
452 /// Write-only values (empty)
453 pub mod W {}
454 /// Read-write values (empty)
455 pub mod RW {}
456 }
457
458 /// Capture/Compare 1 overcapture flag
459 pub mod CC1OF {
460 /// Offset (9 bits)
461 pub const offset: u32 = 9;
462 /// Mask (1 bit: 1 << 9)
463 pub const mask: u32 = 1 << offset;
464 /// Read-only values (empty)
465 pub mod R {}
466 /// Write-only values (empty)
467 pub mod W {}
468 /// Read-write values (empty)
469 pub mod RW {}
470 }
471
472 /// Break interrupt flag
473 pub mod BIF {
474 /// Offset (7 bits)
475 pub const offset: u32 = 7;
476 /// Mask (1 bit: 1 << 7)
477 pub const mask: u32 = 1 << offset;
478 /// Read-only values (empty)
479 pub mod R {}
480 /// Write-only values (empty)
481 pub mod W {}
482 /// Read-write values (empty)
483 pub mod RW {}
484 }
485
486 /// Trigger interrupt flag
487 pub mod TIF {
488 /// Offset (6 bits)
489 pub const offset: u32 = 6;
490 /// Mask (1 bit: 1 << 6)
491 pub const mask: u32 = 1 << offset;
492 /// Read-only values (empty)
493 pub mod R {}
494 /// Write-only values (empty)
495 pub mod W {}
496 /// Read-write values (empty)
497 pub mod RW {}
498 }
499
500 /// COM interrupt flag
501 pub mod COMIF {
502 /// Offset (5 bits)
503 pub const offset: u32 = 5;
504 /// Mask (1 bit: 1 << 5)
505 pub const mask: u32 = 1 << offset;
506 /// Read-only values (empty)
507 pub mod R {}
508 /// Write-only values (empty)
509 pub mod W {}
510 /// Read-write values (empty)
511 pub mod RW {}
512 }
513
514 /// Capture/Compare 2 interrupt flag
515 pub mod CC2IF {
516 /// Offset (2 bits)
517 pub const offset: u32 = 2;
518 /// Mask (1 bit: 1 << 2)
519 pub const mask: u32 = 1 << offset;
520 /// Read-only values (empty)
521 pub mod R {}
522 /// Write-only values (empty)
523 pub mod W {}
524 /// Read-write values (empty)
525 pub mod RW {}
526 }
527
528 /// Capture/compare 1 interrupt flag
529 pub mod CC1IF {
530 /// Offset (1 bits)
531 pub const offset: u32 = 1;
532 /// Mask (1 bit: 1 << 1)
533 pub const mask: u32 = 1 << offset;
534 /// Read-only values (empty)
535 pub mod R {}
536 /// Write-only values (empty)
537 pub mod W {}
538 /// Read-write values (empty)
539 pub mod RW {}
540 }
541
542 /// Update interrupt flag
543 pub mod UIF {
544 /// Offset (0 bits)
545 pub const offset: u32 = 0;
546 /// Mask (1 bit: 1 << 0)
547 pub const mask: u32 = 1 << offset;
548 /// Read-only values (empty)
549 pub mod R {}
550 /// Write-only values (empty)
551 pub mod W {}
552 /// Read-write values
553 pub mod RW {
554
555 /// 0b0: No update occurred
556 pub const Clear: u32 = 0b0;
557
558 /// 0b1: Update interrupt pending.
559 pub const UpdatePending: u32 = 0b1;
560 }
561 }
562}
563
564/// event generation register
565pub mod EGR {
566
567 /// Break generation
568 pub mod BG {
569 /// Offset (7 bits)
570 pub const offset: u32 = 7;
571 /// Mask (1 bit: 1 << 7)
572 pub const mask: u32 = 1 << offset;
573 /// Read-only values (empty)
574 pub mod R {}
575 /// Write-only values (empty)
576 pub mod W {}
577 /// Read-write values (empty)
578 pub mod RW {}
579 }
580
581 /// Trigger generation
582 pub mod TG {
583 /// Offset (6 bits)
584 pub const offset: u32 = 6;
585 /// Mask (1 bit: 1 << 6)
586 pub const mask: u32 = 1 << offset;
587 /// Read-only values (empty)
588 pub mod R {}
589 /// Write-only values (empty)
590 pub mod W {}
591 /// Read-write values (empty)
592 pub mod RW {}
593 }
594
595 /// Capture/Compare control update generation
596 pub mod COMG {
597 /// Offset (5 bits)
598 pub const offset: u32 = 5;
599 /// Mask (1 bit: 1 << 5)
600 pub const mask: u32 = 1 << offset;
601 /// Read-only values (empty)
602 pub mod R {}
603 /// Write-only values (empty)
604 pub mod W {}
605 /// Read-write values (empty)
606 pub mod RW {}
607 }
608
609 /// Capture/compare 2 generation
610 pub mod CC2G {
611 /// Offset (2 bits)
612 pub const offset: u32 = 2;
613 /// Mask (1 bit: 1 << 2)
614 pub const mask: u32 = 1 << offset;
615 /// Read-only values (empty)
616 pub mod R {}
617 /// Write-only values (empty)
618 pub mod W {}
619 /// Read-write values (empty)
620 pub mod RW {}
621 }
622
623 /// Capture/compare 1 generation
624 pub mod CC1G {
625 /// Offset (1 bits)
626 pub const offset: u32 = 1;
627 /// Mask (1 bit: 1 << 1)
628 pub const mask: u32 = 1 << offset;
629 /// Read-only values (empty)
630 pub mod R {}
631 /// Write-only values (empty)
632 pub mod W {}
633 /// Read-write values (empty)
634 pub mod RW {}
635 }
636
637 /// Update generation
638 pub mod UG {
639 /// Offset (0 bits)
640 pub const offset: u32 = 0;
641 /// Mask (1 bit: 1 << 0)
642 pub const mask: u32 = 1 << offset;
643 /// Read-only values (empty)
644 pub mod R {}
645 /// Write-only values
646 pub mod W {
647
648 /// 0b1: Re-initializes the timer counter and generates an update of the registers.
649 pub const Update: u32 = 0b1;
650 }
651 /// Read-write values (empty)
652 pub mod RW {}
653 }
654}
655
656/// CCMR1_Output and CCMR1_Input
657/// CCMR1_Output: capture/compare mode register (output mode)
658/// CCMR1_Input: capture/compare mode register 1 (input mode)
659pub mod CCMR1 {
660
661 /// Output Compare 2 mode
662 pub mod OC2M {
663 /// Offset (12 bits)
664 pub const offset: u32 = 12;
665 /// Mask (3 bits: 0b111 << 12)
666 pub const mask: u32 = 0b111 << offset;
667 /// Read-only values (empty)
668 pub mod R {}
669 /// Write-only values (empty)
670 pub mod W {}
671 /// Read-write values
672 pub mod RW {
673
674 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
675 pub const Frozen: u32 = 0b000;
676
677 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
678 pub const ActiveOnMatch: u32 = 0b001;
679
680 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
681 pub const InactiveOnMatch: u32 = 0b010;
682
683 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy
684 pub const Toggle: u32 = 0b011;
685
686 /// 0b100: OCyREF is forced low
687 pub const ForceInactive: u32 = 0b100;
688
689 /// 0b101: OCyREF is forced high
690 pub const ForceActive: u32 = 0b101;
691
692 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
693 pub const PwmMode1: u32 = 0b110;
694
695 /// 0b111: Inversely to PwmMode1
696 pub const PwmMode2: u32 = 0b111;
697 }
698 }
699
700 /// Output Compare 2 preload enable
701 pub mod OC2PE {
702 /// Offset (11 bits)
703 pub const offset: u32 = 11;
704 /// Mask (1 bit: 1 << 11)
705 pub const mask: u32 = 1 << offset;
706 /// Read-only values (empty)
707 pub mod R {}
708 /// Write-only values (empty)
709 pub mod W {}
710 /// Read-write values (empty)
711 pub mod RW {}
712 }
713
714 /// Output Compare 2 fast enable
715 pub mod OC2FE {
716 /// Offset (10 bits)
717 pub const offset: u32 = 10;
718 /// Mask (1 bit: 1 << 10)
719 pub const mask: u32 = 1 << offset;
720 /// Read-only values (empty)
721 pub mod R {}
722 /// Write-only values (empty)
723 pub mod W {}
724 /// Read-write values (empty)
725 pub mod RW {}
726 }
727
728 /// Capture/Compare 2 selection
729 pub mod CC2S {
730 /// Offset (8 bits)
731 pub const offset: u32 = 8;
732 /// Mask (2 bits: 0b11 << 8)
733 pub const mask: u32 = 0b11 << offset;
734 /// Read-only values (empty)
735 pub mod R {}
736 /// Write-only values (empty)
737 pub mod W {}
738 /// Read-write values (empty)
739 pub mod RW {}
740 }
741
742 /// Output Compare 1 mode
743 pub mod OC1M {
744 /// Offset (4 bits)
745 pub const offset: u32 = 4;
746 /// Mask (3 bits: 0b111 << 4)
747 pub const mask: u32 = 0b111 << offset;
748 /// Read-only values (empty)
749 pub mod R {}
750 /// Write-only values (empty)
751 pub mod W {}
752 pub use super::OC2M::RW;
753 }
754
755 /// Output Compare 1 preload enable
756 pub mod OC1PE {
757 /// Offset (3 bits)
758 pub const offset: u32 = 3;
759 /// Mask (1 bit: 1 << 3)
760 pub const mask: u32 = 1 << offset;
761 /// Read-only values (empty)
762 pub mod R {}
763 /// Write-only values (empty)
764 pub mod W {}
765 /// Read-write values (empty)
766 pub mod RW {}
767 }
768
769 /// Output Compare 1 fast enable
770 pub mod OC1FE {
771 /// Offset (2 bits)
772 pub const offset: u32 = 2;
773 /// Mask (1 bit: 1 << 2)
774 pub const mask: u32 = 1 << offset;
775 /// Read-only values (empty)
776 pub mod R {}
777 /// Write-only values (empty)
778 pub mod W {}
779 /// Read-write values (empty)
780 pub mod RW {}
781 }
782
783 /// Capture/Compare 1 selection
784 pub mod CC1S {
785 /// Offset (0 bits)
786 pub const offset: u32 = 0;
787 /// Mask (2 bits: 0b11 << 0)
788 pub const mask: u32 = 0b11 << offset;
789 /// Read-only values (empty)
790 pub mod R {}
791 /// Write-only values (empty)
792 pub mod W {}
793 /// Read-write values (empty)
794 pub mod RW {}
795 }
796
797 /// Input capture 2 filter
798 pub mod IC2F {
799 /// Offset (12 bits)
800 pub const offset: u32 = 12;
801 /// Mask (4 bits: 0b1111 << 12)
802 pub const mask: u32 = 0b1111 << offset;
803 /// Read-only values (empty)
804 pub mod R {}
805 /// Write-only values (empty)
806 pub mod W {}
807 /// Read-write values (empty)
808 pub mod RW {}
809 }
810
811 /// Input capture 2 prescaler
812 pub mod IC2PSC {
813 /// Offset (10 bits)
814 pub const offset: u32 = 10;
815 /// Mask (2 bits: 0b11 << 10)
816 pub const mask: u32 = 0b11 << offset;
817 /// Read-only values (empty)
818 pub mod R {}
819 /// Write-only values (empty)
820 pub mod W {}
821 /// Read-write values (empty)
822 pub mod RW {}
823 }
824
825 /// Input capture 1 filter
826 pub mod IC1F {
827 /// Offset (4 bits)
828 pub const offset: u32 = 4;
829 /// Mask (4 bits: 0b1111 << 4)
830 pub const mask: u32 = 0b1111 << offset;
831 /// Read-only values (empty)
832 pub mod R {}
833 /// Write-only values (empty)
834 pub mod W {}
835 /// Read-write values (empty)
836 pub mod RW {}
837 }
838
839 /// Input capture 1 prescaler
840 pub mod IC1PSC {
841 /// Offset (2 bits)
842 pub const offset: u32 = 2;
843 /// Mask (2 bits: 0b11 << 2)
844 pub const mask: u32 = 0b11 << offset;
845 /// Read-only values (empty)
846 pub mod R {}
847 /// Write-only values (empty)
848 pub mod W {}
849 /// Read-write values (empty)
850 pub mod RW {}
851 }
852}
853
854/// capture/compare enable register
855pub mod CCER {
856
857 /// Capture/Compare 2 output Polarity
858 pub mod CC2NP {
859 /// Offset (7 bits)
860 pub const offset: u32 = 7;
861 /// Mask (1 bit: 1 << 7)
862 pub const mask: u32 = 1 << offset;
863 /// Read-only values (empty)
864 pub mod R {}
865 /// Write-only values (empty)
866 pub mod W {}
867 /// Read-write values (empty)
868 pub mod RW {}
869 }
870
871 /// Capture/Compare 2 output Polarity
872 pub mod CC2P {
873 /// Offset (5 bits)
874 pub const offset: u32 = 5;
875 /// Mask (1 bit: 1 << 5)
876 pub const mask: u32 = 1 << offset;
877 /// Read-only values (empty)
878 pub mod R {}
879 /// Write-only values (empty)
880 pub mod W {}
881 /// Read-write values (empty)
882 pub mod RW {}
883 }
884
885 /// Capture/Compare 2 output enable
886 pub mod CC2E {
887 /// Offset (4 bits)
888 pub const offset: u32 = 4;
889 /// Mask (1 bit: 1 << 4)
890 pub const mask: u32 = 1 << offset;
891 /// Read-only values (empty)
892 pub mod R {}
893 /// Write-only values (empty)
894 pub mod W {}
895 /// Read-write values (empty)
896 pub mod RW {}
897 }
898
899 /// Capture/Compare 1 output Polarity
900 pub mod CC1NP {
901 /// Offset (3 bits)
902 pub const offset: u32 = 3;
903 /// Mask (1 bit: 1 << 3)
904 pub const mask: u32 = 1 << offset;
905 /// Read-only values (empty)
906 pub mod R {}
907 /// Write-only values (empty)
908 pub mod W {}
909 /// Read-write values (empty)
910 pub mod RW {}
911 }
912
913 /// Capture/Compare 1 complementary output enable
914 pub mod CC1NE {
915 /// Offset (2 bits)
916 pub const offset: u32 = 2;
917 /// Mask (1 bit: 1 << 2)
918 pub const mask: u32 = 1 << offset;
919 /// Read-only values (empty)
920 pub mod R {}
921 /// Write-only values (empty)
922 pub mod W {}
923 /// Read-write values (empty)
924 pub mod RW {}
925 }
926
927 /// Capture/Compare 1 output Polarity
928 pub mod CC1P {
929 /// Offset (1 bits)
930 pub const offset: u32 = 1;
931 /// Mask (1 bit: 1 << 1)
932 pub const mask: u32 = 1 << offset;
933 /// Read-only values (empty)
934 pub mod R {}
935 /// Write-only values (empty)
936 pub mod W {}
937 /// Read-write values (empty)
938 pub mod RW {}
939 }
940
941 /// Capture/Compare 1 output enable
942 pub mod CC1E {
943 /// Offset (0 bits)
944 pub const offset: u32 = 0;
945 /// Mask (1 bit: 1 << 0)
946 pub const mask: u32 = 1 << offset;
947 /// Read-only values (empty)
948 pub mod R {}
949 /// Write-only values (empty)
950 pub mod W {}
951 /// Read-write values (empty)
952 pub mod RW {}
953 }
954}
955
956/// counter
957pub mod CNT {
958
959 /// counter value
960 pub mod CNT {
961 /// Offset (0 bits)
962 pub const offset: u32 = 0;
963 /// Mask (16 bits: 0xffff << 0)
964 pub const mask: u32 = 0xffff << offset;
965 /// Read-only values (empty)
966 pub mod R {}
967 /// Write-only values (empty)
968 pub mod W {}
969 /// Read-write values (empty)
970 pub mod RW {}
971 }
972}
973
974/// prescaler
975pub mod PSC {
976
977 /// Prescaler value
978 pub mod PSC {
979 /// Offset (0 bits)
980 pub const offset: u32 = 0;
981 /// Mask (16 bits: 0xffff << 0)
982 pub const mask: u32 = 0xffff << offset;
983 /// Read-only values (empty)
984 pub mod R {}
985 /// Write-only values (empty)
986 pub mod W {}
987 /// Read-write values (empty)
988 pub mod RW {}
989 }
990}
991
992/// auto-reload register
993pub mod ARR {
994
995 /// Auto-reload value
996 pub mod ARR {
997 /// Offset (0 bits)
998 pub const offset: u32 = 0;
999 /// Mask (16 bits: 0xffff << 0)
1000 pub const mask: u32 = 0xffff << offset;
1001 /// Read-only values (empty)
1002 pub mod R {}
1003 /// Write-only values (empty)
1004 pub mod W {}
1005 /// Read-write values (empty)
1006 pub mod RW {}
1007 }
1008}
1009
1010/// repetition counter register
1011pub mod RCR {
1012
1013 /// Repetition counter value
1014 pub mod REP {
1015 /// Offset (0 bits)
1016 pub const offset: u32 = 0;
1017 /// Mask (8 bits: 0xff << 0)
1018 pub const mask: u32 = 0xff << offset;
1019 /// Read-only values (empty)
1020 pub mod R {}
1021 /// Write-only values (empty)
1022 pub mod W {}
1023 /// Read-write values (empty)
1024 pub mod RW {}
1025 }
1026}
1027
1028/// capture/compare register
1029pub mod CCR1 {
1030
1031 /// Capture/Compare value
1032 pub mod CCR {
1033 /// Offset (0 bits)
1034 pub const offset: u32 = 0;
1035 /// Mask (16 bits: 0xffff << 0)
1036 pub const mask: u32 = 0xffff << offset;
1037 /// Read-only values (empty)
1038 pub mod R {}
1039 /// Write-only values (empty)
1040 pub mod W {}
1041 /// Read-write values (empty)
1042 pub mod RW {}
1043 }
1044}
1045
1046/// capture/compare register
1047pub mod CCR2 {
1048 pub use super::CCR1::CCR;
1049}
1050
1051/// break and dead-time register
1052pub mod BDTR {
1053
1054 /// Main output enable
1055 pub mod MOE {
1056 /// Offset (15 bits)
1057 pub const offset: u32 = 15;
1058 /// Mask (1 bit: 1 << 15)
1059 pub const mask: u32 = 1 << offset;
1060 /// Read-only values (empty)
1061 pub mod R {}
1062 /// Write-only values (empty)
1063 pub mod W {}
1064 /// Read-write values (empty)
1065 pub mod RW {}
1066 }
1067
1068 /// Automatic output enable
1069 pub mod AOE {
1070 /// Offset (14 bits)
1071 pub const offset: u32 = 14;
1072 /// Mask (1 bit: 1 << 14)
1073 pub const mask: u32 = 1 << offset;
1074 /// Read-only values (empty)
1075 pub mod R {}
1076 /// Write-only values (empty)
1077 pub mod W {}
1078 /// Read-write values (empty)
1079 pub mod RW {}
1080 }
1081
1082 /// Break polarity
1083 pub mod BKP {
1084 /// Offset (13 bits)
1085 pub const offset: u32 = 13;
1086 /// Mask (1 bit: 1 << 13)
1087 pub const mask: u32 = 1 << offset;
1088 /// Read-only values (empty)
1089 pub mod R {}
1090 /// Write-only values (empty)
1091 pub mod W {}
1092 /// Read-write values (empty)
1093 pub mod RW {}
1094 }
1095
1096 /// Break enable
1097 pub mod BKE {
1098 /// Offset (12 bits)
1099 pub const offset: u32 = 12;
1100 /// Mask (1 bit: 1 << 12)
1101 pub const mask: u32 = 1 << offset;
1102 /// Read-only values (empty)
1103 pub mod R {}
1104 /// Write-only values (empty)
1105 pub mod W {}
1106 /// Read-write values (empty)
1107 pub mod RW {}
1108 }
1109
1110 /// Off-state selection for Run mode
1111 pub mod OSSR {
1112 /// Offset (11 bits)
1113 pub const offset: u32 = 11;
1114 /// Mask (1 bit: 1 << 11)
1115 pub const mask: u32 = 1 << offset;
1116 /// Read-only values (empty)
1117 pub mod R {}
1118 /// Write-only values (empty)
1119 pub mod W {}
1120 /// Read-write values (empty)
1121 pub mod RW {}
1122 }
1123
1124 /// Off-state selection for Idle mode
1125 pub mod OSSI {
1126 /// Offset (10 bits)
1127 pub const offset: u32 = 10;
1128 /// Mask (1 bit: 1 << 10)
1129 pub const mask: u32 = 1 << offset;
1130 /// Read-only values (empty)
1131 pub mod R {}
1132 /// Write-only values (empty)
1133 pub mod W {}
1134 /// Read-write values (empty)
1135 pub mod RW {}
1136 }
1137
1138 /// Lock configuration
1139 pub mod LOCK {
1140 /// Offset (8 bits)
1141 pub const offset: u32 = 8;
1142 /// Mask (2 bits: 0b11 << 8)
1143 pub const mask: u32 = 0b11 << offset;
1144 /// Read-only values (empty)
1145 pub mod R {}
1146 /// Write-only values (empty)
1147 pub mod W {}
1148 /// Read-write values (empty)
1149 pub mod RW {}
1150 }
1151
1152 /// Dead-time generator setup
1153 pub mod DTG {
1154 /// Offset (0 bits)
1155 pub const offset: u32 = 0;
1156 /// Mask (8 bits: 0xff << 0)
1157 pub const mask: u32 = 0xff << offset;
1158 /// Read-only values (empty)
1159 pub mod R {}
1160 /// Write-only values (empty)
1161 pub mod W {}
1162 /// Read-write values (empty)
1163 pub mod RW {}
1164 }
1165}
1166
1167/// DMA control register
1168pub mod DCR {
1169
1170 /// DMA burst length
1171 pub mod DBL {
1172 /// Offset (8 bits)
1173 pub const offset: u32 = 8;
1174 /// Mask (5 bits: 0b11111 << 8)
1175 pub const mask: u32 = 0b11111 << offset;
1176 /// Read-only values (empty)
1177 pub mod R {}
1178 /// Write-only values (empty)
1179 pub mod W {}
1180 /// Read-write values (empty)
1181 pub mod RW {}
1182 }
1183
1184 /// DMA base address
1185 pub mod DBA {
1186 /// Offset (0 bits)
1187 pub const offset: u32 = 0;
1188 /// Mask (5 bits: 0b11111 << 0)
1189 pub const mask: u32 = 0b11111 << offset;
1190 /// Read-only values (empty)
1191 pub mod R {}
1192 /// Write-only values (empty)
1193 pub mod W {}
1194 /// Read-write values (empty)
1195 pub mod RW {}
1196 }
1197}
1198
1199/// DMA address for full transfer
1200pub mod DMAR {
1201
1202 /// DMA register for burst accesses
1203 pub mod DMAB {
1204 /// Offset (0 bits)
1205 pub const offset: u32 = 0;
1206 /// Mask (16 bits: 0xffff << 0)
1207 pub const mask: u32 = 0xffff << offset;
1208 /// Read-only values (empty)
1209 pub mod R {}
1210 /// Write-only values (empty)
1211 pub mod W {}
1212 /// Read-write values (empty)
1213 pub mod RW {}
1214 }
1215}
1216#[repr(C)]
1217pub struct RegisterBlock {
1218 /// control register 1
1219 pub CR1: RWRegister<u32>,
1220
1221 /// control register 2
1222 pub CR2: RWRegister<u32>,
1223
1224 /// slave mode control register
1225 pub SMCR: RWRegister<u32>,
1226
1227 /// DMA/Interrupt enable register
1228 pub DIER: RWRegister<u32>,
1229
1230 /// status register
1231 pub SR: RWRegister<u32>,
1232
1233 /// event generation register
1234 pub EGR: WORegister<u32>,
1235
1236 /// CCMR1_Output and CCMR1_Input
1237 /// CCMR1_Output: capture/compare mode register (output mode)
1238 /// CCMR1_Input: capture/compare mode register 1 (input mode)
1239 pub CCMR1: RWRegister<u32>,
1240
1241 _reserved1: [u8; 4],
1242
1243 /// capture/compare enable register
1244 pub CCER: RWRegister<u32>,
1245
1246 /// counter
1247 pub CNT: RWRegister<u32>,
1248
1249 /// prescaler
1250 pub PSC: RWRegister<u32>,
1251
1252 /// auto-reload register
1253 pub ARR: RWRegister<u32>,
1254
1255 /// repetition counter register
1256 pub RCR: RWRegister<u32>,
1257
1258 /// capture/compare register
1259 pub CCR1: RWRegister<u32>,
1260
1261 /// capture/compare register
1262 pub CCR2: RWRegister<u32>,
1263
1264 _reserved2: [u8; 8],
1265
1266 /// break and dead-time register
1267 pub BDTR: RWRegister<u32>,
1268
1269 /// DMA control register
1270 pub DCR: RWRegister<u32>,
1271
1272 /// DMA address for full transfer
1273 pub DMAR: RWRegister<u32>,
1274}
1275pub struct ResetValues {
1276 pub CR1: u32,
1277 pub CR2: u32,
1278 pub SMCR: u32,
1279 pub DIER: u32,
1280 pub SR: u32,
1281 pub EGR: u32,
1282 pub CCMR1: u32,
1283 pub CCER: u32,
1284 pub CNT: u32,
1285 pub PSC: u32,
1286 pub ARR: u32,
1287 pub RCR: u32,
1288 pub CCR1: u32,
1289 pub CCR2: u32,
1290 pub BDTR: u32,
1291 pub DCR: u32,
1292 pub DMAR: u32,
1293}
1294#[cfg(not(feature = "nosync"))]
1295pub struct Instance {
1296 pub(crate) addr: u32,
1297 pub(crate) _marker: PhantomData<*const RegisterBlock>,
1298}
1299#[cfg(not(feature = "nosync"))]
1300impl ::core::ops::Deref for Instance {
1301 type Target = RegisterBlock;
1302 #[inline(always)]
1303 fn deref(&self) -> &RegisterBlock {
1304 unsafe { &*(self.addr as *const _) }
1305 }
1306}
1307#[cfg(feature = "rtic")]
1308unsafe impl Send for Instance {}
1309
1310/// Access functions for the TIM15 peripheral instance
1311pub mod TIM15 {
1312 use super::ResetValues;
1313
1314 #[cfg(not(feature = "nosync"))]
1315 use super::Instance;
1316
1317 #[cfg(not(feature = "nosync"))]
1318 const INSTANCE: Instance = Instance {
1319 addr: 0x40014000,
1320 _marker: ::core::marker::PhantomData,
1321 };
1322
1323 /// Reset values for each field in TIM15
1324 pub const reset: ResetValues = ResetValues {
1325 CR1: 0x00000000,
1326 CR2: 0x00000000,
1327 SMCR: 0x00000000,
1328 DIER: 0x00000000,
1329 SR: 0x00000000,
1330 EGR: 0x00000000,
1331 CCMR1: 0x00000000,
1332 CCER: 0x00000000,
1333 CNT: 0x00000000,
1334 PSC: 0x00000000,
1335 ARR: 0x00000000,
1336 RCR: 0x00000000,
1337 CCR1: 0x00000000,
1338 CCR2: 0x00000000,
1339 BDTR: 0x00000000,
1340 DCR: 0x00000000,
1341 DMAR: 0x00000000,
1342 };
1343
1344 #[cfg(not(feature = "nosync"))]
1345 #[allow(renamed_and_removed_lints)]
1346 #[allow(private_no_mangle_statics)]
1347 #[no_mangle]
1348 static mut TIM15_TAKEN: bool = false;
1349
1350 /// Safe access to TIM15
1351 ///
1352 /// This function returns `Some(Instance)` if this instance is not
1353 /// currently taken, and `None` if it is. This ensures that if you
1354 /// do get `Some(Instance)`, you are ensured unique access to
1355 /// the peripheral and there cannot be data races (unless other
1356 /// code uses `unsafe`, of course). You can then pass the
1357 /// `Instance` around to other functions as required. When you're
1358 /// done with it, you can call `release(instance)` to return it.
1359 ///
1360 /// `Instance` itself dereferences to a `RegisterBlock`, which
1361 /// provides access to the peripheral's registers.
1362 #[cfg(not(feature = "nosync"))]
1363 #[inline]
1364 pub fn take() -> Option<Instance> {
1365 external_cortex_m::interrupt::free(|_| unsafe {
1366 if TIM15_TAKEN {
1367 None
1368 } else {
1369 TIM15_TAKEN = true;
1370 Some(INSTANCE)
1371 }
1372 })
1373 }
1374
1375 /// Release exclusive access to TIM15
1376 ///
1377 /// This function allows you to return an `Instance` so that it
1378 /// is available to `take()` again. This function will panic if
1379 /// you return a different `Instance` or if this instance is not
1380 /// already taken.
1381 #[cfg(not(feature = "nosync"))]
1382 #[inline]
1383 pub fn release(inst: Instance) {
1384 external_cortex_m::interrupt::free(|_| unsafe {
1385 if TIM15_TAKEN && inst.addr == INSTANCE.addr {
1386 TIM15_TAKEN = false;
1387 } else {
1388 panic!("Released a peripheral which was not taken");
1389 }
1390 });
1391 }
1392
1393 /// Unsafely steal TIM15
1394 ///
1395 /// This function is similar to take() but forcibly takes the
1396 /// Instance, marking it as taken irregardless of its previous
1397 /// state.
1398 #[cfg(not(feature = "nosync"))]
1399 #[inline]
1400 pub unsafe fn steal() -> Instance {
1401 TIM15_TAKEN = true;
1402 INSTANCE
1403 }
1404}
1405
1406/// Raw pointer to TIM15
1407///
1408/// Dereferencing this is unsafe because you are not ensured unique
1409/// access to the peripheral, so you may encounter data races with
1410/// other users of this peripheral. It is up to you to ensure you
1411/// will not cause data races.
1412///
1413/// This constant is provided for ease of use in unsafe code: you can
1414/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
1415pub const TIM15: *const RegisterBlock = 0x40014000 as *const _;