stm32ral/stm32f3/stm32f301/dac1.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Digital-to-analog converter
4
5use crate::{RORegister, RWRegister, WORegister};
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// control register
10pub mod CR {
11
12 /// DAC channel2 DMA underrun interrupt enable
13 pub mod DMAUDRIE2 {
14 /// Offset (29 bits)
15 pub const offset: u32 = 29;
16 /// Mask (1 bit: 1 << 29)
17 pub const mask: u32 = 1 << offset;
18 /// Read-only values (empty)
19 pub mod R {}
20 /// Write-only values (empty)
21 pub mod W {}
22 /// Read-write values
23 pub mod RW {
24
25 /// 0b0: DAC channel X DMA Underrun Interrupt disabled
26 pub const Disabled: u32 = 0b0;
27
28 /// 0b1: DAC channel X DMA Underrun Interrupt enabled
29 pub const Enabled: u32 = 0b1;
30 }
31 }
32
33 /// DAC channel2 DMA enable
34 pub mod DMAEN2 {
35 /// Offset (28 bits)
36 pub const offset: u32 = 28;
37 /// Mask (1 bit: 1 << 28)
38 pub const mask: u32 = 1 << offset;
39 /// Read-only values (empty)
40 pub mod R {}
41 /// Write-only values (empty)
42 pub mod W {}
43 /// Read-write values
44 pub mod RW {
45
46 /// 0b0: DAC channel X DMA mode disabled
47 pub const Disabled: u32 = 0b0;
48
49 /// 0b1: DAC channel X DMA mode enabled
50 pub const Enabled: u32 = 0b1;
51 }
52 }
53
54 /// DAC channel2 mask/amplitude selector
55 pub mod MAMP2 {
56 /// Offset (24 bits)
57 pub const offset: u32 = 24;
58 /// Mask (4 bits: 0b1111 << 24)
59 pub const mask: u32 = 0b1111 << offset;
60 /// Read-only values (empty)
61 pub mod R {}
62 /// Write-only values (empty)
63 pub mod W {}
64 /// Read-write values (empty)
65 pub mod RW {}
66 }
67
68 /// DAC channel2 noise/triangle wave generation enable
69 pub mod WAVE2 {
70 /// Offset (22 bits)
71 pub const offset: u32 = 22;
72 /// Mask (2 bits: 0b11 << 22)
73 pub const mask: u32 = 0b11 << offset;
74 /// Read-only values (empty)
75 pub mod R {}
76 /// Write-only values (empty)
77 pub mod W {}
78 /// Read-write values (empty)
79 pub mod RW {}
80 }
81
82 /// DAC channel2 trigger selection
83 pub mod TSEL2 {
84 /// Offset (19 bits)
85 pub const offset: u32 = 19;
86 /// Mask (3 bits: 0b111 << 19)
87 pub const mask: u32 = 0b111 << offset;
88 /// Read-only values (empty)
89 pub mod R {}
90 /// Write-only values (empty)
91 pub mod W {}
92 /// Read-write values (empty)
93 pub mod RW {}
94 }
95
96 /// DAC channel2 trigger enable
97 pub mod TEN2 {
98 /// Offset (18 bits)
99 pub const offset: u32 = 18;
100 /// Mask (1 bit: 1 << 18)
101 pub const mask: u32 = 1 << offset;
102 /// Read-only values (empty)
103 pub mod R {}
104 /// Write-only values (empty)
105 pub mod W {}
106 /// Read-write values
107 pub mod RW {
108
109 /// 0b0: DAC channel X trigger disabled
110 pub const Disabled: u32 = 0b0;
111
112 /// 0b1: DAC channel X trigger enabled
113 pub const Enabled: u32 = 0b1;
114 }
115 }
116
117 /// DAC channel2 output buffer disable
118 pub mod BOFF2 {
119 /// Offset (17 bits)
120 pub const offset: u32 = 17;
121 /// Mask (1 bit: 1 << 17)
122 pub const mask: u32 = 1 << offset;
123 /// Read-only values (empty)
124 pub mod R {}
125 /// Write-only values (empty)
126 pub mod W {}
127 /// Read-write values
128 pub mod RW {
129
130 /// 0b0: DAC channel X output buffer enabled
131 pub const Enabled: u32 = 0b0;
132
133 /// 0b1: DAC channel X output buffer disabled
134 pub const Disabled: u32 = 0b1;
135 }
136 }
137
138 /// DAC channel2 enable
139 pub mod EN2 {
140 /// Offset (16 bits)
141 pub const offset: u32 = 16;
142 /// Mask (1 bit: 1 << 16)
143 pub const mask: u32 = 1 << offset;
144 /// Read-only values (empty)
145 pub mod R {}
146 /// Write-only values (empty)
147 pub mod W {}
148 /// Read-write values
149 pub mod RW {
150
151 /// 0b0: DAC channel X disabled
152 pub const Disabled: u32 = 0b0;
153
154 /// 0b1: DAC channel X enabled
155 pub const Enabled: u32 = 0b1;
156 }
157 }
158
159 /// DAC channel1 DMA Underrun Interrupt enable
160 pub mod DMAUDRIE1 {
161 /// Offset (13 bits)
162 pub const offset: u32 = 13;
163 /// Mask (1 bit: 1 << 13)
164 pub const mask: u32 = 1 << offset;
165 /// Read-only values (empty)
166 pub mod R {}
167 /// Write-only values (empty)
168 pub mod W {}
169 pub use super::DMAUDRIE2::RW;
170 }
171
172 /// DAC channel1 DMA enable
173 pub mod DMAEN1 {
174 /// Offset (12 bits)
175 pub const offset: u32 = 12;
176 /// Mask (1 bit: 1 << 12)
177 pub const mask: u32 = 1 << offset;
178 /// Read-only values (empty)
179 pub mod R {}
180 /// Write-only values (empty)
181 pub mod W {}
182 pub use super::DMAEN2::RW;
183 }
184
185 /// DAC channel1 mask/amplitude selector
186 pub mod MAMP1 {
187 /// Offset (8 bits)
188 pub const offset: u32 = 8;
189 /// Mask (4 bits: 0b1111 << 8)
190 pub const mask: u32 = 0b1111 << offset;
191 /// Read-only values (empty)
192 pub mod R {}
193 /// Write-only values (empty)
194 pub mod W {}
195 /// Read-write values (empty)
196 pub mod RW {}
197 }
198
199 /// DAC channel1 noise/triangle wave generation enable
200 pub mod WAVE1 {
201 /// Offset (6 bits)
202 pub const offset: u32 = 6;
203 /// Mask (2 bits: 0b11 << 6)
204 pub const mask: u32 = 0b11 << offset;
205 /// Read-only values (empty)
206 pub mod R {}
207 /// Write-only values (empty)
208 pub mod W {}
209 /// Read-write values (empty)
210 pub mod RW {}
211 }
212
213 /// DAC channel1 trigger selection
214 pub mod TSEL1 {
215 /// Offset (3 bits)
216 pub const offset: u32 = 3;
217 /// Mask (3 bits: 0b111 << 3)
218 pub const mask: u32 = 0b111 << offset;
219 /// Read-only values (empty)
220 pub mod R {}
221 /// Write-only values (empty)
222 pub mod W {}
223 /// Read-write values
224 pub mod RW {
225
226 /// 0b000: Timer 6 TRGO event
227 pub const TIM6_TRGO: u32 = 0b000;
228
229 /// 0b001: Timer 3 TRGO event
230 pub const TIM3_TRGO: u32 = 0b001;
231
232 /// 0b010: Timer 7 TRGO event
233 pub const TIM7_TRGO: u32 = 0b010;
234
235 /// 0b011: Timer 15 TRGO event
236 pub const TIM15_TRGO: u32 = 0b011;
237
238 /// 0b100: Timer 2 TRGO event
239 pub const TIM2_TRGO: u32 = 0b100;
240
241 /// 0b110: EXTI line9
242 pub const EXTI9: u32 = 0b110;
243
244 /// 0b111: Software trigger
245 pub const SOFTWARE: u32 = 0b111;
246 }
247 }
248
249 /// DAC channel1 trigger enable
250 pub mod TEN1 {
251 /// Offset (2 bits)
252 pub const offset: u32 = 2;
253 /// Mask (1 bit: 1 << 2)
254 pub const mask: u32 = 1 << offset;
255 /// Read-only values (empty)
256 pub mod R {}
257 /// Write-only values (empty)
258 pub mod W {}
259 pub use super::TEN2::RW;
260 }
261
262 /// DAC channel1 output buffer disable
263 pub mod BOFF1 {
264 /// Offset (1 bits)
265 pub const offset: u32 = 1;
266 /// Mask (1 bit: 1 << 1)
267 pub const mask: u32 = 1 << offset;
268 /// Read-only values (empty)
269 pub mod R {}
270 /// Write-only values (empty)
271 pub mod W {}
272 pub use super::BOFF2::RW;
273 }
274
275 /// DAC channel1 enable
276 pub mod EN1 {
277 /// Offset (0 bits)
278 pub const offset: u32 = 0;
279 /// Mask (1 bit: 1 << 0)
280 pub const mask: u32 = 1 << offset;
281 /// Read-only values (empty)
282 pub mod R {}
283 /// Write-only values (empty)
284 pub mod W {}
285 pub use super::EN2::RW;
286 }
287}
288
289/// software trigger register
290pub mod SWTRIGR {
291
292 /// DAC channel2 software trigger
293 pub mod SWTRIG2 {
294 /// Offset (1 bits)
295 pub const offset: u32 = 1;
296 /// Mask (1 bit: 1 << 1)
297 pub const mask: u32 = 1 << offset;
298 /// Read-only values (empty)
299 pub mod R {}
300 /// Write-only values
301 pub mod W {
302
303 /// 0b0: DAC channel X software trigger disabled
304 pub const Disabled: u32 = 0b0;
305
306 /// 0b1: DAC channel X software trigger enabled
307 pub const Enabled: u32 = 0b1;
308 }
309 /// Read-write values (empty)
310 pub mod RW {}
311 }
312
313 /// DAC channel1 software trigger
314 pub mod SWTRIG1 {
315 /// Offset (0 bits)
316 pub const offset: u32 = 0;
317 /// Mask (1 bit: 1 << 0)
318 pub const mask: u32 = 1 << offset;
319 /// Read-only values (empty)
320 pub mod R {}
321 pub use super::SWTRIG2::W;
322 /// Read-write values (empty)
323 pub mod RW {}
324 }
325}
326
327/// channel1 12-bit right-aligned data holding register
328pub mod DHR12R1 {
329
330 /// DAC channel1 12-bit right-aligned data
331 pub mod DACC1DHR {
332 /// Offset (0 bits)
333 pub const offset: u32 = 0;
334 /// Mask (12 bits: 0xfff << 0)
335 pub const mask: u32 = 0xfff << offset;
336 /// Read-only values (empty)
337 pub mod R {}
338 /// Write-only values (empty)
339 pub mod W {}
340 /// Read-write values (empty)
341 pub mod RW {}
342 }
343}
344
345/// channel1 12-bit left aligned data holding register
346pub mod DHR12L1 {
347
348 /// DAC channel1 12-bit left-aligned data
349 pub mod DACC1DHR {
350 /// Offset (4 bits)
351 pub const offset: u32 = 4;
352 /// Mask (12 bits: 0xfff << 4)
353 pub const mask: u32 = 0xfff << offset;
354 /// Read-only values (empty)
355 pub mod R {}
356 /// Write-only values (empty)
357 pub mod W {}
358 /// Read-write values (empty)
359 pub mod RW {}
360 }
361}
362
363/// channel1 8-bit right aligned data holding register
364pub mod DHR8R1 {
365
366 /// DAC channel1 8-bit right-aligned data
367 pub mod DACC1DHR {
368 /// Offset (0 bits)
369 pub const offset: u32 = 0;
370 /// Mask (8 bits: 0xff << 0)
371 pub const mask: u32 = 0xff << offset;
372 /// Read-only values (empty)
373 pub mod R {}
374 /// Write-only values (empty)
375 pub mod W {}
376 /// Read-write values (empty)
377 pub mod RW {}
378 }
379}
380
381/// channel2 12-bit right aligned data holding register
382pub mod DHR12R2 {
383
384 /// DAC channel2 12-bit right-aligned data
385 pub mod DACC2DHR {
386 /// Offset (0 bits)
387 pub const offset: u32 = 0;
388 /// Mask (12 bits: 0xfff << 0)
389 pub const mask: u32 = 0xfff << offset;
390 /// Read-only values (empty)
391 pub mod R {}
392 /// Write-only values (empty)
393 pub mod W {}
394 /// Read-write values (empty)
395 pub mod RW {}
396 }
397}
398
399/// channel2 12-bit left aligned data holding register
400pub mod DHR12L2 {
401
402 /// DAC channel2 12-bit left-aligned data
403 pub mod DACC2DHR {
404 /// Offset (4 bits)
405 pub const offset: u32 = 4;
406 /// Mask (12 bits: 0xfff << 4)
407 pub const mask: u32 = 0xfff << offset;
408 /// Read-only values (empty)
409 pub mod R {}
410 /// Write-only values (empty)
411 pub mod W {}
412 /// Read-write values (empty)
413 pub mod RW {}
414 }
415}
416
417/// channel2 8-bit right-aligned data holding register
418pub mod DHR8R2 {
419
420 /// DAC channel2 8-bit right-aligned data
421 pub mod DACC2DHR {
422 /// Offset (0 bits)
423 pub const offset: u32 = 0;
424 /// Mask (8 bits: 0xff << 0)
425 pub const mask: u32 = 0xff << offset;
426 /// Read-only values (empty)
427 pub mod R {}
428 /// Write-only values (empty)
429 pub mod W {}
430 /// Read-write values (empty)
431 pub mod RW {}
432 }
433}
434
435/// Dual DAC 12-bit right-aligned data holding register
436pub mod DHR12RD {
437
438 /// DAC channel2 12-bit right-aligned data
439 pub mod DACC2DHR {
440 /// Offset (16 bits)
441 pub const offset: u32 = 16;
442 /// Mask (12 bits: 0xfff << 16)
443 pub const mask: u32 = 0xfff << offset;
444 /// Read-only values (empty)
445 pub mod R {}
446 /// Write-only values (empty)
447 pub mod W {}
448 /// Read-write values (empty)
449 pub mod RW {}
450 }
451
452 /// DAC channel1 12-bit right-aligned data
453 pub mod DACC1DHR {
454 /// Offset (0 bits)
455 pub const offset: u32 = 0;
456 /// Mask (12 bits: 0xfff << 0)
457 pub const mask: u32 = 0xfff << offset;
458 /// Read-only values (empty)
459 pub mod R {}
460 /// Write-only values (empty)
461 pub mod W {}
462 /// Read-write values (empty)
463 pub mod RW {}
464 }
465}
466
467/// DUAL DAC 12-bit left aligned data holding register
468pub mod DHR12LD {
469
470 /// DAC channel2 12-bit left-aligned data
471 pub mod DACC2DHR {
472 /// Offset (20 bits)
473 pub const offset: u32 = 20;
474 /// Mask (12 bits: 0xfff << 20)
475 pub const mask: u32 = 0xfff << offset;
476 /// Read-only values (empty)
477 pub mod R {}
478 /// Write-only values (empty)
479 pub mod W {}
480 /// Read-write values (empty)
481 pub mod RW {}
482 }
483
484 /// DAC channel1 12-bit left-aligned data
485 pub mod DACC1DHR {
486 /// Offset (4 bits)
487 pub const offset: u32 = 4;
488 /// Mask (12 bits: 0xfff << 4)
489 pub const mask: u32 = 0xfff << offset;
490 /// Read-only values (empty)
491 pub mod R {}
492 /// Write-only values (empty)
493 pub mod W {}
494 /// Read-write values (empty)
495 pub mod RW {}
496 }
497}
498
499/// DUAL DAC 8-bit right aligned data holding register
500pub mod DHR8RD {
501
502 /// DAC channel2 8-bit right-aligned data
503 pub mod DACC2DHR {
504 /// Offset (8 bits)
505 pub const offset: u32 = 8;
506 /// Mask (8 bits: 0xff << 8)
507 pub const mask: u32 = 0xff << offset;
508 /// Read-only values (empty)
509 pub mod R {}
510 /// Write-only values (empty)
511 pub mod W {}
512 /// Read-write values (empty)
513 pub mod RW {}
514 }
515
516 /// DAC channel1 8-bit right-aligned data
517 pub mod DACC1DHR {
518 /// Offset (0 bits)
519 pub const offset: u32 = 0;
520 /// Mask (8 bits: 0xff << 0)
521 pub const mask: u32 = 0xff << offset;
522 /// Read-only values (empty)
523 pub mod R {}
524 /// Write-only values (empty)
525 pub mod W {}
526 /// Read-write values (empty)
527 pub mod RW {}
528 }
529}
530
531/// channel1 data output register
532pub mod DOR1 {
533
534 /// DAC channel1 data output
535 pub mod DACC1DOR {
536 /// Offset (0 bits)
537 pub const offset: u32 = 0;
538 /// Mask (12 bits: 0xfff << 0)
539 pub const mask: u32 = 0xfff << offset;
540 /// Read-only values (empty)
541 pub mod R {}
542 /// Write-only values (empty)
543 pub mod W {}
544 /// Read-write values (empty)
545 pub mod RW {}
546 }
547}
548
549/// channel2 data output register
550pub mod DOR2 {
551
552 /// DAC channel2 data output
553 pub mod DACC2DOR {
554 /// Offset (0 bits)
555 pub const offset: u32 = 0;
556 /// Mask (12 bits: 0xfff << 0)
557 pub const mask: u32 = 0xfff << offset;
558 /// Read-only values (empty)
559 pub mod R {}
560 /// Write-only values (empty)
561 pub mod W {}
562 /// Read-write values (empty)
563 pub mod RW {}
564 }
565}
566
567/// status register
568pub mod SR {
569
570 /// DAC channel2 DMA underrun flag
571 pub mod DMAUDR2 {
572 /// Offset (29 bits)
573 pub const offset: u32 = 29;
574 /// Mask (1 bit: 1 << 29)
575 pub const mask: u32 = 1 << offset;
576 /// Read-only values (empty)
577 pub mod R {}
578 /// Write-only values (empty)
579 pub mod W {}
580 /// Read-write values
581 pub mod RW {
582
583 /// 0b0: No DMA underrun error condition occurred for DAC channel X
584 pub const NoUnderrun: u32 = 0b0;
585
586 /// 0b1: DMA underrun error condition occurred for DAC channel X
587 pub const Underrun: u32 = 0b1;
588 }
589 }
590
591 /// DAC channel1 DMA underrun flag
592 pub mod DMAUDR1 {
593 /// Offset (13 bits)
594 pub const offset: u32 = 13;
595 /// Mask (1 bit: 1 << 13)
596 pub const mask: u32 = 1 << offset;
597 /// Read-only values (empty)
598 pub mod R {}
599 /// Write-only values (empty)
600 pub mod W {}
601 pub use super::DMAUDR2::RW;
602 }
603}
604#[repr(C)]
605pub struct RegisterBlock {
606 /// control register
607 pub CR: RWRegister<u32>,
608
609 /// software trigger register
610 pub SWTRIGR: WORegister<u32>,
611
612 /// channel1 12-bit right-aligned data holding register
613 pub DHR12R1: RWRegister<u32>,
614
615 /// channel1 12-bit left aligned data holding register
616 pub DHR12L1: RWRegister<u32>,
617
618 /// channel1 8-bit right aligned data holding register
619 pub DHR8R1: RWRegister<u32>,
620
621 /// channel2 12-bit right aligned data holding register
622 pub DHR12R2: RWRegister<u32>,
623
624 /// channel2 12-bit left aligned data holding register
625 pub DHR12L2: RWRegister<u32>,
626
627 /// channel2 8-bit right-aligned data holding register
628 pub DHR8R2: RWRegister<u32>,
629
630 /// Dual DAC 12-bit right-aligned data holding register
631 pub DHR12RD: RWRegister<u32>,
632
633 /// DUAL DAC 12-bit left aligned data holding register
634 pub DHR12LD: RWRegister<u32>,
635
636 /// DUAL DAC 8-bit right aligned data holding register
637 pub DHR8RD: RWRegister<u32>,
638
639 /// channel1 data output register
640 pub DOR1: RORegister<u32>,
641
642 /// channel2 data output register
643 pub DOR2: RORegister<u32>,
644
645 /// status register
646 pub SR: RWRegister<u32>,
647}
648pub struct ResetValues {
649 pub CR: u32,
650 pub SWTRIGR: u32,
651 pub DHR12R1: u32,
652 pub DHR12L1: u32,
653 pub DHR8R1: u32,
654 pub DHR12R2: u32,
655 pub DHR12L2: u32,
656 pub DHR8R2: u32,
657 pub DHR12RD: u32,
658 pub DHR12LD: u32,
659 pub DHR8RD: u32,
660 pub DOR1: u32,
661 pub DOR2: u32,
662 pub SR: u32,
663}
664#[cfg(not(feature = "nosync"))]
665pub struct Instance {
666 pub(crate) addr: u32,
667 pub(crate) _marker: PhantomData<*const RegisterBlock>,
668}
669#[cfg(not(feature = "nosync"))]
670impl ::core::ops::Deref for Instance {
671 type Target = RegisterBlock;
672 #[inline(always)]
673 fn deref(&self) -> &RegisterBlock {
674 unsafe { &*(self.addr as *const _) }
675 }
676}
677#[cfg(feature = "rtic")]
678unsafe impl Send for Instance {}
679
680/// Access functions for the DAC1 peripheral instance
681pub mod DAC1 {
682 use super::ResetValues;
683
684 #[cfg(not(feature = "nosync"))]
685 use super::Instance;
686
687 #[cfg(not(feature = "nosync"))]
688 const INSTANCE: Instance = Instance {
689 addr: 0x40007400,
690 _marker: ::core::marker::PhantomData,
691 };
692
693 /// Reset values for each field in DAC1
694 pub const reset: ResetValues = ResetValues {
695 CR: 0x00000000,
696 SWTRIGR: 0x00000000,
697 DHR12R1: 0x00000000,
698 DHR12L1: 0x00000000,
699 DHR8R1: 0x00000000,
700 DHR12R2: 0x00000000,
701 DHR12L2: 0x00000000,
702 DHR8R2: 0x00000000,
703 DHR12RD: 0x00000000,
704 DHR12LD: 0x00000000,
705 DHR8RD: 0x00000000,
706 DOR1: 0x00000000,
707 DOR2: 0x00000000,
708 SR: 0x00000000,
709 };
710
711 #[cfg(not(feature = "nosync"))]
712 #[allow(renamed_and_removed_lints)]
713 #[allow(private_no_mangle_statics)]
714 #[no_mangle]
715 static mut DAC1_TAKEN: bool = false;
716
717 /// Safe access to DAC1
718 ///
719 /// This function returns `Some(Instance)` if this instance is not
720 /// currently taken, and `None` if it is. This ensures that if you
721 /// do get `Some(Instance)`, you are ensured unique access to
722 /// the peripheral and there cannot be data races (unless other
723 /// code uses `unsafe`, of course). You can then pass the
724 /// `Instance` around to other functions as required. When you're
725 /// done with it, you can call `release(instance)` to return it.
726 ///
727 /// `Instance` itself dereferences to a `RegisterBlock`, which
728 /// provides access to the peripheral's registers.
729 #[cfg(not(feature = "nosync"))]
730 #[inline]
731 pub fn take() -> Option<Instance> {
732 external_cortex_m::interrupt::free(|_| unsafe {
733 if DAC1_TAKEN {
734 None
735 } else {
736 DAC1_TAKEN = true;
737 Some(INSTANCE)
738 }
739 })
740 }
741
742 /// Release exclusive access to DAC1
743 ///
744 /// This function allows you to return an `Instance` so that it
745 /// is available to `take()` again. This function will panic if
746 /// you return a different `Instance` or if this instance is not
747 /// already taken.
748 #[cfg(not(feature = "nosync"))]
749 #[inline]
750 pub fn release(inst: Instance) {
751 external_cortex_m::interrupt::free(|_| unsafe {
752 if DAC1_TAKEN && inst.addr == INSTANCE.addr {
753 DAC1_TAKEN = false;
754 } else {
755 panic!("Released a peripheral which was not taken");
756 }
757 });
758 }
759
760 /// Unsafely steal DAC1
761 ///
762 /// This function is similar to take() but forcibly takes the
763 /// Instance, marking it as taken irregardless of its previous
764 /// state.
765 #[cfg(not(feature = "nosync"))]
766 #[inline]
767 pub unsafe fn steal() -> Instance {
768 DAC1_TAKEN = true;
769 INSTANCE
770 }
771}
772
773/// Raw pointer to DAC1
774///
775/// Dereferencing this is unsafe because you are not ensured unique
776/// access to the peripheral, so you may encounter data races with
777/// other users of this peripheral. It is up to you to ensure you
778/// will not cause data races.
779///
780/// This constant is provided for ease of use in unsafe code: you can
781/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
782pub const DAC1: *const RegisterBlock = 0x40007400 as *const _;