stm32ral/stm32f3/peripherals/tim17.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! General purpose timer
4//!
5//! Used by: stm32f302, stm32f303, stm32f3x4
6
7use crate::{RWRegister, WORegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// control register 1
12pub mod CR1 {
13
14 /// Counter enable
15 pub mod CEN {
16 /// Offset (0 bits)
17 pub const offset: u32 = 0;
18 /// Mask (1 bit: 1 << 0)
19 pub const mask: u32 = 1 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values
25 pub mod RW {
26
27 /// 0b0: Counter disabled
28 pub const Disabled: u32 = 0b0;
29
30 /// 0b1: Counter enabled
31 pub const Enabled: u32 = 0b1;
32 }
33 }
34
35 /// Update disable
36 pub mod UDIS {
37 /// Offset (1 bits)
38 pub const offset: u32 = 1;
39 /// Mask (1 bit: 1 << 1)
40 pub const mask: u32 = 1 << offset;
41 /// Read-only values (empty)
42 pub mod R {}
43 /// Write-only values (empty)
44 pub mod W {}
45 /// Read-write values
46 pub mod RW {
47
48 /// 0b0: Update event enabled
49 pub const Enabled: u32 = 0b0;
50
51 /// 0b1: Update event disabled
52 pub const Disabled: u32 = 0b1;
53 }
54 }
55
56 /// Update request source
57 pub mod URS {
58 /// Offset (2 bits)
59 pub const offset: u32 = 2;
60 /// Mask (1 bit: 1 << 2)
61 pub const mask: u32 = 1 << offset;
62 /// Read-only values (empty)
63 pub mod R {}
64 /// Write-only values (empty)
65 pub mod W {}
66 /// Read-write values
67 pub mod RW {
68
69 /// 0b0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
70 pub const AnyEvent: u32 = 0b0;
71
72 /// 0b1: Only counter overflow/underflow generates an update interrupt or DMA request
73 pub const CounterOnly: u32 = 0b1;
74 }
75 }
76
77 /// One-pulse mode
78 pub mod OPM {
79 /// Offset (3 bits)
80 pub const offset: u32 = 3;
81 /// Mask (1 bit: 1 << 3)
82 pub const mask: u32 = 1 << offset;
83 /// Read-only values (empty)
84 pub mod R {}
85 /// Write-only values (empty)
86 pub mod W {}
87 /// Read-write values
88 pub mod RW {
89
90 /// 0b0: Counter is not stopped at update event
91 pub const Disabled: u32 = 0b0;
92
93 /// 0b1: Counter stops counting at the next update event (clearing the CEN bit)
94 pub const Enabled: u32 = 0b1;
95 }
96 }
97
98 /// Auto-reload preload enable
99 pub mod ARPE {
100 /// Offset (7 bits)
101 pub const offset: u32 = 7;
102 /// Mask (1 bit: 1 << 7)
103 pub const mask: u32 = 1 << offset;
104 /// Read-only values (empty)
105 pub mod R {}
106 /// Write-only values (empty)
107 pub mod W {}
108 /// Read-write values
109 pub mod RW {
110
111 /// 0b0: TIMx_APRR register is not buffered
112 pub const Disabled: u32 = 0b0;
113
114 /// 0b1: TIMx_APRR register is buffered
115 pub const Enabled: u32 = 0b1;
116 }
117 }
118
119 /// Clock division
120 pub mod CKD {
121 /// Offset (8 bits)
122 pub const offset: u32 = 8;
123 /// Mask (2 bits: 0b11 << 8)
124 pub const mask: u32 = 0b11 << offset;
125 /// Read-only values (empty)
126 pub mod R {}
127 /// Write-only values (empty)
128 pub mod W {}
129 /// Read-write values
130 pub mod RW {
131
132 /// 0b00: t_DTS = t_CK_INT
133 pub const Div1: u32 = 0b00;
134
135 /// 0b01: t_DTS = 2 × t_CK_INT
136 pub const Div2: u32 = 0b01;
137
138 /// 0b10: t_DTS = 4 × t_CK_INT
139 pub const Div4: u32 = 0b10;
140 }
141 }
142
143 /// UIF status bit remapping
144 pub mod UIFREMAP {
145 /// Offset (11 bits)
146 pub const offset: u32 = 11;
147 /// Mask (1 bit: 1 << 11)
148 pub const mask: u32 = 1 << offset;
149 /// Read-only values (empty)
150 pub mod R {}
151 /// Write-only values (empty)
152 pub mod W {}
153 /// Read-write values (empty)
154 pub mod RW {}
155 }
156}
157
158/// control register 2
159pub mod CR2 {
160
161 /// Output Idle state 1
162 pub mod OIS1N {
163 /// Offset (9 bits)
164 pub const offset: u32 = 9;
165 /// Mask (1 bit: 1 << 9)
166 pub const mask: u32 = 1 << offset;
167 /// Read-only values (empty)
168 pub mod R {}
169 /// Write-only values (empty)
170 pub mod W {}
171 /// Read-write values (empty)
172 pub mod RW {}
173 }
174
175 /// Output Idle state 1
176 pub mod OIS1 {
177 /// Offset (8 bits)
178 pub const offset: u32 = 8;
179 /// Mask (1 bit: 1 << 8)
180 pub const mask: u32 = 1 << offset;
181 /// Read-only values (empty)
182 pub mod R {}
183 /// Write-only values (empty)
184 pub mod W {}
185 /// Read-write values (empty)
186 pub mod RW {}
187 }
188
189 /// Capture/compare DMA selection
190 pub mod CCDS {
191 /// Offset (3 bits)
192 pub const offset: u32 = 3;
193 /// Mask (1 bit: 1 << 3)
194 pub const mask: u32 = 1 << offset;
195 /// Read-only values (empty)
196 pub mod R {}
197 /// Write-only values (empty)
198 pub mod W {}
199 /// Read-write values (empty)
200 pub mod RW {}
201 }
202
203 /// Capture/compare control update selection
204 pub mod CCUS {
205 /// Offset (2 bits)
206 pub const offset: u32 = 2;
207 /// Mask (1 bit: 1 << 2)
208 pub const mask: u32 = 1 << offset;
209 /// Read-only values (empty)
210 pub mod R {}
211 /// Write-only values (empty)
212 pub mod W {}
213 /// Read-write values (empty)
214 pub mod RW {}
215 }
216
217 /// Capture/compare preloaded control
218 pub mod CCPC {
219 /// Offset (0 bits)
220 pub const offset: u32 = 0;
221 /// Mask (1 bit: 1 << 0)
222 pub const mask: u32 = 1 << offset;
223 /// Read-only values (empty)
224 pub mod R {}
225 /// Write-only values (empty)
226 pub mod W {}
227 /// Read-write values (empty)
228 pub mod RW {}
229 }
230}
231
232/// DMA/Interrupt enable register
233pub mod DIER {
234
235 /// Update interrupt enable
236 pub mod UIE {
237 /// Offset (0 bits)
238 pub const offset: u32 = 0;
239 /// Mask (1 bit: 1 << 0)
240 pub const mask: u32 = 1 << offset;
241 /// Read-only values (empty)
242 pub mod R {}
243 /// Write-only values (empty)
244 pub mod W {}
245 /// Read-write values
246 pub mod RW {
247
248 /// 0b0: Update interrupt disabled
249 pub const Disabled: u32 = 0b0;
250
251 /// 0b1: Update interrupt enabled
252 pub const Enabled: u32 = 0b1;
253 }
254 }
255
256 /// Capture/Compare 1 interrupt enable
257 pub mod CC1IE {
258 /// Offset (1 bits)
259 pub const offset: u32 = 1;
260 /// Mask (1 bit: 1 << 1)
261 pub const mask: u32 = 1 << offset;
262 /// Read-only values (empty)
263 pub mod R {}
264 /// Write-only values (empty)
265 pub mod W {}
266 /// Read-write values (empty)
267 pub mod RW {}
268 }
269
270 /// COM interrupt enable
271 pub mod COMIE {
272 /// Offset (5 bits)
273 pub const offset: u32 = 5;
274 /// Mask (1 bit: 1 << 5)
275 pub const mask: u32 = 1 << offset;
276 /// Read-only values (empty)
277 pub mod R {}
278 /// Write-only values (empty)
279 pub mod W {}
280 /// Read-write values (empty)
281 pub mod RW {}
282 }
283
284 /// Trigger interrupt enable
285 pub mod TIE {
286 /// Offset (6 bits)
287 pub const offset: u32 = 6;
288 /// Mask (1 bit: 1 << 6)
289 pub const mask: u32 = 1 << offset;
290 /// Read-only values (empty)
291 pub mod R {}
292 /// Write-only values (empty)
293 pub mod W {}
294 /// Read-write values (empty)
295 pub mod RW {}
296 }
297
298 /// Break interrupt enable
299 pub mod BIE {
300 /// Offset (7 bits)
301 pub const offset: u32 = 7;
302 /// Mask (1 bit: 1 << 7)
303 pub const mask: u32 = 1 << offset;
304 /// Read-only values (empty)
305 pub mod R {}
306 /// Write-only values (empty)
307 pub mod W {}
308 /// Read-write values (empty)
309 pub mod RW {}
310 }
311
312 /// Update DMA request enable
313 pub mod UDE {
314 /// Offset (8 bits)
315 pub const offset: u32 = 8;
316 /// Mask (1 bit: 1 << 8)
317 pub const mask: u32 = 1 << offset;
318 /// Read-only values (empty)
319 pub mod R {}
320 /// Write-only values (empty)
321 pub mod W {}
322 /// Read-write values (empty)
323 pub mod RW {}
324 }
325
326 /// Capture/Compare 1 DMA request enable
327 pub mod CC1DE {
328 /// Offset (9 bits)
329 pub const offset: u32 = 9;
330 /// Mask (1 bit: 1 << 9)
331 pub const mask: u32 = 1 << offset;
332 /// Read-only values (empty)
333 pub mod R {}
334 /// Write-only values (empty)
335 pub mod W {}
336 /// Read-write values (empty)
337 pub mod RW {}
338 }
339
340 /// COM DMA request enable
341 pub mod COMDE {
342 /// Offset (13 bits)
343 pub const offset: u32 = 13;
344 /// Mask (1 bit: 1 << 13)
345 pub const mask: u32 = 1 << offset;
346 /// Read-only values (empty)
347 pub mod R {}
348 /// Write-only values (empty)
349 pub mod W {}
350 /// Read-write values (empty)
351 pub mod RW {}
352 }
353
354 /// Trigger DMA request enable
355 pub mod TDE {
356 /// Offset (14 bits)
357 pub const offset: u32 = 14;
358 /// Mask (1 bit: 1 << 14)
359 pub const mask: u32 = 1 << offset;
360 /// Read-only values (empty)
361 pub mod R {}
362 /// Write-only values (empty)
363 pub mod W {}
364 /// Read-write values (empty)
365 pub mod RW {}
366 }
367}
368
369/// status register
370pub mod SR {
371
372 /// Capture/Compare 1 overcapture flag
373 pub mod CC1OF {
374 /// Offset (9 bits)
375 pub const offset: u32 = 9;
376 /// Mask (1 bit: 1 << 9)
377 pub const mask: u32 = 1 << offset;
378 /// Read-only values (empty)
379 pub mod R {}
380 /// Write-only values (empty)
381 pub mod W {}
382 /// Read-write values (empty)
383 pub mod RW {}
384 }
385
386 /// Break interrupt flag
387 pub mod BIF {
388 /// Offset (7 bits)
389 pub const offset: u32 = 7;
390 /// Mask (1 bit: 1 << 7)
391 pub const mask: u32 = 1 << offset;
392 /// Read-only values (empty)
393 pub mod R {}
394 /// Write-only values (empty)
395 pub mod W {}
396 /// Read-write values (empty)
397 pub mod RW {}
398 }
399
400 /// Trigger interrupt flag
401 pub mod TIF {
402 /// Offset (6 bits)
403 pub const offset: u32 = 6;
404 /// Mask (1 bit: 1 << 6)
405 pub const mask: u32 = 1 << offset;
406 /// Read-only values (empty)
407 pub mod R {}
408 /// Write-only values (empty)
409 pub mod W {}
410 /// Read-write values (empty)
411 pub mod RW {}
412 }
413
414 /// COM interrupt flag
415 pub mod COMIF {
416 /// Offset (5 bits)
417 pub const offset: u32 = 5;
418 /// Mask (1 bit: 1 << 5)
419 pub const mask: u32 = 1 << offset;
420 /// Read-only values (empty)
421 pub mod R {}
422 /// Write-only values (empty)
423 pub mod W {}
424 /// Read-write values (empty)
425 pub mod RW {}
426 }
427
428 /// Capture/compare 1 interrupt flag
429 pub mod CC1IF {
430 /// Offset (1 bits)
431 pub const offset: u32 = 1;
432 /// Mask (1 bit: 1 << 1)
433 pub const mask: u32 = 1 << offset;
434 /// Read-only values (empty)
435 pub mod R {}
436 /// Write-only values (empty)
437 pub mod W {}
438 /// Read-write values (empty)
439 pub mod RW {}
440 }
441
442 /// Update interrupt flag
443 pub mod UIF {
444 /// Offset (0 bits)
445 pub const offset: u32 = 0;
446 /// Mask (1 bit: 1 << 0)
447 pub const mask: u32 = 1 << offset;
448 /// Read-only values (empty)
449 pub mod R {}
450 /// Write-only values (empty)
451 pub mod W {}
452 /// Read-write values
453 pub mod RW {
454
455 /// 0b0: No update occurred
456 pub const Clear: u32 = 0b0;
457
458 /// 0b1: Update interrupt pending.
459 pub const UpdatePending: u32 = 0b1;
460 }
461 }
462}
463
464/// event generation register
465pub mod EGR {
466
467 /// Break generation
468 pub mod BG {
469 /// Offset (7 bits)
470 pub const offset: u32 = 7;
471 /// Mask (1 bit: 1 << 7)
472 pub const mask: u32 = 1 << offset;
473 /// Read-only values (empty)
474 pub mod R {}
475 /// Write-only values (empty)
476 pub mod W {}
477 /// Read-write values (empty)
478 pub mod RW {}
479 }
480
481 /// Trigger generation
482 pub mod TG {
483 /// Offset (6 bits)
484 pub const offset: u32 = 6;
485 /// Mask (1 bit: 1 << 6)
486 pub const mask: u32 = 1 << offset;
487 /// Read-only values (empty)
488 pub mod R {}
489 /// Write-only values (empty)
490 pub mod W {}
491 /// Read-write values (empty)
492 pub mod RW {}
493 }
494
495 /// Capture/Compare control update generation
496 pub mod COMG {
497 /// Offset (5 bits)
498 pub const offset: u32 = 5;
499 /// Mask (1 bit: 1 << 5)
500 pub const mask: u32 = 1 << offset;
501 /// Read-only values (empty)
502 pub mod R {}
503 /// Write-only values (empty)
504 pub mod W {}
505 /// Read-write values (empty)
506 pub mod RW {}
507 }
508
509 /// Capture/compare 1 generation
510 pub mod CC1G {
511 /// Offset (1 bits)
512 pub const offset: u32 = 1;
513 /// Mask (1 bit: 1 << 1)
514 pub const mask: u32 = 1 << offset;
515 /// Read-only values (empty)
516 pub mod R {}
517 /// Write-only values (empty)
518 pub mod W {}
519 /// Read-write values (empty)
520 pub mod RW {}
521 }
522
523 /// Update generation
524 pub mod UG {
525 /// Offset (0 bits)
526 pub const offset: u32 = 0;
527 /// Mask (1 bit: 1 << 0)
528 pub const mask: u32 = 1 << offset;
529 /// Read-only values (empty)
530 pub mod R {}
531 /// Write-only values
532 pub mod W {
533
534 /// 0b1: Re-initializes the timer counter and generates an update of the registers.
535 pub const Update: u32 = 0b1;
536 }
537 /// Read-write values (empty)
538 pub mod RW {}
539 }
540}
541
542/// CCMR1_Output and CCMR1_Input
543/// CCMR1_Output: capture/compare mode register (output mode)
544/// CCMR1_Input: capture/compare mode register 1 (input mode)
545pub mod CCMR1 {
546
547 /// Capture/Compare 1 selection
548 pub mod CC1S {
549 /// Offset (0 bits)
550 pub const offset: u32 = 0;
551 /// Mask (2 bits: 0b11 << 0)
552 pub const mask: u32 = 0b11 << offset;
553 /// Read-only values (empty)
554 pub mod R {}
555 /// Write-only values (empty)
556 pub mod W {}
557 /// Read-write values (empty)
558 pub mod RW {}
559 }
560
561 /// Output Compare 1 fast enable
562 pub mod OC1FE {
563 /// Offset (2 bits)
564 pub const offset: u32 = 2;
565 /// Mask (1 bit: 1 << 2)
566 pub const mask: u32 = 1 << offset;
567 /// Read-only values (empty)
568 pub mod R {}
569 /// Write-only values (empty)
570 pub mod W {}
571 /// Read-write values (empty)
572 pub mod RW {}
573 }
574
575 /// Output Compare 1 preload enable
576 pub mod OC1PE {
577 /// Offset (3 bits)
578 pub const offset: u32 = 3;
579 /// Mask (1 bit: 1 << 3)
580 pub const mask: u32 = 1 << offset;
581 /// Read-only values (empty)
582 pub mod R {}
583 /// Write-only values (empty)
584 pub mod W {}
585 /// Read-write values (empty)
586 pub mod RW {}
587 }
588
589 /// Output Compare 1 mode
590 pub mod OC1M {
591 /// Offset (4 bits)
592 pub const offset: u32 = 4;
593 /// Mask (3 bits: 0b111 << 4)
594 pub const mask: u32 = 0b111 << offset;
595 /// Read-only values (empty)
596 pub mod R {}
597 /// Write-only values (empty)
598 pub mod W {}
599 /// Read-write values
600 pub mod RW {
601
602 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
603 pub const Frozen: u32 = 0b000;
604
605 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
606 pub const ActiveOnMatch: u32 = 0b001;
607
608 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
609 pub const InactiveOnMatch: u32 = 0b010;
610
611 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy
612 pub const Toggle: u32 = 0b011;
613
614 /// 0b100: OCyREF is forced low
615 pub const ForceInactive: u32 = 0b100;
616
617 /// 0b101: OCyREF is forced high
618 pub const ForceActive: u32 = 0b101;
619
620 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
621 pub const PwmMode1: u32 = 0b110;
622
623 /// 0b111: Inversely to PwmMode1
624 pub const PwmMode2: u32 = 0b111;
625 }
626 }
627
628 /// Output Compare 1 mode
629 pub mod OC1M_3 {
630 /// Offset (16 bits)
631 pub const offset: u32 = 16;
632 /// Mask (1 bit: 1 << 16)
633 pub const mask: u32 = 1 << offset;
634 /// Read-only values (empty)
635 pub mod R {}
636 /// Write-only values (empty)
637 pub mod W {}
638 /// Read-write values (empty)
639 pub mod RW {}
640 }
641
642 /// Input capture 1 filter
643 pub mod IC1F {
644 /// Offset (4 bits)
645 pub const offset: u32 = 4;
646 /// Mask (4 bits: 0b1111 << 4)
647 pub const mask: u32 = 0b1111 << offset;
648 /// Read-only values (empty)
649 pub mod R {}
650 /// Write-only values (empty)
651 pub mod W {}
652 /// Read-write values (empty)
653 pub mod RW {}
654 }
655
656 /// Input capture 1 prescaler
657 pub mod IC1PSC {
658 /// Offset (2 bits)
659 pub const offset: u32 = 2;
660 /// Mask (2 bits: 0b11 << 2)
661 pub const mask: u32 = 0b11 << offset;
662 /// Read-only values (empty)
663 pub mod R {}
664 /// Write-only values (empty)
665 pub mod W {}
666 /// Read-write values (empty)
667 pub mod RW {}
668 }
669}
670
671/// capture/compare enable register
672pub mod CCER {
673
674 /// Capture/Compare 1 output Polarity
675 pub mod CC1NP {
676 /// Offset (3 bits)
677 pub const offset: u32 = 3;
678 /// Mask (1 bit: 1 << 3)
679 pub const mask: u32 = 1 << offset;
680 /// Read-only values (empty)
681 pub mod R {}
682 /// Write-only values (empty)
683 pub mod W {}
684 /// Read-write values (empty)
685 pub mod RW {}
686 }
687
688 /// Capture/Compare 1 complementary output enable
689 pub mod CC1NE {
690 /// Offset (2 bits)
691 pub const offset: u32 = 2;
692 /// Mask (1 bit: 1 << 2)
693 pub const mask: u32 = 1 << offset;
694 /// Read-only values (empty)
695 pub mod R {}
696 /// Write-only values (empty)
697 pub mod W {}
698 /// Read-write values (empty)
699 pub mod RW {}
700 }
701
702 /// Capture/Compare 1 output Polarity
703 pub mod CC1P {
704 /// Offset (1 bits)
705 pub const offset: u32 = 1;
706 /// Mask (1 bit: 1 << 1)
707 pub const mask: u32 = 1 << offset;
708 /// Read-only values (empty)
709 pub mod R {}
710 /// Write-only values (empty)
711 pub mod W {}
712 /// Read-write values (empty)
713 pub mod RW {}
714 }
715
716 /// Capture/Compare 1 output enable
717 pub mod CC1E {
718 /// Offset (0 bits)
719 pub const offset: u32 = 0;
720 /// Mask (1 bit: 1 << 0)
721 pub const mask: u32 = 1 << offset;
722 /// Read-only values (empty)
723 pub mod R {}
724 /// Write-only values (empty)
725 pub mod W {}
726 /// Read-write values (empty)
727 pub mod RW {}
728 }
729}
730
731/// counter
732pub mod CNT {
733
734 /// counter value
735 pub mod CNT {
736 /// Offset (0 bits)
737 pub const offset: u32 = 0;
738 /// Mask (16 bits: 0xffff << 0)
739 pub const mask: u32 = 0xffff << offset;
740 /// Read-only values (empty)
741 pub mod R {}
742 /// Write-only values (empty)
743 pub mod W {}
744 /// Read-write values (empty)
745 pub mod RW {}
746 }
747
748 /// UIF Copy
749 pub mod UIFCPY {
750 /// Offset (31 bits)
751 pub const offset: u32 = 31;
752 /// Mask (1 bit: 1 << 31)
753 pub const mask: u32 = 1 << offset;
754 /// Read-only values (empty)
755 pub mod R {}
756 /// Write-only values (empty)
757 pub mod W {}
758 /// Read-write values (empty)
759 pub mod RW {}
760 }
761}
762
763/// prescaler
764pub mod PSC {
765
766 /// Prescaler value
767 pub mod PSC {
768 /// Offset (0 bits)
769 pub const offset: u32 = 0;
770 /// Mask (16 bits: 0xffff << 0)
771 pub const mask: u32 = 0xffff << offset;
772 /// Read-only values (empty)
773 pub mod R {}
774 /// Write-only values (empty)
775 pub mod W {}
776 /// Read-write values (empty)
777 pub mod RW {}
778 }
779}
780
781/// auto-reload register
782pub mod ARR {
783
784 /// Auto-reload value
785 pub mod ARR {
786 /// Offset (0 bits)
787 pub const offset: u32 = 0;
788 /// Mask (16 bits: 0xffff << 0)
789 pub const mask: u32 = 0xffff << offset;
790 /// Read-only values (empty)
791 pub mod R {}
792 /// Write-only values (empty)
793 pub mod W {}
794 /// Read-write values (empty)
795 pub mod RW {}
796 }
797}
798
799/// repetition counter register
800pub mod RCR {
801
802 /// Repetition counter value
803 pub mod REP {
804 /// Offset (0 bits)
805 pub const offset: u32 = 0;
806 /// Mask (8 bits: 0xff << 0)
807 pub const mask: u32 = 0xff << offset;
808 /// Read-only values (empty)
809 pub mod R {}
810 /// Write-only values (empty)
811 pub mod W {}
812 /// Read-write values (empty)
813 pub mod RW {}
814 }
815}
816
817/// capture/compare register
818pub mod CCR1 {
819
820 /// Capture/Compare value
821 pub mod CCR {
822 /// Offset (0 bits)
823 pub const offset: u32 = 0;
824 /// Mask (16 bits: 0xffff << 0)
825 pub const mask: u32 = 0xffff << offset;
826 /// Read-only values (empty)
827 pub mod R {}
828 /// Write-only values (empty)
829 pub mod W {}
830 /// Read-write values (empty)
831 pub mod RW {}
832 }
833}
834
835/// break and dead-time register
836pub mod BDTR {
837
838 /// Dead-time generator setup
839 pub mod DTG {
840 /// Offset (0 bits)
841 pub const offset: u32 = 0;
842 /// Mask (8 bits: 0xff << 0)
843 pub const mask: u32 = 0xff << offset;
844 /// Read-only values (empty)
845 pub mod R {}
846 /// Write-only values (empty)
847 pub mod W {}
848 /// Read-write values (empty)
849 pub mod RW {}
850 }
851
852 /// Lock configuration
853 pub mod LOCK {
854 /// Offset (8 bits)
855 pub const offset: u32 = 8;
856 /// Mask (2 bits: 0b11 << 8)
857 pub const mask: u32 = 0b11 << offset;
858 /// Read-only values (empty)
859 pub mod R {}
860 /// Write-only values (empty)
861 pub mod W {}
862 /// Read-write values (empty)
863 pub mod RW {}
864 }
865
866 /// Off-state selection for Idle mode
867 pub mod OSSI {
868 /// Offset (10 bits)
869 pub const offset: u32 = 10;
870 /// Mask (1 bit: 1 << 10)
871 pub const mask: u32 = 1 << offset;
872 /// Read-only values (empty)
873 pub mod R {}
874 /// Write-only values (empty)
875 pub mod W {}
876 /// Read-write values (empty)
877 pub mod RW {}
878 }
879
880 /// Off-state selection for Run mode
881 pub mod OSSR {
882 /// Offset (11 bits)
883 pub const offset: u32 = 11;
884 /// Mask (1 bit: 1 << 11)
885 pub const mask: u32 = 1 << offset;
886 /// Read-only values (empty)
887 pub mod R {}
888 /// Write-only values (empty)
889 pub mod W {}
890 /// Read-write values (empty)
891 pub mod RW {}
892 }
893
894 /// Break enable
895 pub mod BKE {
896 /// Offset (12 bits)
897 pub const offset: u32 = 12;
898 /// Mask (1 bit: 1 << 12)
899 pub const mask: u32 = 1 << offset;
900 /// Read-only values (empty)
901 pub mod R {}
902 /// Write-only values (empty)
903 pub mod W {}
904 /// Read-write values (empty)
905 pub mod RW {}
906 }
907
908 /// Break polarity
909 pub mod BKP {
910 /// Offset (13 bits)
911 pub const offset: u32 = 13;
912 /// Mask (1 bit: 1 << 13)
913 pub const mask: u32 = 1 << offset;
914 /// Read-only values (empty)
915 pub mod R {}
916 /// Write-only values (empty)
917 pub mod W {}
918 /// Read-write values (empty)
919 pub mod RW {}
920 }
921
922 /// Automatic output enable
923 pub mod AOE {
924 /// Offset (14 bits)
925 pub const offset: u32 = 14;
926 /// Mask (1 bit: 1 << 14)
927 pub const mask: u32 = 1 << offset;
928 /// Read-only values (empty)
929 pub mod R {}
930 /// Write-only values (empty)
931 pub mod W {}
932 /// Read-write values (empty)
933 pub mod RW {}
934 }
935
936 /// Main output enable
937 pub mod MOE {
938 /// Offset (15 bits)
939 pub const offset: u32 = 15;
940 /// Mask (1 bit: 1 << 15)
941 pub const mask: u32 = 1 << offset;
942 /// Read-only values (empty)
943 pub mod R {}
944 /// Write-only values (empty)
945 pub mod W {}
946 /// Read-write values (empty)
947 pub mod RW {}
948 }
949
950 /// Break filter
951 pub mod BKF {
952 /// Offset (16 bits)
953 pub const offset: u32 = 16;
954 /// Mask (4 bits: 0b1111 << 16)
955 pub const mask: u32 = 0b1111 << offset;
956 /// Read-only values (empty)
957 pub mod R {}
958 /// Write-only values (empty)
959 pub mod W {}
960 /// Read-write values (empty)
961 pub mod RW {}
962 }
963}
964
965/// DMA control register
966pub mod DCR {
967
968 /// DMA burst length
969 pub mod DBL {
970 /// Offset (8 bits)
971 pub const offset: u32 = 8;
972 /// Mask (5 bits: 0b11111 << 8)
973 pub const mask: u32 = 0b11111 << offset;
974 /// Read-only values (empty)
975 pub mod R {}
976 /// Write-only values (empty)
977 pub mod W {}
978 /// Read-write values (empty)
979 pub mod RW {}
980 }
981
982 /// DMA base address
983 pub mod DBA {
984 /// Offset (0 bits)
985 pub const offset: u32 = 0;
986 /// Mask (5 bits: 0b11111 << 0)
987 pub const mask: u32 = 0b11111 << offset;
988 /// Read-only values (empty)
989 pub mod R {}
990 /// Write-only values (empty)
991 pub mod W {}
992 /// Read-write values (empty)
993 pub mod RW {}
994 }
995}
996
997/// DMA address for full transfer
998pub mod DMAR {
999
1000 /// DMA register for burst accesses
1001 pub mod DMAB {
1002 /// Offset (0 bits)
1003 pub const offset: u32 = 0;
1004 /// Mask (16 bits: 0xffff << 0)
1005 pub const mask: u32 = 0xffff << offset;
1006 /// Read-only values (empty)
1007 pub mod R {}
1008 /// Write-only values (empty)
1009 pub mod W {}
1010 /// Read-write values (empty)
1011 pub mod RW {}
1012 }
1013}
1014#[repr(C)]
1015pub struct RegisterBlock {
1016 /// control register 1
1017 pub CR1: RWRegister<u32>,
1018
1019 /// control register 2
1020 pub CR2: RWRegister<u32>,
1021
1022 _reserved1: [u8; 4],
1023
1024 /// DMA/Interrupt enable register
1025 pub DIER: RWRegister<u32>,
1026
1027 /// status register
1028 pub SR: RWRegister<u32>,
1029
1030 /// event generation register
1031 pub EGR: WORegister<u32>,
1032
1033 /// CCMR1_Output and CCMR1_Input
1034 /// CCMR1_Output: capture/compare mode register (output mode)
1035 /// CCMR1_Input: capture/compare mode register 1 (input mode)
1036 pub CCMR1: RWRegister<u32>,
1037
1038 _reserved2: [u8; 4],
1039
1040 /// capture/compare enable register
1041 pub CCER: RWRegister<u32>,
1042
1043 /// counter
1044 pub CNT: RWRegister<u32>,
1045
1046 /// prescaler
1047 pub PSC: RWRegister<u32>,
1048
1049 /// auto-reload register
1050 pub ARR: RWRegister<u32>,
1051
1052 /// repetition counter register
1053 pub RCR: RWRegister<u32>,
1054
1055 /// capture/compare register
1056 pub CCR1: RWRegister<u32>,
1057
1058 _reserved3: [u8; 12],
1059
1060 /// break and dead-time register
1061 pub BDTR: RWRegister<u32>,
1062
1063 /// DMA control register
1064 pub DCR: RWRegister<u32>,
1065
1066 /// DMA address for full transfer
1067 pub DMAR: RWRegister<u32>,
1068}
1069pub struct ResetValues {
1070 pub CR1: u32,
1071 pub CR2: u32,
1072 pub DIER: u32,
1073 pub SR: u32,
1074 pub EGR: u32,
1075 pub CCMR1: u32,
1076 pub CCER: u32,
1077 pub CNT: u32,
1078 pub PSC: u32,
1079 pub ARR: u32,
1080 pub RCR: u32,
1081 pub CCR1: u32,
1082 pub BDTR: u32,
1083 pub DCR: u32,
1084 pub DMAR: u32,
1085}
1086#[cfg(not(feature = "nosync"))]
1087pub struct Instance {
1088 pub(crate) addr: u32,
1089 pub(crate) _marker: PhantomData<*const RegisterBlock>,
1090}
1091#[cfg(not(feature = "nosync"))]
1092impl ::core::ops::Deref for Instance {
1093 type Target = RegisterBlock;
1094 #[inline(always)]
1095 fn deref(&self) -> &RegisterBlock {
1096 unsafe { &*(self.addr as *const _) }
1097 }
1098}
1099#[cfg(feature = "rtic")]
1100unsafe impl Send for Instance {}