stm32ral/stm32f3/peripherals/adc.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Analog-to-Digital Converter
4//!
5//! Used by: stm32f302, stm32f303, stm32f3x4
6
7use crate::{RORegister, RWRegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// interrupt and status register
12pub mod ISR {
13
14 /// JQOVF
15 pub mod JQOVF {
16 /// Offset (10 bits)
17 pub const offset: u32 = 10;
18 /// Mask (1 bit: 1 << 10)
19 pub const mask: u32 = 1 << offset;
20 /// Read-only values
21 pub mod R {
22
23 /// 0b0: No injected context queue overflow has occurred
24 pub const NoOverflow: u32 = 0b0;
25
26 /// 0b1: Injected context queue overflow has occurred
27 pub const Overflow: u32 = 0b1;
28 }
29 /// Write-only values
30 pub mod W {
31
32 /// 0b1: Clear injected context queue overflow flag
33 pub const Clear: u32 = 0b1;
34 }
35 /// Read-write values (empty)
36 pub mod RW {}
37 }
38
39 /// AWD3
40 pub mod AWD3 {
41 /// Offset (9 bits)
42 pub const offset: u32 = 9;
43 /// Mask (1 bit: 1 << 9)
44 pub const mask: u32 = 1 << offset;
45 /// Read-only values
46 pub mod R {
47
48 /// 0b0: No analog watchdog event occurred
49 pub const NoEvent: u32 = 0b0;
50
51 /// 0b1: Analog watchdog event occurred
52 pub const Event: u32 = 0b1;
53 }
54 /// Write-only values
55 pub mod W {
56
57 /// 0b1: Clear analog watchdog event occurred flag
58 pub const Clear: u32 = 0b1;
59 }
60 /// Read-write values (empty)
61 pub mod RW {}
62 }
63
64 /// AWD2
65 pub mod AWD2 {
66 /// Offset (8 bits)
67 pub const offset: u32 = 8;
68 /// Mask (1 bit: 1 << 8)
69 pub const mask: u32 = 1 << offset;
70 pub use super::AWD3::R;
71 pub use super::AWD3::W;
72 /// Read-write values (empty)
73 pub mod RW {}
74 }
75
76 /// AWD1
77 pub mod AWD1 {
78 /// Offset (7 bits)
79 pub const offset: u32 = 7;
80 /// Mask (1 bit: 1 << 7)
81 pub const mask: u32 = 1 << offset;
82 pub use super::AWD3::R;
83 pub use super::AWD3::W;
84 /// Read-write values (empty)
85 pub mod RW {}
86 }
87
88 /// JEOS
89 pub mod JEOS {
90 /// Offset (6 bits)
91 pub const offset: u32 = 6;
92 /// Mask (1 bit: 1 << 6)
93 pub const mask: u32 = 1 << offset;
94 /// Read-only values
95 pub mod R {
96
97 /// 0b0: Injected sequence is not complete
98 pub const NotComplete: u32 = 0b0;
99
100 /// 0b1: Injected sequence complete
101 pub const Complete: u32 = 0b1;
102 }
103 /// Write-only values
104 pub mod W {
105
106 /// 0b1: Clear Injected sequence complete flag
107 pub const Clear: u32 = 0b1;
108 }
109 /// Read-write values (empty)
110 pub mod RW {}
111 }
112
113 /// JEOC
114 pub mod JEOC {
115 /// Offset (5 bits)
116 pub const offset: u32 = 5;
117 /// Mask (1 bit: 1 << 5)
118 pub const mask: u32 = 1 << offset;
119 /// Read-only values
120 pub mod R {
121
122 /// 0b0: Injected conversion is not complete
123 pub const NotComplete: u32 = 0b0;
124
125 /// 0b1: Injected conversion complete
126 pub const Complete: u32 = 0b1;
127 }
128 /// Write-only values
129 pub mod W {
130
131 /// 0b1: Clear injected conversion complete flag
132 pub const Clear: u32 = 0b1;
133 }
134 /// Read-write values (empty)
135 pub mod RW {}
136 }
137
138 /// OVR
139 pub mod OVR {
140 /// Offset (4 bits)
141 pub const offset: u32 = 4;
142 /// Mask (1 bit: 1 << 4)
143 pub const mask: u32 = 1 << offset;
144 /// Read-only values
145 pub mod R {
146
147 /// 0b0: No overrun occurred
148 pub const NoOverrun: u32 = 0b0;
149
150 /// 0b1: Overrun occurred
151 pub const Overrun: u32 = 0b1;
152 }
153 /// Write-only values
154 pub mod W {
155
156 /// 0b1: Clear overrun occurred flag
157 pub const Clear: u32 = 0b1;
158 }
159 /// Read-write values (empty)
160 pub mod RW {}
161 }
162
163 /// EOS
164 pub mod EOS {
165 /// Offset (3 bits)
166 pub const offset: u32 = 3;
167 /// Mask (1 bit: 1 << 3)
168 pub const mask: u32 = 1 << offset;
169 /// Read-only values
170 pub mod R {
171
172 /// 0b0: Regular sequence is not complete
173 pub const NotComplete: u32 = 0b0;
174
175 /// 0b1: Regular sequence complete
176 pub const Complete: u32 = 0b1;
177 }
178 /// Write-only values
179 pub mod W {
180
181 /// 0b1: Clear regular sequence complete flag
182 pub const Clear: u32 = 0b1;
183 }
184 /// Read-write values (empty)
185 pub mod RW {}
186 }
187
188 /// EOC
189 pub mod EOC {
190 /// Offset (2 bits)
191 pub const offset: u32 = 2;
192 /// Mask (1 bit: 1 << 2)
193 pub const mask: u32 = 1 << offset;
194 /// Read-only values
195 pub mod R {
196
197 /// 0b0: Regular conversion is not complete
198 pub const NotComplete: u32 = 0b0;
199
200 /// 0b1: Regular conversion complete
201 pub const Complete: u32 = 0b1;
202 }
203 /// Write-only values
204 pub mod W {
205
206 /// 0b1: Clear regular conversion complete flag
207 pub const Clear: u32 = 0b1;
208 }
209 /// Read-write values (empty)
210 pub mod RW {}
211 }
212
213 /// EOSMP
214 pub mod EOSMP {
215 /// Offset (1 bits)
216 pub const offset: u32 = 1;
217 /// Mask (1 bit: 1 << 1)
218 pub const mask: u32 = 1 << offset;
219 /// Read-only values
220 pub mod R {
221
222 /// 0b0: End of sampling phase no yet reached
223 pub const NotEnded: u32 = 0b0;
224
225 /// 0b1: End of sampling phase reached
226 pub const Ended: u32 = 0b1;
227 }
228 /// Write-only values
229 pub mod W {
230
231 /// 0b1: Clear end of sampling phase reached flag
232 pub const Clear: u32 = 0b1;
233 }
234 /// Read-write values (empty)
235 pub mod RW {}
236 }
237
238 /// ADRDY
239 pub mod ADRDY {
240 /// Offset (0 bits)
241 pub const offset: u32 = 0;
242 /// Mask (1 bit: 1 << 0)
243 pub const mask: u32 = 1 << offset;
244 /// Read-only values
245 pub mod R {
246
247 /// 0b0: ADC is not ready to start conversion
248 pub const NotReady: u32 = 0b0;
249
250 /// 0b1: ADC is ready to start conversion
251 pub const Ready: u32 = 0b1;
252 }
253 /// Write-only values
254 pub mod W {
255
256 /// 0b1: Clear ADC is ready to start conversion flag
257 pub const Clear: u32 = 0b1;
258 }
259 /// Read-write values (empty)
260 pub mod RW {}
261 }
262}
263
264/// interrupt enable register
265pub mod IER {
266
267 /// JQOVFIE
268 pub mod JQOVFIE {
269 /// Offset (10 bits)
270 pub const offset: u32 = 10;
271 /// Mask (1 bit: 1 << 10)
272 pub const mask: u32 = 1 << offset;
273 /// Read-only values (empty)
274 pub mod R {}
275 /// Write-only values (empty)
276 pub mod W {}
277 /// Read-write values
278 pub mod RW {
279
280 /// 0b0: Injected context queue overflow interrupt disabled
281 pub const Disabled: u32 = 0b0;
282
283 /// 0b1: Injected context queue overflow interrupt enabled
284 pub const Enabled: u32 = 0b1;
285 }
286 }
287
288 /// AWD3IE
289 pub mod AWD3IE {
290 /// Offset (9 bits)
291 pub const offset: u32 = 9;
292 /// Mask (1 bit: 1 << 9)
293 pub const mask: u32 = 1 << offset;
294 /// Read-only values (empty)
295 pub mod R {}
296 /// Write-only values (empty)
297 pub mod W {}
298 /// Read-write values
299 pub mod RW {
300
301 /// 0b0: Analog watchdog interrupt disabled
302 pub const Disabled: u32 = 0b0;
303
304 /// 0b1: Analog watchdog interrupt enabled
305 pub const Enabled: u32 = 0b1;
306 }
307 }
308
309 /// AWD2IE
310 pub mod AWD2IE {
311 /// Offset (8 bits)
312 pub const offset: u32 = 8;
313 /// Mask (1 bit: 1 << 8)
314 pub const mask: u32 = 1 << offset;
315 /// Read-only values (empty)
316 pub mod R {}
317 /// Write-only values (empty)
318 pub mod W {}
319 pub use super::AWD3IE::RW;
320 }
321
322 /// AWD1IE
323 pub mod AWD1IE {
324 /// Offset (7 bits)
325 pub const offset: u32 = 7;
326 /// Mask (1 bit: 1 << 7)
327 pub const mask: u32 = 1 << offset;
328 /// Read-only values (empty)
329 pub mod R {}
330 /// Write-only values (empty)
331 pub mod W {}
332 pub use super::AWD3IE::RW;
333 }
334
335 /// JEOSIE
336 pub mod JEOSIE {
337 /// Offset (6 bits)
338 pub const offset: u32 = 6;
339 /// Mask (1 bit: 1 << 6)
340 pub const mask: u32 = 1 << offset;
341 /// Read-only values (empty)
342 pub mod R {}
343 /// Write-only values (empty)
344 pub mod W {}
345 /// Read-write values
346 pub mod RW {
347
348 /// 0b0: End of injected sequence interrupt disabled
349 pub const Disabled: u32 = 0b0;
350
351 /// 0b1: End of injected sequence interrupt enabled
352 pub const Enabled: u32 = 0b1;
353 }
354 }
355
356 /// JEOCIE
357 pub mod JEOCIE {
358 /// Offset (5 bits)
359 pub const offset: u32 = 5;
360 /// Mask (1 bit: 1 << 5)
361 pub const mask: u32 = 1 << offset;
362 /// Read-only values (empty)
363 pub mod R {}
364 /// Write-only values (empty)
365 pub mod W {}
366 /// Read-write values
367 pub mod RW {
368
369 /// 0b0: End of injected conversion interrupt disabled
370 pub const Disabled: u32 = 0b0;
371
372 /// 0b1: End of injected conversion interrupt enabled
373 pub const Enabled: u32 = 0b1;
374 }
375 }
376
377 /// OVRIE
378 pub mod OVRIE {
379 /// Offset (4 bits)
380 pub const offset: u32 = 4;
381 /// Mask (1 bit: 1 << 4)
382 pub const mask: u32 = 1 << offset;
383 /// Read-only values (empty)
384 pub mod R {}
385 /// Write-only values (empty)
386 pub mod W {}
387 /// Read-write values
388 pub mod RW {
389
390 /// 0b0: Overrun interrupt disabled
391 pub const Disabled: u32 = 0b0;
392
393 /// 0b1: Overrun interrupt enabled
394 pub const Enabled: u32 = 0b1;
395 }
396 }
397
398 /// EOSIE
399 pub mod EOSIE {
400 /// Offset (3 bits)
401 pub const offset: u32 = 3;
402 /// Mask (1 bit: 1 << 3)
403 pub const mask: u32 = 1 << offset;
404 /// Read-only values (empty)
405 pub mod R {}
406 /// Write-only values (empty)
407 pub mod W {}
408 /// Read-write values
409 pub mod RW {
410
411 /// 0b0: End of regular sequence interrupt disabled
412 pub const Disabled: u32 = 0b0;
413
414 /// 0b1: End of regular sequence interrupt enabled
415 pub const Enabled: u32 = 0b1;
416 }
417 }
418
419 /// EOCIE
420 pub mod EOCIE {
421 /// Offset (2 bits)
422 pub const offset: u32 = 2;
423 /// Mask (1 bit: 1 << 2)
424 pub const mask: u32 = 1 << offset;
425 /// Read-only values (empty)
426 pub mod R {}
427 /// Write-only values (empty)
428 pub mod W {}
429 /// Read-write values
430 pub mod RW {
431
432 /// 0b0: End of regular conversion interrupt disabled
433 pub const Disabled: u32 = 0b0;
434
435 /// 0b1: End of regular conversion interrupt enabled
436 pub const Enabled: u32 = 0b1;
437 }
438 }
439
440 /// EOSMPIE
441 pub mod EOSMPIE {
442 /// Offset (1 bits)
443 pub const offset: u32 = 1;
444 /// Mask (1 bit: 1 << 1)
445 pub const mask: u32 = 1 << offset;
446 /// Read-only values (empty)
447 pub mod R {}
448 /// Write-only values (empty)
449 pub mod W {}
450 /// Read-write values
451 pub mod RW {
452
453 /// 0b0: End of regular conversion sampling phase interrupt disabled
454 pub const Disabled: u32 = 0b0;
455
456 /// 0b1: End of regular conversion sampling phase interrupt enabled
457 pub const Enabled: u32 = 0b1;
458 }
459 }
460
461 /// ADRDYIE
462 pub mod ADRDYIE {
463 /// Offset (0 bits)
464 pub const offset: u32 = 0;
465 /// Mask (1 bit: 1 << 0)
466 pub const mask: u32 = 1 << offset;
467 /// Read-only values (empty)
468 pub mod R {}
469 /// Write-only values (empty)
470 pub mod W {}
471 /// Read-write values
472 pub mod RW {
473
474 /// 0b0: ADC ready interrupt disabled
475 pub const Disabled: u32 = 0b0;
476
477 /// 0b1: ADC ready interrupt enabled
478 pub const Enabled: u32 = 0b1;
479 }
480 }
481}
482
483/// control register
484pub mod CR {
485
486 /// ADCAL
487 pub mod ADCAL {
488 /// Offset (31 bits)
489 pub const offset: u32 = 31;
490 /// Mask (1 bit: 1 << 31)
491 pub const mask: u32 = 1 << offset;
492 /// Read-only values (empty)
493 pub mod R {}
494 /// Write-only values (empty)
495 pub mod W {}
496 /// Read-write values
497 pub mod RW {
498
499 /// 0b0: Calibration complete
500 pub const Complete: u32 = 0b0;
501
502 /// 0b1: Start the calibration of the ADC
503 pub const Calibration: u32 = 0b1;
504 }
505 }
506
507 /// ADCALDIF
508 pub mod ADCALDIF {
509 /// Offset (30 bits)
510 pub const offset: u32 = 30;
511 /// Mask (1 bit: 1 << 30)
512 pub const mask: u32 = 1 << offset;
513 /// Read-only values (empty)
514 pub mod R {}
515 /// Write-only values (empty)
516 pub mod W {}
517 /// Read-write values
518 pub mod RW {
519
520 /// 0b0: Calibration for single-ended mode
521 pub const SingleEnded: u32 = 0b0;
522
523 /// 0b1: Calibration for differential mode
524 pub const Differential: u32 = 0b1;
525 }
526 }
527
528 /// ADVREGEN
529 pub mod ADVREGEN {
530 /// Offset (28 bits)
531 pub const offset: u32 = 28;
532 /// Mask (2 bits: 0b11 << 28)
533 pub const mask: u32 = 0b11 << offset;
534 /// Read-only values (empty)
535 pub mod R {}
536 /// Write-only values (empty)
537 pub mod W {}
538 /// Read-write values
539 pub mod RW {
540
541 /// 0b00: Intermediate state required when moving the ADC voltage regulator between states
542 pub const Intermediate: u32 = 0b00;
543
544 /// 0b01: ADC voltage regulator enabled
545 pub const Enabled: u32 = 0b01;
546
547 /// 0b10: ADC voltage regulator disabled
548 pub const Disabled: u32 = 0b10;
549 }
550 }
551
552 /// JADSTP
553 pub mod JADSTP {
554 /// Offset (5 bits)
555 pub const offset: u32 = 5;
556 /// Mask (1 bit: 1 << 5)
557 pub const mask: u32 = 1 << offset;
558 /// Read-only values
559 pub mod R {
560
561 /// 0b0: No stop command active
562 pub const NotStopping: u32 = 0b0;
563
564 /// 0b1: ADC stopping conversion
565 pub const Stopping: u32 = 0b1;
566 }
567 /// Write-only values
568 pub mod W {
569
570 /// 0b1: Stop the active conversion
571 pub const StopConversion: u32 = 0b1;
572 }
573 /// Read-write values (empty)
574 pub mod RW {}
575 }
576
577 /// ADSTP
578 pub mod ADSTP {
579 /// Offset (4 bits)
580 pub const offset: u32 = 4;
581 /// Mask (1 bit: 1 << 4)
582 pub const mask: u32 = 1 << offset;
583 pub use super::JADSTP::R;
584 pub use super::JADSTP::W;
585 /// Read-write values (empty)
586 pub mod RW {}
587 }
588
589 /// JADSTART
590 pub mod JADSTART {
591 /// Offset (3 bits)
592 pub const offset: u32 = 3;
593 /// Mask (1 bit: 1 << 3)
594 pub const mask: u32 = 1 << offset;
595 /// Read-only values
596 pub mod R {
597
598 /// 0b0: No conversion ongoing
599 pub const NotActive: u32 = 0b0;
600
601 /// 0b1: ADC operating and may be converting
602 pub const Active: u32 = 0b1;
603 }
604 /// Write-only values
605 pub mod W {
606
607 /// 0b1: Start the ADC conversion (may be delayed for hardware triggers)
608 pub const StartConversion: u32 = 0b1;
609 }
610 /// Read-write values (empty)
611 pub mod RW {}
612 }
613
614 /// ADSTART
615 pub mod ADSTART {
616 /// Offset (2 bits)
617 pub const offset: u32 = 2;
618 /// Mask (1 bit: 1 << 2)
619 pub const mask: u32 = 1 << offset;
620 pub use super::JADSTART::R;
621 pub use super::JADSTART::W;
622 /// Read-write values (empty)
623 pub mod RW {}
624 }
625
626 /// ADDIS
627 pub mod ADDIS {
628 /// Offset (1 bits)
629 pub const offset: u32 = 1;
630 /// Mask (1 bit: 1 << 1)
631 pub const mask: u32 = 1 << offset;
632 /// Read-only values
633 pub mod R {
634
635 /// 0b0: No disable command active
636 pub const NotDisabling: u32 = 0b0;
637
638 /// 0b1: ADC disabling
639 pub const Disabling: u32 = 0b1;
640 }
641 /// Write-only values
642 pub mod W {
643
644 /// 0b1: Disable the ADC
645 pub const Disable: u32 = 0b1;
646 }
647 /// Read-write values (empty)
648 pub mod RW {}
649 }
650
651 /// ADEN
652 pub mod ADEN {
653 /// Offset (0 bits)
654 pub const offset: u32 = 0;
655 /// Mask (1 bit: 1 << 0)
656 pub const mask: u32 = 1 << offset;
657 /// Read-only values
658 pub mod R {
659
660 /// 0b0: ADC disabled
661 pub const Disabled: u32 = 0b0;
662
663 /// 0b1: ADC enabled
664 pub const Enabled: u32 = 0b1;
665 }
666 /// Write-only values
667 pub mod W {
668
669 /// 0b1: Enable the ADC
670 pub const Enabled: u32 = 0b1;
671 }
672 /// Read-write values (empty)
673 pub mod RW {}
674 }
675}
676
677/// configuration register
678pub mod CFGR {
679
680 /// AWDCH1CH
681 pub mod AWD1CH {
682 /// Offset (26 bits)
683 pub const offset: u32 = 26;
684 /// Mask (5 bits: 0b11111 << 26)
685 pub const mask: u32 = 0b11111 << offset;
686 /// Read-only values (empty)
687 pub mod R {}
688 /// Write-only values (empty)
689 pub mod W {}
690 /// Read-write values (empty)
691 pub mod RW {}
692 }
693
694 /// JAUTO
695 pub mod JAUTO {
696 /// Offset (25 bits)
697 pub const offset: u32 = 25;
698 /// Mask (1 bit: 1 << 25)
699 pub const mask: u32 = 1 << offset;
700 /// Read-only values (empty)
701 pub mod R {}
702 /// Write-only values (empty)
703 pub mod W {}
704 /// Read-write values
705 pub mod RW {
706
707 /// 0b0: Automatic injected group conversion disabled
708 pub const Disabled: u32 = 0b0;
709
710 /// 0b1: Automatic injected group conversion enabled
711 pub const Enabled: u32 = 0b1;
712 }
713 }
714
715 /// JAWD1EN
716 pub mod JAWD1EN {
717 /// Offset (24 bits)
718 pub const offset: u32 = 24;
719 /// Mask (1 bit: 1 << 24)
720 pub const mask: u32 = 1 << offset;
721 /// Read-only values (empty)
722 pub mod R {}
723 /// Write-only values (empty)
724 pub mod W {}
725 /// Read-write values
726 pub mod RW {
727
728 /// 0b0: Analog watchdog 1 disabled on injected channels
729 pub const Disabled: u32 = 0b0;
730
731 /// 0b1: Analog watchdog 1 enabled on injected channels
732 pub const Enabled: u32 = 0b1;
733 }
734 }
735
736 /// AWD1EN
737 pub mod AWD1EN {
738 /// Offset (23 bits)
739 pub const offset: u32 = 23;
740 /// Mask (1 bit: 1 << 23)
741 pub const mask: u32 = 1 << offset;
742 /// Read-only values (empty)
743 pub mod R {}
744 /// Write-only values (empty)
745 pub mod W {}
746 /// Read-write values
747 pub mod RW {
748
749 /// 0b0: Analog watchdog 1 disabled on regular channels
750 pub const Disabled: u32 = 0b0;
751
752 /// 0b1: Analog watchdog 1 enabled on regular channels
753 pub const Enabled: u32 = 0b1;
754 }
755 }
756
757 /// AWD1SGL
758 pub mod AWD1SGL {
759 /// Offset (22 bits)
760 pub const offset: u32 = 22;
761 /// Mask (1 bit: 1 << 22)
762 pub const mask: u32 = 1 << offset;
763 /// Read-only values (empty)
764 pub mod R {}
765 /// Write-only values (empty)
766 pub mod W {}
767 /// Read-write values
768 pub mod RW {
769
770 /// 0b0: Analog watchdog 1 enabled on all channels
771 pub const All: u32 = 0b0;
772
773 /// 0b1: Analog watchdog 1 enabled on single channel selected in AWD1CH
774 pub const Single: u32 = 0b1;
775 }
776 }
777
778 /// JQM
779 pub mod JQM {
780 /// Offset (21 bits)
781 pub const offset: u32 = 21;
782 /// Mask (1 bit: 1 << 21)
783 pub const mask: u32 = 1 << offset;
784 /// Read-only values (empty)
785 pub mod R {}
786 /// Write-only values (empty)
787 pub mod W {}
788 /// Read-write values
789 pub mod RW {
790
791 /// 0b0: JSQR Mode 0: Queue maintains the last written configuration into JSQR
792 pub const Mode0: u32 = 0b0;
793
794 /// 0b1: JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence
795 pub const Mode1: u32 = 0b1;
796 }
797 }
798
799 /// JDISCEN
800 pub mod JDISCEN {
801 /// Offset (20 bits)
802 pub const offset: u32 = 20;
803 /// Mask (1 bit: 1 << 20)
804 pub const mask: u32 = 1 << offset;
805 /// Read-only values (empty)
806 pub mod R {}
807 /// Write-only values (empty)
808 pub mod W {}
809 /// Read-write values
810 pub mod RW {
811
812 /// 0b0: Discontinuous mode on injected channels disabled
813 pub const Disabled: u32 = 0b0;
814
815 /// 0b1: Discontinuous mode on injected channels enabled
816 pub const Enabled: u32 = 0b1;
817 }
818 }
819
820 /// DISCNUM
821 pub mod DISCNUM {
822 /// Offset (17 bits)
823 pub const offset: u32 = 17;
824 /// Mask (3 bits: 0b111 << 17)
825 pub const mask: u32 = 0b111 << offset;
826 /// Read-only values (empty)
827 pub mod R {}
828 /// Write-only values (empty)
829 pub mod W {}
830 /// Read-write values (empty)
831 pub mod RW {}
832 }
833
834 /// DISCEN
835 pub mod DISCEN {
836 /// Offset (16 bits)
837 pub const offset: u32 = 16;
838 /// Mask (1 bit: 1 << 16)
839 pub const mask: u32 = 1 << offset;
840 /// Read-only values (empty)
841 pub mod R {}
842 /// Write-only values (empty)
843 pub mod W {}
844 /// Read-write values
845 pub mod RW {
846
847 /// 0b0: Discontinuous mode on regular channels disabled
848 pub const Disabled: u32 = 0b0;
849
850 /// 0b1: Discontinuous mode on regular channels enabled
851 pub const Enabled: u32 = 0b1;
852 }
853 }
854
855 /// AUTDLY
856 pub mod AUTDLY {
857 /// Offset (14 bits)
858 pub const offset: u32 = 14;
859 /// Mask (1 bit: 1 << 14)
860 pub const mask: u32 = 1 << offset;
861 /// Read-only values (empty)
862 pub mod R {}
863 /// Write-only values (empty)
864 pub mod W {}
865 /// Read-write values
866 pub mod RW {
867
868 /// 0b0: Auto delayed conversion mode off
869 pub const Off: u32 = 0b0;
870
871 /// 0b1: Auto delayed conversion mode on
872 pub const On: u32 = 0b1;
873 }
874 }
875
876 /// CONT
877 pub mod CONT {
878 /// Offset (13 bits)
879 pub const offset: u32 = 13;
880 /// Mask (1 bit: 1 << 13)
881 pub const mask: u32 = 1 << offset;
882 /// Read-only values (empty)
883 pub mod R {}
884 /// Write-only values (empty)
885 pub mod W {}
886 /// Read-write values
887 pub mod RW {
888
889 /// 0b0: Single conversion mode
890 pub const Single: u32 = 0b0;
891
892 /// 0b1: Continuous conversion mode
893 pub const Continuous: u32 = 0b1;
894 }
895 }
896
897 /// OVRMOD
898 pub mod OVRMOD {
899 /// Offset (12 bits)
900 pub const offset: u32 = 12;
901 /// Mask (1 bit: 1 << 12)
902 pub const mask: u32 = 1 << offset;
903 /// Read-only values (empty)
904 pub mod R {}
905 /// Write-only values (empty)
906 pub mod W {}
907 /// Read-write values
908 pub mod RW {
909
910 /// 0b0: Preserve DR register when an overrun is detected
911 pub const Preserve: u32 = 0b0;
912
913 /// 0b1: Overwrite DR register when an overrun is detected
914 pub const Overwrite: u32 = 0b1;
915 }
916 }
917
918 /// EXTEN
919 pub mod EXTEN {
920 /// Offset (10 bits)
921 pub const offset: u32 = 10;
922 /// Mask (2 bits: 0b11 << 10)
923 pub const mask: u32 = 0b11 << offset;
924 /// Read-only values (empty)
925 pub mod R {}
926 /// Write-only values (empty)
927 pub mod W {}
928 /// Read-write values
929 pub mod RW {
930
931 /// 0b00: Trigger detection disabled
932 pub const Disabled: u32 = 0b00;
933
934 /// 0b01: Trigger detection on the rising edge
935 pub const RisingEdge: u32 = 0b01;
936
937 /// 0b10: Trigger detection on the falling edge
938 pub const FallingEdge: u32 = 0b10;
939
940 /// 0b11: Trigger detection on both the rising and falling edges
941 pub const BothEdges: u32 = 0b11;
942 }
943 }
944
945 /// EXTSEL
946 pub mod EXTSEL {
947 /// Offset (6 bits)
948 pub const offset: u32 = 6;
949 /// Mask (4 bits: 0b1111 << 6)
950 pub const mask: u32 = 0b1111 << offset;
951 /// Read-only values (empty)
952 pub mod R {}
953 /// Write-only values (empty)
954 pub mod W {}
955 /// Read-write values
956 pub mod RW {
957
958 /// 0b0000: Timer 1 CC1 event
959 pub const TIM1_CC1: u32 = 0b0000;
960
961 /// 0b0001: Timer 1 CC2 event
962 pub const TIM1_CC2: u32 = 0b0001;
963
964 /// 0b0010: Timer 1 CC3 event
965 pub const TIM1_CC3: u32 = 0b0010;
966
967 /// 0b0011: Timer 2 CC2 event
968 pub const TIM2_CC2: u32 = 0b0011;
969
970 /// 0b0100: Timer 3 TRGO event
971 pub const TIM3_TRGO: u32 = 0b0100;
972
973 /// 0b0110: EXTI line 11
974 pub const EXTI11: u32 = 0b0110;
975
976 /// 0b0111: HRTIM_ADCTRG1 event
977 pub const HRTIM_ADCTRG1: u32 = 0b0111;
978
979 /// 0b1000: HRTIM_ADCTRG3 event
980 pub const HRTIM_ADCTRG3: u32 = 0b1000;
981
982 /// 0b1001: Timer 1 TRGO event
983 pub const TIM1_TRGO: u32 = 0b1001;
984
985 /// 0b1010: Timer 1 TRGO2 event
986 pub const TIM1_TRGO2: u32 = 0b1010;
987
988 /// 0b1011: Timer 2 TRGO event
989 pub const TIM2_TRGO: u32 = 0b1011;
990
991 /// 0b1101: Timer 6 TRGO event
992 pub const TIM6_TRGO: u32 = 0b1101;
993
994 /// 0b1110: Timer 15 TRGO event
995 pub const TIM15_TRGO: u32 = 0b1110;
996
997 /// 0b1111: Timer 3 CC4 event
998 pub const TIM3_CC4: u32 = 0b1111;
999 }
1000 }
1001
1002 /// ALIGN
1003 pub mod ALIGN {
1004 /// Offset (5 bits)
1005 pub const offset: u32 = 5;
1006 /// Mask (1 bit: 1 << 5)
1007 pub const mask: u32 = 1 << offset;
1008 /// Read-only values (empty)
1009 pub mod R {}
1010 /// Write-only values (empty)
1011 pub mod W {}
1012 /// Read-write values
1013 pub mod RW {
1014
1015 /// 0b0: Right alignment
1016 pub const Right: u32 = 0b0;
1017
1018 /// 0b1: Left alignment
1019 pub const Left: u32 = 0b1;
1020 }
1021 }
1022
1023 /// RES
1024 pub mod RES {
1025 /// Offset (3 bits)
1026 pub const offset: u32 = 3;
1027 /// Mask (2 bits: 0b11 << 3)
1028 pub const mask: u32 = 0b11 << offset;
1029 /// Read-only values (empty)
1030 pub mod R {}
1031 /// Write-only values (empty)
1032 pub mod W {}
1033 /// Read-write values
1034 pub mod RW {
1035
1036 /// 0b00: 12-bit
1037 pub const Bits12: u32 = 0b00;
1038
1039 /// 0b01: 10-bit
1040 pub const Bits10: u32 = 0b01;
1041
1042 /// 0b10: 8-bit
1043 pub const Bits8: u32 = 0b10;
1044
1045 /// 0b11: 6-bit
1046 pub const Bits6: u32 = 0b11;
1047 }
1048 }
1049
1050 /// DMACFG
1051 pub mod DMACFG {
1052 /// Offset (1 bits)
1053 pub const offset: u32 = 1;
1054 /// Mask (1 bit: 1 << 1)
1055 pub const mask: u32 = 1 << offset;
1056 /// Read-only values (empty)
1057 pub mod R {}
1058 /// Write-only values (empty)
1059 pub mod W {}
1060 /// Read-write values
1061 pub mod RW {
1062
1063 /// 0b0: DMA One Shot Mode selected
1064 pub const OneShot: u32 = 0b0;
1065
1066 /// 0b1: DMA circular mode selected
1067 pub const Circular: u32 = 0b1;
1068 }
1069 }
1070
1071 /// DMAEN
1072 pub mod DMAEN {
1073 /// Offset (0 bits)
1074 pub const offset: u32 = 0;
1075 /// Mask (1 bit: 1 << 0)
1076 pub const mask: u32 = 1 << offset;
1077 /// Read-only values (empty)
1078 pub mod R {}
1079 /// Write-only values (empty)
1080 pub mod W {}
1081 /// Read-write values
1082 pub mod RW {
1083
1084 /// 0b0: DMA disabled
1085 pub const Disabled: u32 = 0b0;
1086
1087 /// 0b1: DMA enabled
1088 pub const Enabled: u32 = 0b1;
1089 }
1090 }
1091}
1092
1093/// sample time register 1
1094pub mod SMPR1 {
1095
1096 /// SMP9
1097 pub mod SMP9 {
1098 /// Offset (27 bits)
1099 pub const offset: u32 = 27;
1100 /// Mask (3 bits: 0b111 << 27)
1101 pub const mask: u32 = 0b111 << offset;
1102 /// Read-only values (empty)
1103 pub mod R {}
1104 /// Write-only values (empty)
1105 pub mod W {}
1106 /// Read-write values
1107 pub mod RW {
1108
1109 /// 0b000: 1.5 ADC clock cycles
1110 pub const Cycles1_5: u32 = 0b000;
1111
1112 /// 0b001: 2.5 ADC clock cycles
1113 pub const Cycles2_5: u32 = 0b001;
1114
1115 /// 0b010: 4.5 ADC clock cycles
1116 pub const Cycles4_5: u32 = 0b010;
1117
1118 /// 0b011: 7.5 ADC clock cycles
1119 pub const Cycles7_5: u32 = 0b011;
1120
1121 /// 0b100: 19.5 ADC clock cycles
1122 pub const Cycles19_5: u32 = 0b100;
1123
1124 /// 0b101: 61.5 ADC clock cycles
1125 pub const Cycles61_5: u32 = 0b101;
1126
1127 /// 0b110: 181.5 ADC clock cycles
1128 pub const Cycles181_5: u32 = 0b110;
1129
1130 /// 0b111: 601.5 ADC clock cycles
1131 pub const Cycles601_5: u32 = 0b111;
1132 }
1133 }
1134
1135 /// SMP8
1136 pub mod SMP8 {
1137 /// Offset (24 bits)
1138 pub const offset: u32 = 24;
1139 /// Mask (3 bits: 0b111 << 24)
1140 pub const mask: u32 = 0b111 << offset;
1141 /// Read-only values (empty)
1142 pub mod R {}
1143 /// Write-only values (empty)
1144 pub mod W {}
1145 pub use super::SMP9::RW;
1146 }
1147
1148 /// SMP7
1149 pub mod SMP7 {
1150 /// Offset (21 bits)
1151 pub const offset: u32 = 21;
1152 /// Mask (3 bits: 0b111 << 21)
1153 pub const mask: u32 = 0b111 << offset;
1154 /// Read-only values (empty)
1155 pub mod R {}
1156 /// Write-only values (empty)
1157 pub mod W {}
1158 pub use super::SMP9::RW;
1159 }
1160
1161 /// SMP6
1162 pub mod SMP6 {
1163 /// Offset (18 bits)
1164 pub const offset: u32 = 18;
1165 /// Mask (3 bits: 0b111 << 18)
1166 pub const mask: u32 = 0b111 << offset;
1167 /// Read-only values (empty)
1168 pub mod R {}
1169 /// Write-only values (empty)
1170 pub mod W {}
1171 pub use super::SMP9::RW;
1172 }
1173
1174 /// SMP5
1175 pub mod SMP5 {
1176 /// Offset (15 bits)
1177 pub const offset: u32 = 15;
1178 /// Mask (3 bits: 0b111 << 15)
1179 pub const mask: u32 = 0b111 << offset;
1180 /// Read-only values (empty)
1181 pub mod R {}
1182 /// Write-only values (empty)
1183 pub mod W {}
1184 pub use super::SMP9::RW;
1185 }
1186
1187 /// SMP4
1188 pub mod SMP4 {
1189 /// Offset (12 bits)
1190 pub const offset: u32 = 12;
1191 /// Mask (3 bits: 0b111 << 12)
1192 pub const mask: u32 = 0b111 << offset;
1193 /// Read-only values (empty)
1194 pub mod R {}
1195 /// Write-only values (empty)
1196 pub mod W {}
1197 pub use super::SMP9::RW;
1198 }
1199
1200 /// SMP3
1201 pub mod SMP3 {
1202 /// Offset (9 bits)
1203 pub const offset: u32 = 9;
1204 /// Mask (3 bits: 0b111 << 9)
1205 pub const mask: u32 = 0b111 << offset;
1206 /// Read-only values (empty)
1207 pub mod R {}
1208 /// Write-only values (empty)
1209 pub mod W {}
1210 pub use super::SMP9::RW;
1211 }
1212
1213 /// SMP2
1214 pub mod SMP2 {
1215 /// Offset (6 bits)
1216 pub const offset: u32 = 6;
1217 /// Mask (3 bits: 0b111 << 6)
1218 pub const mask: u32 = 0b111 << offset;
1219 /// Read-only values (empty)
1220 pub mod R {}
1221 /// Write-only values (empty)
1222 pub mod W {}
1223 pub use super::SMP9::RW;
1224 }
1225
1226 /// SMP1
1227 pub mod SMP1 {
1228 /// Offset (3 bits)
1229 pub const offset: u32 = 3;
1230 /// Mask (3 bits: 0b111 << 3)
1231 pub const mask: u32 = 0b111 << offset;
1232 /// Read-only values (empty)
1233 pub mod R {}
1234 /// Write-only values (empty)
1235 pub mod W {}
1236 pub use super::SMP9::RW;
1237 }
1238}
1239
1240/// sample time register 2
1241pub mod SMPR2 {
1242
1243 /// SMP18
1244 pub mod SMP18 {
1245 /// Offset (24 bits)
1246 pub const offset: u32 = 24;
1247 /// Mask (3 bits: 0b111 << 24)
1248 pub const mask: u32 = 0b111 << offset;
1249 /// Read-only values (empty)
1250 pub mod R {}
1251 /// Write-only values (empty)
1252 pub mod W {}
1253 /// Read-write values
1254 pub mod RW {
1255
1256 /// 0b000: 1.5 ADC clock cycles
1257 pub const Cycles1_5: u32 = 0b000;
1258
1259 /// 0b001: 2.5 ADC clock cycles
1260 pub const Cycles2_5: u32 = 0b001;
1261
1262 /// 0b010: 4.5 ADC clock cycles
1263 pub const Cycles4_5: u32 = 0b010;
1264
1265 /// 0b011: 7.5 ADC clock cycles
1266 pub const Cycles7_5: u32 = 0b011;
1267
1268 /// 0b100: 19.5 ADC clock cycles
1269 pub const Cycles19_5: u32 = 0b100;
1270
1271 /// 0b101: 61.5 ADC clock cycles
1272 pub const Cycles61_5: u32 = 0b101;
1273
1274 /// 0b110: 181.5 ADC clock cycles
1275 pub const Cycles181_5: u32 = 0b110;
1276
1277 /// 0b111: 601.5 ADC clock cycles
1278 pub const Cycles601_5: u32 = 0b111;
1279 }
1280 }
1281
1282 /// SMP17
1283 pub mod SMP17 {
1284 /// Offset (21 bits)
1285 pub const offset: u32 = 21;
1286 /// Mask (3 bits: 0b111 << 21)
1287 pub const mask: u32 = 0b111 << offset;
1288 /// Read-only values (empty)
1289 pub mod R {}
1290 /// Write-only values (empty)
1291 pub mod W {}
1292 pub use super::SMP18::RW;
1293 }
1294
1295 /// SMP16
1296 pub mod SMP16 {
1297 /// Offset (18 bits)
1298 pub const offset: u32 = 18;
1299 /// Mask (3 bits: 0b111 << 18)
1300 pub const mask: u32 = 0b111 << offset;
1301 /// Read-only values (empty)
1302 pub mod R {}
1303 /// Write-only values (empty)
1304 pub mod W {}
1305 pub use super::SMP18::RW;
1306 }
1307
1308 /// SMP15
1309 pub mod SMP15 {
1310 /// Offset (15 bits)
1311 pub const offset: u32 = 15;
1312 /// Mask (3 bits: 0b111 << 15)
1313 pub const mask: u32 = 0b111 << offset;
1314 /// Read-only values (empty)
1315 pub mod R {}
1316 /// Write-only values (empty)
1317 pub mod W {}
1318 pub use super::SMP18::RW;
1319 }
1320
1321 /// SMP14
1322 pub mod SMP14 {
1323 /// Offset (12 bits)
1324 pub const offset: u32 = 12;
1325 /// Mask (3 bits: 0b111 << 12)
1326 pub const mask: u32 = 0b111 << offset;
1327 /// Read-only values (empty)
1328 pub mod R {}
1329 /// Write-only values (empty)
1330 pub mod W {}
1331 pub use super::SMP18::RW;
1332 }
1333
1334 /// SMP13
1335 pub mod SMP13 {
1336 /// Offset (9 bits)
1337 pub const offset: u32 = 9;
1338 /// Mask (3 bits: 0b111 << 9)
1339 pub const mask: u32 = 0b111 << offset;
1340 /// Read-only values (empty)
1341 pub mod R {}
1342 /// Write-only values (empty)
1343 pub mod W {}
1344 pub use super::SMP18::RW;
1345 }
1346
1347 /// SMP12
1348 pub mod SMP12 {
1349 /// Offset (6 bits)
1350 pub const offset: u32 = 6;
1351 /// Mask (3 bits: 0b111 << 6)
1352 pub const mask: u32 = 0b111 << offset;
1353 /// Read-only values (empty)
1354 pub mod R {}
1355 /// Write-only values (empty)
1356 pub mod W {}
1357 pub use super::SMP18::RW;
1358 }
1359
1360 /// SMP11
1361 pub mod SMP11 {
1362 /// Offset (3 bits)
1363 pub const offset: u32 = 3;
1364 /// Mask (3 bits: 0b111 << 3)
1365 pub const mask: u32 = 0b111 << offset;
1366 /// Read-only values (empty)
1367 pub mod R {}
1368 /// Write-only values (empty)
1369 pub mod W {}
1370 pub use super::SMP18::RW;
1371 }
1372
1373 /// SMP10
1374 pub mod SMP10 {
1375 /// Offset (0 bits)
1376 pub const offset: u32 = 0;
1377 /// Mask (3 bits: 0b111 << 0)
1378 pub const mask: u32 = 0b111 << offset;
1379 /// Read-only values (empty)
1380 pub mod R {}
1381 /// Write-only values (empty)
1382 pub mod W {}
1383 pub use super::SMP18::RW;
1384 }
1385}
1386
1387/// watchdog threshold register 1
1388pub mod TR1 {
1389
1390 /// HT1
1391 pub mod HT1 {
1392 /// Offset (16 bits)
1393 pub const offset: u32 = 16;
1394 /// Mask (12 bits: 0xfff << 16)
1395 pub const mask: u32 = 0xfff << offset;
1396 /// Read-only values (empty)
1397 pub mod R {}
1398 /// Write-only values (empty)
1399 pub mod W {}
1400 /// Read-write values (empty)
1401 pub mod RW {}
1402 }
1403
1404 /// LT1
1405 pub mod LT1 {
1406 /// Offset (0 bits)
1407 pub const offset: u32 = 0;
1408 /// Mask (12 bits: 0xfff << 0)
1409 pub const mask: u32 = 0xfff << offset;
1410 /// Read-only values (empty)
1411 pub mod R {}
1412 /// Write-only values (empty)
1413 pub mod W {}
1414 /// Read-write values (empty)
1415 pub mod RW {}
1416 }
1417}
1418
1419/// watchdog threshold register
1420pub mod TR2 {
1421
1422 /// HT2
1423 pub mod HT2 {
1424 /// Offset (16 bits)
1425 pub const offset: u32 = 16;
1426 /// Mask (8 bits: 0xff << 16)
1427 pub const mask: u32 = 0xff << offset;
1428 /// Read-only values (empty)
1429 pub mod R {}
1430 /// Write-only values (empty)
1431 pub mod W {}
1432 /// Read-write values (empty)
1433 pub mod RW {}
1434 }
1435
1436 /// LT2
1437 pub mod LT2 {
1438 /// Offset (0 bits)
1439 pub const offset: u32 = 0;
1440 /// Mask (8 bits: 0xff << 0)
1441 pub const mask: u32 = 0xff << offset;
1442 /// Read-only values (empty)
1443 pub mod R {}
1444 /// Write-only values (empty)
1445 pub mod W {}
1446 /// Read-write values (empty)
1447 pub mod RW {}
1448 }
1449}
1450
1451/// watchdog threshold register 3
1452pub mod TR3 {
1453
1454 /// HT3
1455 pub mod HT3 {
1456 /// Offset (16 bits)
1457 pub const offset: u32 = 16;
1458 /// Mask (8 bits: 0xff << 16)
1459 pub const mask: u32 = 0xff << offset;
1460 /// Read-only values (empty)
1461 pub mod R {}
1462 /// Write-only values (empty)
1463 pub mod W {}
1464 /// Read-write values (empty)
1465 pub mod RW {}
1466 }
1467
1468 /// LT3
1469 pub mod LT3 {
1470 /// Offset (0 bits)
1471 pub const offset: u32 = 0;
1472 /// Mask (8 bits: 0xff << 0)
1473 pub const mask: u32 = 0xff << offset;
1474 /// Read-only values (empty)
1475 pub mod R {}
1476 /// Write-only values (empty)
1477 pub mod W {}
1478 /// Read-write values (empty)
1479 pub mod RW {}
1480 }
1481}
1482
1483/// regular sequence register 1
1484pub mod SQR1 {
1485
1486 /// SQ4
1487 pub mod SQ4 {
1488 /// Offset (24 bits)
1489 pub const offset: u32 = 24;
1490 /// Mask (5 bits: 0b11111 << 24)
1491 pub const mask: u32 = 0b11111 << offset;
1492 /// Read-only values (empty)
1493 pub mod R {}
1494 /// Write-only values (empty)
1495 pub mod W {}
1496 /// Read-write values (empty)
1497 pub mod RW {}
1498 }
1499
1500 /// SQ3
1501 pub mod SQ3 {
1502 /// Offset (18 bits)
1503 pub const offset: u32 = 18;
1504 /// Mask (5 bits: 0b11111 << 18)
1505 pub const mask: u32 = 0b11111 << offset;
1506 /// Read-only values (empty)
1507 pub mod R {}
1508 /// Write-only values (empty)
1509 pub mod W {}
1510 /// Read-write values (empty)
1511 pub mod RW {}
1512 }
1513
1514 /// SQ2
1515 pub mod SQ2 {
1516 /// Offset (12 bits)
1517 pub const offset: u32 = 12;
1518 /// Mask (5 bits: 0b11111 << 12)
1519 pub const mask: u32 = 0b11111 << offset;
1520 /// Read-only values (empty)
1521 pub mod R {}
1522 /// Write-only values (empty)
1523 pub mod W {}
1524 /// Read-write values (empty)
1525 pub mod RW {}
1526 }
1527
1528 /// SQ1
1529 pub mod SQ1 {
1530 /// Offset (6 bits)
1531 pub const offset: u32 = 6;
1532 /// Mask (5 bits: 0b11111 << 6)
1533 pub const mask: u32 = 0b11111 << offset;
1534 /// Read-only values (empty)
1535 pub mod R {}
1536 /// Write-only values (empty)
1537 pub mod W {}
1538 /// Read-write values (empty)
1539 pub mod RW {}
1540 }
1541
1542 /// L3
1543 pub mod L {
1544 /// Offset (0 bits)
1545 pub const offset: u32 = 0;
1546 /// Mask (4 bits: 0b1111 << 0)
1547 pub const mask: u32 = 0b1111 << offset;
1548 /// Read-only values (empty)
1549 pub mod R {}
1550 /// Write-only values (empty)
1551 pub mod W {}
1552 /// Read-write values (empty)
1553 pub mod RW {}
1554 }
1555}
1556
1557/// regular sequence register 2
1558pub mod SQR2 {
1559
1560 /// SQ9
1561 pub mod SQ9 {
1562 /// Offset (24 bits)
1563 pub const offset: u32 = 24;
1564 /// Mask (5 bits: 0b11111 << 24)
1565 pub const mask: u32 = 0b11111 << offset;
1566 /// Read-only values (empty)
1567 pub mod R {}
1568 /// Write-only values (empty)
1569 pub mod W {}
1570 /// Read-write values (empty)
1571 pub mod RW {}
1572 }
1573
1574 /// SQ8
1575 pub mod SQ8 {
1576 /// Offset (18 bits)
1577 pub const offset: u32 = 18;
1578 /// Mask (5 bits: 0b11111 << 18)
1579 pub const mask: u32 = 0b11111 << offset;
1580 /// Read-only values (empty)
1581 pub mod R {}
1582 /// Write-only values (empty)
1583 pub mod W {}
1584 /// Read-write values (empty)
1585 pub mod RW {}
1586 }
1587
1588 /// SQ7
1589 pub mod SQ7 {
1590 /// Offset (12 bits)
1591 pub const offset: u32 = 12;
1592 /// Mask (5 bits: 0b11111 << 12)
1593 pub const mask: u32 = 0b11111 << offset;
1594 /// Read-only values (empty)
1595 pub mod R {}
1596 /// Write-only values (empty)
1597 pub mod W {}
1598 /// Read-write values (empty)
1599 pub mod RW {}
1600 }
1601
1602 /// SQ6
1603 pub mod SQ6 {
1604 /// Offset (6 bits)
1605 pub const offset: u32 = 6;
1606 /// Mask (5 bits: 0b11111 << 6)
1607 pub const mask: u32 = 0b11111 << offset;
1608 /// Read-only values (empty)
1609 pub mod R {}
1610 /// Write-only values (empty)
1611 pub mod W {}
1612 /// Read-write values (empty)
1613 pub mod RW {}
1614 }
1615
1616 /// SQ5
1617 pub mod SQ5 {
1618 /// Offset (0 bits)
1619 pub const offset: u32 = 0;
1620 /// Mask (5 bits: 0b11111 << 0)
1621 pub const mask: u32 = 0b11111 << offset;
1622 /// Read-only values (empty)
1623 pub mod R {}
1624 /// Write-only values (empty)
1625 pub mod W {}
1626 /// Read-write values (empty)
1627 pub mod RW {}
1628 }
1629}
1630
1631/// regular sequence register 3
1632pub mod SQR3 {
1633
1634 /// SQ14
1635 pub mod SQ14 {
1636 /// Offset (24 bits)
1637 pub const offset: u32 = 24;
1638 /// Mask (5 bits: 0b11111 << 24)
1639 pub const mask: u32 = 0b11111 << offset;
1640 /// Read-only values (empty)
1641 pub mod R {}
1642 /// Write-only values (empty)
1643 pub mod W {}
1644 /// Read-write values (empty)
1645 pub mod RW {}
1646 }
1647
1648 /// SQ13
1649 pub mod SQ13 {
1650 /// Offset (18 bits)
1651 pub const offset: u32 = 18;
1652 /// Mask (5 bits: 0b11111 << 18)
1653 pub const mask: u32 = 0b11111 << offset;
1654 /// Read-only values (empty)
1655 pub mod R {}
1656 /// Write-only values (empty)
1657 pub mod W {}
1658 /// Read-write values (empty)
1659 pub mod RW {}
1660 }
1661
1662 /// SQ12
1663 pub mod SQ12 {
1664 /// Offset (12 bits)
1665 pub const offset: u32 = 12;
1666 /// Mask (5 bits: 0b11111 << 12)
1667 pub const mask: u32 = 0b11111 << offset;
1668 /// Read-only values (empty)
1669 pub mod R {}
1670 /// Write-only values (empty)
1671 pub mod W {}
1672 /// Read-write values (empty)
1673 pub mod RW {}
1674 }
1675
1676 /// SQ11
1677 pub mod SQ11 {
1678 /// Offset (6 bits)
1679 pub const offset: u32 = 6;
1680 /// Mask (5 bits: 0b11111 << 6)
1681 pub const mask: u32 = 0b11111 << offset;
1682 /// Read-only values (empty)
1683 pub mod R {}
1684 /// Write-only values (empty)
1685 pub mod W {}
1686 /// Read-write values (empty)
1687 pub mod RW {}
1688 }
1689
1690 /// SQ10
1691 pub mod SQ10 {
1692 /// Offset (0 bits)
1693 pub const offset: u32 = 0;
1694 /// Mask (5 bits: 0b11111 << 0)
1695 pub const mask: u32 = 0b11111 << offset;
1696 /// Read-only values (empty)
1697 pub mod R {}
1698 /// Write-only values (empty)
1699 pub mod W {}
1700 /// Read-write values (empty)
1701 pub mod RW {}
1702 }
1703}
1704
1705/// regular sequence register 4
1706pub mod SQR4 {
1707
1708 /// SQ16
1709 pub mod SQ16 {
1710 /// Offset (6 bits)
1711 pub const offset: u32 = 6;
1712 /// Mask (5 bits: 0b11111 << 6)
1713 pub const mask: u32 = 0b11111 << offset;
1714 /// Read-only values (empty)
1715 pub mod R {}
1716 /// Write-only values (empty)
1717 pub mod W {}
1718 /// Read-write values (empty)
1719 pub mod RW {}
1720 }
1721
1722 /// SQ15
1723 pub mod SQ15 {
1724 /// Offset (0 bits)
1725 pub const offset: u32 = 0;
1726 /// Mask (5 bits: 0b11111 << 0)
1727 pub const mask: u32 = 0b11111 << offset;
1728 /// Read-only values (empty)
1729 pub mod R {}
1730 /// Write-only values (empty)
1731 pub mod W {}
1732 /// Read-write values (empty)
1733 pub mod RW {}
1734 }
1735}
1736
1737/// regular Data Register
1738pub mod DR {
1739
1740 /// Regular data
1741 pub mod RDATA {
1742 /// Offset (0 bits)
1743 pub const offset: u32 = 0;
1744 /// Mask (16 bits: 0xffff << 0)
1745 pub const mask: u32 = 0xffff << offset;
1746 /// Read-only values (empty)
1747 pub mod R {}
1748 /// Write-only values (empty)
1749 pub mod W {}
1750 /// Read-write values (empty)
1751 pub mod RW {}
1752 }
1753}
1754
1755/// injected sequence register
1756pub mod JSQR {
1757
1758 /// JSQ4
1759 pub mod JSQ4 {
1760 /// Offset (26 bits)
1761 pub const offset: u32 = 26;
1762 /// Mask (5 bits: 0b11111 << 26)
1763 pub const mask: u32 = 0b11111 << offset;
1764 /// Read-only values (empty)
1765 pub mod R {}
1766 /// Write-only values (empty)
1767 pub mod W {}
1768 /// Read-write values (empty)
1769 pub mod RW {}
1770 }
1771
1772 /// JSQ3
1773 pub mod JSQ3 {
1774 /// Offset (20 bits)
1775 pub const offset: u32 = 20;
1776 /// Mask (5 bits: 0b11111 << 20)
1777 pub const mask: u32 = 0b11111 << offset;
1778 /// Read-only values (empty)
1779 pub mod R {}
1780 /// Write-only values (empty)
1781 pub mod W {}
1782 /// Read-write values (empty)
1783 pub mod RW {}
1784 }
1785
1786 /// JSQ2
1787 pub mod JSQ2 {
1788 /// Offset (14 bits)
1789 pub const offset: u32 = 14;
1790 /// Mask (5 bits: 0b11111 << 14)
1791 pub const mask: u32 = 0b11111 << offset;
1792 /// Read-only values (empty)
1793 pub mod R {}
1794 /// Write-only values (empty)
1795 pub mod W {}
1796 /// Read-write values (empty)
1797 pub mod RW {}
1798 }
1799
1800 /// JSQ1
1801 pub mod JSQ1 {
1802 /// Offset (8 bits)
1803 pub const offset: u32 = 8;
1804 /// Mask (5 bits: 0b11111 << 8)
1805 pub const mask: u32 = 0b11111 << offset;
1806 /// Read-only values (empty)
1807 pub mod R {}
1808 /// Write-only values (empty)
1809 pub mod W {}
1810 /// Read-write values (empty)
1811 pub mod RW {}
1812 }
1813
1814 /// JEXTEN
1815 pub mod JEXTEN {
1816 /// Offset (6 bits)
1817 pub const offset: u32 = 6;
1818 /// Mask (2 bits: 0b11 << 6)
1819 pub const mask: u32 = 0b11 << offset;
1820 /// Read-only values (empty)
1821 pub mod R {}
1822 /// Write-only values (empty)
1823 pub mod W {}
1824 /// Read-write values
1825 pub mod RW {
1826
1827 /// 0b00: Trigger detection disabled
1828 pub const Disabled: u32 = 0b00;
1829
1830 /// 0b01: Trigger detection on the rising edge
1831 pub const RisingEdge: u32 = 0b01;
1832
1833 /// 0b10: Trigger detection on the falling edge
1834 pub const FallingEdge: u32 = 0b10;
1835
1836 /// 0b11: Trigger detection on both the rising and falling edges
1837 pub const BothEdges: u32 = 0b11;
1838 }
1839 }
1840
1841 /// JEXTSEL
1842 pub mod JEXTSEL {
1843 /// Offset (2 bits)
1844 pub const offset: u32 = 2;
1845 /// Mask (4 bits: 0b1111 << 2)
1846 pub const mask: u32 = 0b1111 << offset;
1847 /// Read-only values (empty)
1848 pub mod R {}
1849 /// Write-only values (empty)
1850 pub mod W {}
1851 /// Read-write values
1852 pub mod RW {
1853
1854 /// 0b0000: Timer 1 TRGO event
1855 pub const TIM1_TRGO: u32 = 0b0000;
1856
1857 /// 0b0001: Timer 1 CC4 event
1858 pub const TIM1_CC4: u32 = 0b0001;
1859
1860 /// 0b0010: Timer 2 TRGO event
1861 pub const TIM2_TRGO: u32 = 0b0010;
1862
1863 /// 0b0011: Timer 2 CC1 event
1864 pub const TIM2_CC1: u32 = 0b0011;
1865
1866 /// 0b0100: Timer 3 CC4 event
1867 pub const TIM3_CC4: u32 = 0b0100;
1868
1869 /// 0b0110: EXTI line 15
1870 pub const EXTI15: u32 = 0b0110;
1871
1872 /// 0b1000: Timer 1 TRGO2 event
1873 pub const TIM1_TRGO2: u32 = 0b1000;
1874
1875 /// 0b1001: HRTIM_ADCTRG2 event
1876 pub const HRTIM_ADCTRG2: u32 = 0b1001;
1877
1878 /// 0b1010: HRTIM_ADCTRG4 event
1879 pub const HRTIM_ADCTRG4: u32 = 0b1010;
1880
1881 /// 0b1011: Timer 3 CC3 event
1882 pub const TIM3_CC3: u32 = 0b1011;
1883
1884 /// 0b1100: Timer 3 TRGO event
1885 pub const TIM3_TRGO: u32 = 0b1100;
1886
1887 /// 0b1101: Timer 3 CC1 event
1888 pub const TIM3_CC1: u32 = 0b1101;
1889
1890 /// 0b1110: Timer 6 TRGO event
1891 pub const TIM6_TRGO: u32 = 0b1110;
1892
1893 /// 0b1111: Timer 15 TRGO event
1894 pub const TIM15_TRGO: u32 = 0b1111;
1895 }
1896 }
1897
1898 /// JL
1899 pub mod JL {
1900 /// Offset (0 bits)
1901 pub const offset: u32 = 0;
1902 /// Mask (2 bits: 0b11 << 0)
1903 pub const mask: u32 = 0b11 << offset;
1904 /// Read-only values (empty)
1905 pub mod R {}
1906 /// Write-only values (empty)
1907 pub mod W {}
1908 /// Read-write values (empty)
1909 pub mod RW {}
1910 }
1911}
1912
1913/// offset register 1
1914pub mod OFR1 {
1915
1916 /// OFFSET1_EN
1917 pub mod OFFSET1_EN {
1918 /// Offset (31 bits)
1919 pub const offset: u32 = 31;
1920 /// Mask (1 bit: 1 << 31)
1921 pub const mask: u32 = 1 << offset;
1922 /// Read-only values (empty)
1923 pub mod R {}
1924 /// Write-only values (empty)
1925 pub mod W {}
1926 /// Read-write values
1927 pub mod RW {
1928
1929 /// 0b0: Offset disabled
1930 pub const Disabled: u32 = 0b0;
1931
1932 /// 0b1: Offset enabled
1933 pub const Enabled: u32 = 0b1;
1934 }
1935 }
1936
1937 /// OFFSET1_CH
1938 pub mod OFFSET1_CH {
1939 /// Offset (26 bits)
1940 pub const offset: u32 = 26;
1941 /// Mask (5 bits: 0b11111 << 26)
1942 pub const mask: u32 = 0b11111 << offset;
1943 /// Read-only values (empty)
1944 pub mod R {}
1945 /// Write-only values (empty)
1946 pub mod W {}
1947 /// Read-write values (empty)
1948 pub mod RW {}
1949 }
1950
1951 /// OFFSET1
1952 pub mod OFFSET1 {
1953 /// Offset (0 bits)
1954 pub const offset: u32 = 0;
1955 /// Mask (12 bits: 0xfff << 0)
1956 pub const mask: u32 = 0xfff << offset;
1957 /// Read-only values (empty)
1958 pub mod R {}
1959 /// Write-only values (empty)
1960 pub mod W {}
1961 /// Read-write values (empty)
1962 pub mod RW {}
1963 }
1964}
1965
1966/// offset register 2
1967pub mod OFR2 {
1968
1969 /// OFFSET2_EN
1970 pub mod OFFSET2_EN {
1971 /// Offset (31 bits)
1972 pub const offset: u32 = 31;
1973 /// Mask (1 bit: 1 << 31)
1974 pub const mask: u32 = 1 << offset;
1975 /// Read-only values (empty)
1976 pub mod R {}
1977 /// Write-only values (empty)
1978 pub mod W {}
1979 /// Read-write values
1980 pub mod RW {
1981
1982 /// 0b0: Offset disabled
1983 pub const Disabled: u32 = 0b0;
1984
1985 /// 0b1: Offset enabled
1986 pub const Enabled: u32 = 0b1;
1987 }
1988 }
1989
1990 /// OFFSET2_CH
1991 pub mod OFFSET2_CH {
1992 /// Offset (26 bits)
1993 pub const offset: u32 = 26;
1994 /// Mask (5 bits: 0b11111 << 26)
1995 pub const mask: u32 = 0b11111 << offset;
1996 /// Read-only values (empty)
1997 pub mod R {}
1998 /// Write-only values (empty)
1999 pub mod W {}
2000 /// Read-write values (empty)
2001 pub mod RW {}
2002 }
2003
2004 /// OFFSET2
2005 pub mod OFFSET2 {
2006 /// Offset (0 bits)
2007 pub const offset: u32 = 0;
2008 /// Mask (12 bits: 0xfff << 0)
2009 pub const mask: u32 = 0xfff << offset;
2010 /// Read-only values (empty)
2011 pub mod R {}
2012 /// Write-only values (empty)
2013 pub mod W {}
2014 /// Read-write values (empty)
2015 pub mod RW {}
2016 }
2017}
2018
2019/// offset register 3
2020pub mod OFR3 {
2021
2022 /// OFFSET3_EN
2023 pub mod OFFSET3_EN {
2024 /// Offset (31 bits)
2025 pub const offset: u32 = 31;
2026 /// Mask (1 bit: 1 << 31)
2027 pub const mask: u32 = 1 << offset;
2028 /// Read-only values (empty)
2029 pub mod R {}
2030 /// Write-only values (empty)
2031 pub mod W {}
2032 /// Read-write values
2033 pub mod RW {
2034
2035 /// 0b0: Offset disabled
2036 pub const Disabled: u32 = 0b0;
2037
2038 /// 0b1: Offset enabled
2039 pub const Enabled: u32 = 0b1;
2040 }
2041 }
2042
2043 /// OFFSET3_CH
2044 pub mod OFFSET3_CH {
2045 /// Offset (26 bits)
2046 pub const offset: u32 = 26;
2047 /// Mask (5 bits: 0b11111 << 26)
2048 pub const mask: u32 = 0b11111 << offset;
2049 /// Read-only values (empty)
2050 pub mod R {}
2051 /// Write-only values (empty)
2052 pub mod W {}
2053 /// Read-write values (empty)
2054 pub mod RW {}
2055 }
2056
2057 /// OFFSET3
2058 pub mod OFFSET3 {
2059 /// Offset (0 bits)
2060 pub const offset: u32 = 0;
2061 /// Mask (12 bits: 0xfff << 0)
2062 pub const mask: u32 = 0xfff << offset;
2063 /// Read-only values (empty)
2064 pub mod R {}
2065 /// Write-only values (empty)
2066 pub mod W {}
2067 /// Read-write values (empty)
2068 pub mod RW {}
2069 }
2070}
2071
2072/// offset register 4
2073pub mod OFR4 {
2074
2075 /// OFFSET4_EN
2076 pub mod OFFSET4_EN {
2077 /// Offset (31 bits)
2078 pub const offset: u32 = 31;
2079 /// Mask (1 bit: 1 << 31)
2080 pub const mask: u32 = 1 << offset;
2081 /// Read-only values (empty)
2082 pub mod R {}
2083 /// Write-only values (empty)
2084 pub mod W {}
2085 /// Read-write values
2086 pub mod RW {
2087
2088 /// 0b0: Offset disabled
2089 pub const Disabled: u32 = 0b0;
2090
2091 /// 0b1: Offset enabled
2092 pub const Enabled: u32 = 0b1;
2093 }
2094 }
2095
2096 /// OFFSET4_CH
2097 pub mod OFFSET4_CH {
2098 /// Offset (26 bits)
2099 pub const offset: u32 = 26;
2100 /// Mask (5 bits: 0b11111 << 26)
2101 pub const mask: u32 = 0b11111 << offset;
2102 /// Read-only values (empty)
2103 pub mod R {}
2104 /// Write-only values (empty)
2105 pub mod W {}
2106 /// Read-write values (empty)
2107 pub mod RW {}
2108 }
2109
2110 /// OFFSET4
2111 pub mod OFFSET4 {
2112 /// Offset (0 bits)
2113 pub const offset: u32 = 0;
2114 /// Mask (12 bits: 0xfff << 0)
2115 pub const mask: u32 = 0xfff << offset;
2116 /// Read-only values (empty)
2117 pub mod R {}
2118 /// Write-only values (empty)
2119 pub mod W {}
2120 /// Read-write values (empty)
2121 pub mod RW {}
2122 }
2123}
2124
2125/// injected data register 1
2126pub mod JDR1 {
2127
2128 /// JDATA1
2129 pub mod JDATA1 {
2130 /// Offset (0 bits)
2131 pub const offset: u32 = 0;
2132 /// Mask (16 bits: 0xffff << 0)
2133 pub const mask: u32 = 0xffff << offset;
2134 /// Read-only values (empty)
2135 pub mod R {}
2136 /// Write-only values (empty)
2137 pub mod W {}
2138 /// Read-write values (empty)
2139 pub mod RW {}
2140 }
2141}
2142
2143/// injected data register 2
2144pub mod JDR2 {
2145
2146 /// JDATA2
2147 pub mod JDATA2 {
2148 /// Offset (0 bits)
2149 pub const offset: u32 = 0;
2150 /// Mask (16 bits: 0xffff << 0)
2151 pub const mask: u32 = 0xffff << offset;
2152 /// Read-only values (empty)
2153 pub mod R {}
2154 /// Write-only values (empty)
2155 pub mod W {}
2156 /// Read-write values (empty)
2157 pub mod RW {}
2158 }
2159}
2160
2161/// injected data register 3
2162pub mod JDR3 {
2163
2164 /// JDATA3
2165 pub mod JDATA3 {
2166 /// Offset (0 bits)
2167 pub const offset: u32 = 0;
2168 /// Mask (16 bits: 0xffff << 0)
2169 pub const mask: u32 = 0xffff << offset;
2170 /// Read-only values (empty)
2171 pub mod R {}
2172 /// Write-only values (empty)
2173 pub mod W {}
2174 /// Read-write values (empty)
2175 pub mod RW {}
2176 }
2177}
2178
2179/// injected data register 4
2180pub mod JDR4 {
2181
2182 /// JDATA4
2183 pub mod JDATA4 {
2184 /// Offset (0 bits)
2185 pub const offset: u32 = 0;
2186 /// Mask (16 bits: 0xffff << 0)
2187 pub const mask: u32 = 0xffff << offset;
2188 /// Read-only values (empty)
2189 pub mod R {}
2190 /// Write-only values (empty)
2191 pub mod W {}
2192 /// Read-write values (empty)
2193 pub mod RW {}
2194 }
2195}
2196
2197/// Analog Watchdog 2 Configuration Register
2198pub mod AWD2CR {
2199
2200 /// AWD2CH
2201 pub mod AWD2CH0 {
2202 /// Offset (1 bits)
2203 pub const offset: u32 = 1;
2204 /// Mask (1 bit: 1 << 1)
2205 pub const mask: u32 = 1 << offset;
2206 /// Read-only values (empty)
2207 pub mod R {}
2208 /// Write-only values (empty)
2209 pub mod W {}
2210 /// Read-write values
2211 pub mod RW {
2212
2213 /// 0b0: Input channel not monitored by AWDx
2214 pub const NotMonitored: u32 = 0b0;
2215
2216 /// 0b1: Input channel monitored by AWDx
2217 pub const Monitored: u32 = 0b1;
2218 }
2219 }
2220
2221 /// AWD2CH
2222 pub mod AWD2CH1 {
2223 /// Offset (2 bits)
2224 pub const offset: u32 = 2;
2225 /// Mask (1 bit: 1 << 2)
2226 pub const mask: u32 = 1 << offset;
2227 /// Read-only values (empty)
2228 pub mod R {}
2229 /// Write-only values (empty)
2230 pub mod W {}
2231 pub use super::AWD2CH0::RW;
2232 }
2233
2234 /// AWD2CH
2235 pub mod AWD2CH2 {
2236 /// Offset (3 bits)
2237 pub const offset: u32 = 3;
2238 /// Mask (1 bit: 1 << 3)
2239 pub const mask: u32 = 1 << offset;
2240 /// Read-only values (empty)
2241 pub mod R {}
2242 /// Write-only values (empty)
2243 pub mod W {}
2244 pub use super::AWD2CH0::RW;
2245 }
2246
2247 /// AWD2CH
2248 pub mod AWD2CH3 {
2249 /// Offset (4 bits)
2250 pub const offset: u32 = 4;
2251 /// Mask (1 bit: 1 << 4)
2252 pub const mask: u32 = 1 << offset;
2253 /// Read-only values (empty)
2254 pub mod R {}
2255 /// Write-only values (empty)
2256 pub mod W {}
2257 pub use super::AWD2CH0::RW;
2258 }
2259
2260 /// AWD2CH
2261 pub mod AWD2CH4 {
2262 /// Offset (5 bits)
2263 pub const offset: u32 = 5;
2264 /// Mask (1 bit: 1 << 5)
2265 pub const mask: u32 = 1 << offset;
2266 /// Read-only values (empty)
2267 pub mod R {}
2268 /// Write-only values (empty)
2269 pub mod W {}
2270 pub use super::AWD2CH0::RW;
2271 }
2272
2273 /// AWD2CH
2274 pub mod AWD2CH5 {
2275 /// Offset (6 bits)
2276 pub const offset: u32 = 6;
2277 /// Mask (1 bit: 1 << 6)
2278 pub const mask: u32 = 1 << offset;
2279 /// Read-only values (empty)
2280 pub mod R {}
2281 /// Write-only values (empty)
2282 pub mod W {}
2283 pub use super::AWD2CH0::RW;
2284 }
2285
2286 /// AWD2CH
2287 pub mod AWD2CH6 {
2288 /// Offset (7 bits)
2289 pub const offset: u32 = 7;
2290 /// Mask (1 bit: 1 << 7)
2291 pub const mask: u32 = 1 << offset;
2292 /// Read-only values (empty)
2293 pub mod R {}
2294 /// Write-only values (empty)
2295 pub mod W {}
2296 pub use super::AWD2CH0::RW;
2297 }
2298
2299 /// AWD2CH
2300 pub mod AWD2CH7 {
2301 /// Offset (8 bits)
2302 pub const offset: u32 = 8;
2303 /// Mask (1 bit: 1 << 8)
2304 pub const mask: u32 = 1 << offset;
2305 /// Read-only values (empty)
2306 pub mod R {}
2307 /// Write-only values (empty)
2308 pub mod W {}
2309 pub use super::AWD2CH0::RW;
2310 }
2311
2312 /// AWD2CH
2313 pub mod AWD2CH8 {
2314 /// Offset (9 bits)
2315 pub const offset: u32 = 9;
2316 /// Mask (1 bit: 1 << 9)
2317 pub const mask: u32 = 1 << offset;
2318 /// Read-only values (empty)
2319 pub mod R {}
2320 /// Write-only values (empty)
2321 pub mod W {}
2322 pub use super::AWD2CH0::RW;
2323 }
2324
2325 /// AWD2CH
2326 pub mod AWD2CH9 {
2327 /// Offset (10 bits)
2328 pub const offset: u32 = 10;
2329 /// Mask (1 bit: 1 << 10)
2330 pub const mask: u32 = 1 << offset;
2331 /// Read-only values (empty)
2332 pub mod R {}
2333 /// Write-only values (empty)
2334 pub mod W {}
2335 pub use super::AWD2CH0::RW;
2336 }
2337
2338 /// AWD2CH
2339 pub mod AWD2CH10 {
2340 /// Offset (11 bits)
2341 pub const offset: u32 = 11;
2342 /// Mask (1 bit: 1 << 11)
2343 pub const mask: u32 = 1 << offset;
2344 /// Read-only values (empty)
2345 pub mod R {}
2346 /// Write-only values (empty)
2347 pub mod W {}
2348 pub use super::AWD2CH0::RW;
2349 }
2350
2351 /// AWD2CH
2352 pub mod AWD2CH11 {
2353 /// Offset (12 bits)
2354 pub const offset: u32 = 12;
2355 /// Mask (1 bit: 1 << 12)
2356 pub const mask: u32 = 1 << offset;
2357 /// Read-only values (empty)
2358 pub mod R {}
2359 /// Write-only values (empty)
2360 pub mod W {}
2361 pub use super::AWD2CH0::RW;
2362 }
2363
2364 /// AWD2CH
2365 pub mod AWD2CH12 {
2366 /// Offset (13 bits)
2367 pub const offset: u32 = 13;
2368 /// Mask (1 bit: 1 << 13)
2369 pub const mask: u32 = 1 << offset;
2370 /// Read-only values (empty)
2371 pub mod R {}
2372 /// Write-only values (empty)
2373 pub mod W {}
2374 pub use super::AWD2CH0::RW;
2375 }
2376
2377 /// AWD2CH
2378 pub mod AWD2CH13 {
2379 /// Offset (14 bits)
2380 pub const offset: u32 = 14;
2381 /// Mask (1 bit: 1 << 14)
2382 pub const mask: u32 = 1 << offset;
2383 /// Read-only values (empty)
2384 pub mod R {}
2385 /// Write-only values (empty)
2386 pub mod W {}
2387 pub use super::AWD2CH0::RW;
2388 }
2389
2390 /// AWD2CH
2391 pub mod AWD2CH14 {
2392 /// Offset (15 bits)
2393 pub const offset: u32 = 15;
2394 /// Mask (1 bit: 1 << 15)
2395 pub const mask: u32 = 1 << offset;
2396 /// Read-only values (empty)
2397 pub mod R {}
2398 /// Write-only values (empty)
2399 pub mod W {}
2400 pub use super::AWD2CH0::RW;
2401 }
2402
2403 /// AWD2CH
2404 pub mod AWD2CH15 {
2405 /// Offset (16 bits)
2406 pub const offset: u32 = 16;
2407 /// Mask (1 bit: 1 << 16)
2408 pub const mask: u32 = 1 << offset;
2409 /// Read-only values (empty)
2410 pub mod R {}
2411 /// Write-only values (empty)
2412 pub mod W {}
2413 pub use super::AWD2CH0::RW;
2414 }
2415
2416 /// AWD2CH
2417 pub mod AWD2CH16 {
2418 /// Offset (17 bits)
2419 pub const offset: u32 = 17;
2420 /// Mask (1 bit: 1 << 17)
2421 pub const mask: u32 = 1 << offset;
2422 /// Read-only values (empty)
2423 pub mod R {}
2424 /// Write-only values (empty)
2425 pub mod W {}
2426 pub use super::AWD2CH0::RW;
2427 }
2428
2429 /// AWD2CH
2430 pub mod AWD2CH17 {
2431 /// Offset (18 bits)
2432 pub const offset: u32 = 18;
2433 /// Mask (1 bit: 1 << 18)
2434 pub const mask: u32 = 1 << offset;
2435 /// Read-only values (empty)
2436 pub mod R {}
2437 /// Write-only values (empty)
2438 pub mod W {}
2439 pub use super::AWD2CH0::RW;
2440 }
2441}
2442
2443/// Analog Watchdog 3 Configuration Register
2444pub mod AWD3CR {
2445
2446 /// AWD3CH
2447 pub mod AWD3CH0 {
2448 /// Offset (1 bits)
2449 pub const offset: u32 = 1;
2450 /// Mask (1 bit: 1 << 1)
2451 pub const mask: u32 = 1 << offset;
2452 /// Read-only values (empty)
2453 pub mod R {}
2454 /// Write-only values (empty)
2455 pub mod W {}
2456 /// Read-write values
2457 pub mod RW {
2458
2459 /// 0b0: Input channel not monitored by AWDx
2460 pub const NotMonitored: u32 = 0b0;
2461
2462 /// 0b1: Input channel monitored by AWDx
2463 pub const Monitored: u32 = 0b1;
2464 }
2465 }
2466
2467 /// AWD3CH
2468 pub mod AWD3CH1 {
2469 /// Offset (2 bits)
2470 pub const offset: u32 = 2;
2471 /// Mask (1 bit: 1 << 2)
2472 pub const mask: u32 = 1 << offset;
2473 /// Read-only values (empty)
2474 pub mod R {}
2475 /// Write-only values (empty)
2476 pub mod W {}
2477 pub use super::AWD3CH0::RW;
2478 }
2479
2480 /// AWD3CH
2481 pub mod AWD3CH2 {
2482 /// Offset (3 bits)
2483 pub const offset: u32 = 3;
2484 /// Mask (1 bit: 1 << 3)
2485 pub const mask: u32 = 1 << offset;
2486 /// Read-only values (empty)
2487 pub mod R {}
2488 /// Write-only values (empty)
2489 pub mod W {}
2490 pub use super::AWD3CH0::RW;
2491 }
2492
2493 /// AWD3CH
2494 pub mod AWD3CH3 {
2495 /// Offset (4 bits)
2496 pub const offset: u32 = 4;
2497 /// Mask (1 bit: 1 << 4)
2498 pub const mask: u32 = 1 << offset;
2499 /// Read-only values (empty)
2500 pub mod R {}
2501 /// Write-only values (empty)
2502 pub mod W {}
2503 pub use super::AWD3CH0::RW;
2504 }
2505
2506 /// AWD3CH
2507 pub mod AWD3CH4 {
2508 /// Offset (5 bits)
2509 pub const offset: u32 = 5;
2510 /// Mask (1 bit: 1 << 5)
2511 pub const mask: u32 = 1 << offset;
2512 /// Read-only values (empty)
2513 pub mod R {}
2514 /// Write-only values (empty)
2515 pub mod W {}
2516 pub use super::AWD3CH0::RW;
2517 }
2518
2519 /// AWD3CH
2520 pub mod AWD3CH5 {
2521 /// Offset (6 bits)
2522 pub const offset: u32 = 6;
2523 /// Mask (1 bit: 1 << 6)
2524 pub const mask: u32 = 1 << offset;
2525 /// Read-only values (empty)
2526 pub mod R {}
2527 /// Write-only values (empty)
2528 pub mod W {}
2529 pub use super::AWD3CH0::RW;
2530 }
2531
2532 /// AWD3CH
2533 pub mod AWD3CH6 {
2534 /// Offset (7 bits)
2535 pub const offset: u32 = 7;
2536 /// Mask (1 bit: 1 << 7)
2537 pub const mask: u32 = 1 << offset;
2538 /// Read-only values (empty)
2539 pub mod R {}
2540 /// Write-only values (empty)
2541 pub mod W {}
2542 pub use super::AWD3CH0::RW;
2543 }
2544
2545 /// AWD3CH
2546 pub mod AWD3CH7 {
2547 /// Offset (8 bits)
2548 pub const offset: u32 = 8;
2549 /// Mask (1 bit: 1 << 8)
2550 pub const mask: u32 = 1 << offset;
2551 /// Read-only values (empty)
2552 pub mod R {}
2553 /// Write-only values (empty)
2554 pub mod W {}
2555 pub use super::AWD3CH0::RW;
2556 }
2557
2558 /// AWD3CH
2559 pub mod AWD3CH8 {
2560 /// Offset (9 bits)
2561 pub const offset: u32 = 9;
2562 /// Mask (1 bit: 1 << 9)
2563 pub const mask: u32 = 1 << offset;
2564 /// Read-only values (empty)
2565 pub mod R {}
2566 /// Write-only values (empty)
2567 pub mod W {}
2568 pub use super::AWD3CH0::RW;
2569 }
2570
2571 /// AWD3CH
2572 pub mod AWD3CH9 {
2573 /// Offset (10 bits)
2574 pub const offset: u32 = 10;
2575 /// Mask (1 bit: 1 << 10)
2576 pub const mask: u32 = 1 << offset;
2577 /// Read-only values (empty)
2578 pub mod R {}
2579 /// Write-only values (empty)
2580 pub mod W {}
2581 pub use super::AWD3CH0::RW;
2582 }
2583
2584 /// AWD3CH
2585 pub mod AWD3CH10 {
2586 /// Offset (11 bits)
2587 pub const offset: u32 = 11;
2588 /// Mask (1 bit: 1 << 11)
2589 pub const mask: u32 = 1 << offset;
2590 /// Read-only values (empty)
2591 pub mod R {}
2592 /// Write-only values (empty)
2593 pub mod W {}
2594 pub use super::AWD3CH0::RW;
2595 }
2596
2597 /// AWD3CH
2598 pub mod AWD3CH11 {
2599 /// Offset (12 bits)
2600 pub const offset: u32 = 12;
2601 /// Mask (1 bit: 1 << 12)
2602 pub const mask: u32 = 1 << offset;
2603 /// Read-only values (empty)
2604 pub mod R {}
2605 /// Write-only values (empty)
2606 pub mod W {}
2607 pub use super::AWD3CH0::RW;
2608 }
2609
2610 /// AWD3CH
2611 pub mod AWD3CH12 {
2612 /// Offset (13 bits)
2613 pub const offset: u32 = 13;
2614 /// Mask (1 bit: 1 << 13)
2615 pub const mask: u32 = 1 << offset;
2616 /// Read-only values (empty)
2617 pub mod R {}
2618 /// Write-only values (empty)
2619 pub mod W {}
2620 pub use super::AWD3CH0::RW;
2621 }
2622
2623 /// AWD3CH
2624 pub mod AWD3CH13 {
2625 /// Offset (14 bits)
2626 pub const offset: u32 = 14;
2627 /// Mask (1 bit: 1 << 14)
2628 pub const mask: u32 = 1 << offset;
2629 /// Read-only values (empty)
2630 pub mod R {}
2631 /// Write-only values (empty)
2632 pub mod W {}
2633 pub use super::AWD3CH0::RW;
2634 }
2635
2636 /// AWD3CH
2637 pub mod AWD3CH14 {
2638 /// Offset (15 bits)
2639 pub const offset: u32 = 15;
2640 /// Mask (1 bit: 1 << 15)
2641 pub const mask: u32 = 1 << offset;
2642 /// Read-only values (empty)
2643 pub mod R {}
2644 /// Write-only values (empty)
2645 pub mod W {}
2646 pub use super::AWD3CH0::RW;
2647 }
2648
2649 /// AWD3CH
2650 pub mod AWD3CH15 {
2651 /// Offset (16 bits)
2652 pub const offset: u32 = 16;
2653 /// Mask (1 bit: 1 << 16)
2654 pub const mask: u32 = 1 << offset;
2655 /// Read-only values (empty)
2656 pub mod R {}
2657 /// Write-only values (empty)
2658 pub mod W {}
2659 pub use super::AWD3CH0::RW;
2660 }
2661
2662 /// AWD3CH
2663 pub mod AWD3CH16 {
2664 /// Offset (17 bits)
2665 pub const offset: u32 = 17;
2666 /// Mask (1 bit: 1 << 17)
2667 pub const mask: u32 = 1 << offset;
2668 /// Read-only values (empty)
2669 pub mod R {}
2670 /// Write-only values (empty)
2671 pub mod W {}
2672 pub use super::AWD3CH0::RW;
2673 }
2674
2675 /// AWD3CH
2676 pub mod AWD3CH17 {
2677 /// Offset (18 bits)
2678 pub const offset: u32 = 18;
2679 /// Mask (1 bit: 1 << 18)
2680 pub const mask: u32 = 1 << offset;
2681 /// Read-only values (empty)
2682 pub mod R {}
2683 /// Write-only values (empty)
2684 pub mod W {}
2685 pub use super::AWD3CH0::RW;
2686 }
2687}
2688
2689/// Differential Mode Selection Register 2
2690pub mod DIFSEL {
2691
2692 /// Differential mode for channels 15 to 1
2693 pub mod DIFSEL_10 {
2694 /// Offset (1 bits)
2695 pub const offset: u32 = 1;
2696 /// Mask (1 bit: 1 << 1)
2697 pub const mask: u32 = 1 << offset;
2698 /// Read-only values (empty)
2699 pub mod R {}
2700 /// Write-only values (empty)
2701 pub mod W {}
2702 /// Read-write values
2703 pub mod RW {
2704
2705 /// 0b0: Input channel is configured in single-ended mode
2706 pub const SingleEnded: u32 = 0b0;
2707
2708 /// 0b1: Input channel is configured in differential mode
2709 pub const Differential: u32 = 0b1;
2710 }
2711 }
2712
2713 /// Differential mode for channels 15 to 1
2714 pub mod DIFSEL_11 {
2715 /// Offset (2 bits)
2716 pub const offset: u32 = 2;
2717 /// Mask (1 bit: 1 << 2)
2718 pub const mask: u32 = 1 << offset;
2719 /// Read-only values (empty)
2720 pub mod R {}
2721 /// Write-only values (empty)
2722 pub mod W {}
2723 pub use super::DIFSEL_10::RW;
2724 }
2725
2726 /// Differential mode for channels 15 to 1
2727 pub mod DIFSEL_12 {
2728 /// Offset (3 bits)
2729 pub const offset: u32 = 3;
2730 /// Mask (1 bit: 1 << 3)
2731 pub const mask: u32 = 1 << offset;
2732 /// Read-only values (empty)
2733 pub mod R {}
2734 /// Write-only values (empty)
2735 pub mod W {}
2736 pub use super::DIFSEL_10::RW;
2737 }
2738
2739 /// Differential mode for channels 15 to 1
2740 pub mod DIFSEL_13 {
2741 /// Offset (4 bits)
2742 pub const offset: u32 = 4;
2743 /// Mask (1 bit: 1 << 4)
2744 pub const mask: u32 = 1 << offset;
2745 /// Read-only values (empty)
2746 pub mod R {}
2747 /// Write-only values (empty)
2748 pub mod W {}
2749 pub use super::DIFSEL_10::RW;
2750 }
2751
2752 /// Differential mode for channels 15 to 1
2753 pub mod DIFSEL_14 {
2754 /// Offset (5 bits)
2755 pub const offset: u32 = 5;
2756 /// Mask (1 bit: 1 << 5)
2757 pub const mask: u32 = 1 << offset;
2758 /// Read-only values (empty)
2759 pub mod R {}
2760 /// Write-only values (empty)
2761 pub mod W {}
2762 pub use super::DIFSEL_10::RW;
2763 }
2764
2765 /// Differential mode for channels 15 to 1
2766 pub mod DIFSEL_15 {
2767 /// Offset (6 bits)
2768 pub const offset: u32 = 6;
2769 /// Mask (1 bit: 1 << 6)
2770 pub const mask: u32 = 1 << offset;
2771 /// Read-only values (empty)
2772 pub mod R {}
2773 /// Write-only values (empty)
2774 pub mod W {}
2775 pub use super::DIFSEL_10::RW;
2776 }
2777
2778 /// Differential mode for channels 15 to 1
2779 pub mod DIFSEL_16 {
2780 /// Offset (7 bits)
2781 pub const offset: u32 = 7;
2782 /// Mask (1 bit: 1 << 7)
2783 pub const mask: u32 = 1 << offset;
2784 /// Read-only values (empty)
2785 pub mod R {}
2786 /// Write-only values (empty)
2787 pub mod W {}
2788 pub use super::DIFSEL_10::RW;
2789 }
2790
2791 /// Differential mode for channels 15 to 1
2792 pub mod DIFSEL_17 {
2793 /// Offset (8 bits)
2794 pub const offset: u32 = 8;
2795 /// Mask (1 bit: 1 << 8)
2796 pub const mask: u32 = 1 << offset;
2797 /// Read-only values (empty)
2798 pub mod R {}
2799 /// Write-only values (empty)
2800 pub mod W {}
2801 pub use super::DIFSEL_10::RW;
2802 }
2803
2804 /// Differential mode for channels 15 to 1
2805 pub mod DIFSEL_18 {
2806 /// Offset (9 bits)
2807 pub const offset: u32 = 9;
2808 /// Mask (1 bit: 1 << 9)
2809 pub const mask: u32 = 1 << offset;
2810 /// Read-only values (empty)
2811 pub mod R {}
2812 /// Write-only values (empty)
2813 pub mod W {}
2814 pub use super::DIFSEL_10::RW;
2815 }
2816
2817 /// Differential mode for channels 15 to 1
2818 pub mod DIFSEL_19 {
2819 /// Offset (10 bits)
2820 pub const offset: u32 = 10;
2821 /// Mask (1 bit: 1 << 10)
2822 pub const mask: u32 = 1 << offset;
2823 /// Read-only values (empty)
2824 pub mod R {}
2825 /// Write-only values (empty)
2826 pub mod W {}
2827 pub use super::DIFSEL_10::RW;
2828 }
2829
2830 /// Differential mode for channels 15 to 1
2831 pub mod DIFSEL_110 {
2832 /// Offset (11 bits)
2833 pub const offset: u32 = 11;
2834 /// Mask (1 bit: 1 << 11)
2835 pub const mask: u32 = 1 << offset;
2836 /// Read-only values (empty)
2837 pub mod R {}
2838 /// Write-only values (empty)
2839 pub mod W {}
2840 pub use super::DIFSEL_10::RW;
2841 }
2842
2843 /// Differential mode for channels 15 to 1
2844 pub mod DIFSEL_111 {
2845 /// Offset (12 bits)
2846 pub const offset: u32 = 12;
2847 /// Mask (1 bit: 1 << 12)
2848 pub const mask: u32 = 1 << offset;
2849 /// Read-only values (empty)
2850 pub mod R {}
2851 /// Write-only values (empty)
2852 pub mod W {}
2853 pub use super::DIFSEL_10::RW;
2854 }
2855
2856 /// Differential mode for channels 15 to 1
2857 pub mod DIFSEL_112 {
2858 /// Offset (13 bits)
2859 pub const offset: u32 = 13;
2860 /// Mask (1 bit: 1 << 13)
2861 pub const mask: u32 = 1 << offset;
2862 /// Read-only values (empty)
2863 pub mod R {}
2864 /// Write-only values (empty)
2865 pub mod W {}
2866 pub use super::DIFSEL_10::RW;
2867 }
2868
2869 /// Differential mode for channels 15 to 1
2870 pub mod DIFSEL_113 {
2871 /// Offset (14 bits)
2872 pub const offset: u32 = 14;
2873 /// Mask (1 bit: 1 << 14)
2874 pub const mask: u32 = 1 << offset;
2875 /// Read-only values (empty)
2876 pub mod R {}
2877 /// Write-only values (empty)
2878 pub mod W {}
2879 pub use super::DIFSEL_10::RW;
2880 }
2881
2882 /// Differential mode for channels 15 to 1
2883 pub mod DIFSEL_114 {
2884 /// Offset (15 bits)
2885 pub const offset: u32 = 15;
2886 /// Mask (1 bit: 1 << 15)
2887 pub const mask: u32 = 1 << offset;
2888 /// Read-only values (empty)
2889 pub mod R {}
2890 /// Write-only values (empty)
2891 pub mod W {}
2892 pub use super::DIFSEL_10::RW;
2893 }
2894
2895 /// Differential mode for channels 15 to 1
2896 pub mod DIFSEL_115 {
2897 /// Offset (16 bits)
2898 pub const offset: u32 = 16;
2899 /// Mask (1 bit: 1 << 16)
2900 pub const mask: u32 = 1 << offset;
2901 /// Read-only values (empty)
2902 pub mod R {}
2903 /// Write-only values (empty)
2904 pub mod W {}
2905 pub use super::DIFSEL_10::RW;
2906 }
2907
2908 /// Differential mode for channels 15 to 1
2909 pub mod DIFSEL_116 {
2910 /// Offset (17 bits)
2911 pub const offset: u32 = 17;
2912 /// Mask (1 bit: 1 << 17)
2913 pub const mask: u32 = 1 << offset;
2914 /// Read-only values (empty)
2915 pub mod R {}
2916 /// Write-only values (empty)
2917 pub mod W {}
2918 pub use super::DIFSEL_10::RW;
2919 }
2920
2921 /// Differential mode for channels 15 to 1
2922 pub mod DIFSEL_117 {
2923 /// Offset (18 bits)
2924 pub const offset: u32 = 18;
2925 /// Mask (1 bit: 1 << 18)
2926 pub const mask: u32 = 1 << offset;
2927 /// Read-only values (empty)
2928 pub mod R {}
2929 /// Write-only values (empty)
2930 pub mod W {}
2931 pub use super::DIFSEL_10::RW;
2932 }
2933}
2934
2935/// Calibration Factors
2936pub mod CALFACT {
2937
2938 /// CALFACT_D
2939 pub mod CALFACT_D {
2940 /// Offset (16 bits)
2941 pub const offset: u32 = 16;
2942 /// Mask (7 bits: 0x7f << 16)
2943 pub const mask: u32 = 0x7f << offset;
2944 /// Read-only values (empty)
2945 pub mod R {}
2946 /// Write-only values (empty)
2947 pub mod W {}
2948 /// Read-write values (empty)
2949 pub mod RW {}
2950 }
2951
2952 /// CALFACT_S
2953 pub mod CALFACT_S {
2954 /// Offset (0 bits)
2955 pub const offset: u32 = 0;
2956 /// Mask (7 bits: 0x7f << 0)
2957 pub const mask: u32 = 0x7f << offset;
2958 /// Read-only values (empty)
2959 pub mod R {}
2960 /// Write-only values (empty)
2961 pub mod W {}
2962 /// Read-write values (empty)
2963 pub mod RW {}
2964 }
2965}
2966#[repr(C)]
2967pub struct RegisterBlock {
2968 /// interrupt and status register
2969 pub ISR: RWRegister<u32>,
2970
2971 /// interrupt enable register
2972 pub IER: RWRegister<u32>,
2973
2974 /// control register
2975 pub CR: RWRegister<u32>,
2976
2977 /// configuration register
2978 pub CFGR: RWRegister<u32>,
2979
2980 _reserved1: [u8; 4],
2981
2982 /// sample time register 1
2983 pub SMPR1: RWRegister<u32>,
2984
2985 /// sample time register 2
2986 pub SMPR2: RWRegister<u32>,
2987
2988 _reserved2: [u8; 4],
2989
2990 /// watchdog threshold register 1
2991 pub TR1: RWRegister<u32>,
2992
2993 /// watchdog threshold register
2994 pub TR2: RWRegister<u32>,
2995
2996 /// watchdog threshold register 3
2997 pub TR3: RWRegister<u32>,
2998
2999 _reserved3: [u8; 4],
3000
3001 /// regular sequence register 1
3002 pub SQR1: RWRegister<u32>,
3003
3004 /// regular sequence register 2
3005 pub SQR2: RWRegister<u32>,
3006
3007 /// regular sequence register 3
3008 pub SQR3: RWRegister<u32>,
3009
3010 /// regular sequence register 4
3011 pub SQR4: RWRegister<u32>,
3012
3013 /// regular Data Register
3014 pub DR: RORegister<u32>,
3015
3016 _reserved4: [u8; 8],
3017
3018 /// injected sequence register
3019 pub JSQR: RWRegister<u32>,
3020
3021 _reserved5: [u8; 16],
3022
3023 /// offset register 1
3024 pub OFR1: RWRegister<u32>,
3025
3026 /// offset register 2
3027 pub OFR2: RWRegister<u32>,
3028
3029 /// offset register 3
3030 pub OFR3: RWRegister<u32>,
3031
3032 /// offset register 4
3033 pub OFR4: RWRegister<u32>,
3034
3035 _reserved6: [u8; 16],
3036
3037 /// injected data register 1
3038 pub JDR1: RORegister<u32>,
3039
3040 /// injected data register 2
3041 pub JDR2: RORegister<u32>,
3042
3043 /// injected data register 3
3044 pub JDR3: RORegister<u32>,
3045
3046 /// injected data register 4
3047 pub JDR4: RORegister<u32>,
3048
3049 _reserved7: [u8; 16],
3050
3051 /// Analog Watchdog 2 Configuration Register
3052 pub AWD2CR: RWRegister<u32>,
3053
3054 /// Analog Watchdog 3 Configuration Register
3055 pub AWD3CR: RWRegister<u32>,
3056
3057 _reserved8: [u8; 8],
3058
3059 /// Differential Mode Selection Register 2
3060 pub DIFSEL: RWRegister<u32>,
3061
3062 /// Calibration Factors
3063 pub CALFACT: RWRegister<u32>,
3064}
3065pub struct ResetValues {
3066 pub ISR: u32,
3067 pub IER: u32,
3068 pub CR: u32,
3069 pub CFGR: u32,
3070 pub SMPR1: u32,
3071 pub SMPR2: u32,
3072 pub TR1: u32,
3073 pub TR2: u32,
3074 pub TR3: u32,
3075 pub SQR1: u32,
3076 pub SQR2: u32,
3077 pub SQR3: u32,
3078 pub SQR4: u32,
3079 pub DR: u32,
3080 pub JSQR: u32,
3081 pub OFR1: u32,
3082 pub OFR2: u32,
3083 pub OFR3: u32,
3084 pub OFR4: u32,
3085 pub JDR1: u32,
3086 pub JDR2: u32,
3087 pub JDR3: u32,
3088 pub JDR4: u32,
3089 pub AWD2CR: u32,
3090 pub AWD3CR: u32,
3091 pub DIFSEL: u32,
3092 pub CALFACT: u32,
3093}
3094#[cfg(not(feature = "nosync"))]
3095pub struct Instance {
3096 pub(crate) addr: u32,
3097 pub(crate) _marker: PhantomData<*const RegisterBlock>,
3098}
3099#[cfg(not(feature = "nosync"))]
3100impl ::core::ops::Deref for Instance {
3101 type Target = RegisterBlock;
3102 #[inline(always)]
3103 fn deref(&self) -> &RegisterBlock {
3104 unsafe { &*(self.addr as *const _) }
3105 }
3106}
3107#[cfg(feature = "rtic")]
3108unsafe impl Send for Instance {}