stm32ral/stm32f2/peripherals/dcmi.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Digital camera interface
4//!
5//! Used by: stm32f215, stm32f217
6
7use crate::{RORegister, RWRegister, WORegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// control register 1
12pub mod CR {
13
14 /// DCMI enable
15 pub mod ENABLE {
16 /// Offset (14 bits)
17 pub const offset: u32 = 14;
18 /// Mask (1 bit: 1 << 14)
19 pub const mask: u32 = 1 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values (empty)
25 pub mod RW {}
26 }
27
28 /// Extended data mode
29 pub mod EDM {
30 /// Offset (10 bits)
31 pub const offset: u32 = 10;
32 /// Mask (2 bits: 0b11 << 10)
33 pub const mask: u32 = 0b11 << offset;
34 /// Read-only values (empty)
35 pub mod R {}
36 /// Write-only values (empty)
37 pub mod W {}
38 /// Read-write values (empty)
39 pub mod RW {}
40 }
41
42 /// Frame capture rate control
43 pub mod FCRC {
44 /// Offset (8 bits)
45 pub const offset: u32 = 8;
46 /// Mask (2 bits: 0b11 << 8)
47 pub const mask: u32 = 0b11 << offset;
48 /// Read-only values (empty)
49 pub mod R {}
50 /// Write-only values (empty)
51 pub mod W {}
52 /// Read-write values (empty)
53 pub mod RW {}
54 }
55
56 /// Vertical synchronization polarity
57 pub mod VSPOL {
58 /// Offset (7 bits)
59 pub const offset: u32 = 7;
60 /// Mask (1 bit: 1 << 7)
61 pub const mask: u32 = 1 << offset;
62 /// Read-only values (empty)
63 pub mod R {}
64 /// Write-only values (empty)
65 pub mod W {}
66 /// Read-write values (empty)
67 pub mod RW {}
68 }
69
70 /// Horizontal synchronization polarity
71 pub mod HSPOL {
72 /// Offset (6 bits)
73 pub const offset: u32 = 6;
74 /// Mask (1 bit: 1 << 6)
75 pub const mask: u32 = 1 << offset;
76 /// Read-only values (empty)
77 pub mod R {}
78 /// Write-only values (empty)
79 pub mod W {}
80 /// Read-write values (empty)
81 pub mod RW {}
82 }
83
84 /// Pixel clock polarity
85 pub mod PCKPOL {
86 /// Offset (5 bits)
87 pub const offset: u32 = 5;
88 /// Mask (1 bit: 1 << 5)
89 pub const mask: u32 = 1 << offset;
90 /// Read-only values (empty)
91 pub mod R {}
92 /// Write-only values (empty)
93 pub mod W {}
94 /// Read-write values (empty)
95 pub mod RW {}
96 }
97
98 /// Embedded synchronization select
99 pub mod ESS {
100 /// Offset (4 bits)
101 pub const offset: u32 = 4;
102 /// Mask (1 bit: 1 << 4)
103 pub const mask: u32 = 1 << offset;
104 /// Read-only values (empty)
105 pub mod R {}
106 /// Write-only values (empty)
107 pub mod W {}
108 /// Read-write values (empty)
109 pub mod RW {}
110 }
111
112 /// JPEG format
113 pub mod JPEG {
114 /// Offset (3 bits)
115 pub const offset: u32 = 3;
116 /// Mask (1 bit: 1 << 3)
117 pub const mask: u32 = 1 << offset;
118 /// Read-only values (empty)
119 pub mod R {}
120 /// Write-only values (empty)
121 pub mod W {}
122 /// Read-write values (empty)
123 pub mod RW {}
124 }
125
126 /// Crop feature
127 pub mod CROP {
128 /// Offset (2 bits)
129 pub const offset: u32 = 2;
130 /// Mask (1 bit: 1 << 2)
131 pub const mask: u32 = 1 << offset;
132 /// Read-only values (empty)
133 pub mod R {}
134 /// Write-only values (empty)
135 pub mod W {}
136 /// Read-write values (empty)
137 pub mod RW {}
138 }
139
140 /// Capture mode
141 pub mod CM {
142 /// Offset (1 bits)
143 pub const offset: u32 = 1;
144 /// Mask (1 bit: 1 << 1)
145 pub const mask: u32 = 1 << offset;
146 /// Read-only values (empty)
147 pub mod R {}
148 /// Write-only values (empty)
149 pub mod W {}
150 /// Read-write values (empty)
151 pub mod RW {}
152 }
153
154 /// Capture enable
155 pub mod CAPTURE {
156 /// Offset (0 bits)
157 pub const offset: u32 = 0;
158 /// Mask (1 bit: 1 << 0)
159 pub const mask: u32 = 1 << offset;
160 /// Read-only values (empty)
161 pub mod R {}
162 /// Write-only values (empty)
163 pub mod W {}
164 /// Read-write values (empty)
165 pub mod RW {}
166 }
167}
168
169/// status register
170pub mod SR {
171
172 /// FIFO not empty
173 pub mod FNE {
174 /// Offset (2 bits)
175 pub const offset: u32 = 2;
176 /// Mask (1 bit: 1 << 2)
177 pub const mask: u32 = 1 << offset;
178 /// Read-only values (empty)
179 pub mod R {}
180 /// Write-only values (empty)
181 pub mod W {}
182 /// Read-write values (empty)
183 pub mod RW {}
184 }
185
186 /// VSYNC
187 pub mod VSYNC {
188 /// Offset (1 bits)
189 pub const offset: u32 = 1;
190 /// Mask (1 bit: 1 << 1)
191 pub const mask: u32 = 1 << offset;
192 /// Read-only values (empty)
193 pub mod R {}
194 /// Write-only values (empty)
195 pub mod W {}
196 /// Read-write values (empty)
197 pub mod RW {}
198 }
199
200 /// HSYNC
201 pub mod HSYNC {
202 /// Offset (0 bits)
203 pub const offset: u32 = 0;
204 /// Mask (1 bit: 1 << 0)
205 pub const mask: u32 = 1 << offset;
206 /// Read-only values (empty)
207 pub mod R {}
208 /// Write-only values (empty)
209 pub mod W {}
210 /// Read-write values (empty)
211 pub mod RW {}
212 }
213}
214
215/// raw interrupt status register
216pub mod RIS {
217
218 /// Line raw interrupt status
219 pub mod LINE_RIS {
220 /// Offset (4 bits)
221 pub const offset: u32 = 4;
222 /// Mask (1 bit: 1 << 4)
223 pub const mask: u32 = 1 << offset;
224 /// Read-only values (empty)
225 pub mod R {}
226 /// Write-only values (empty)
227 pub mod W {}
228 /// Read-write values (empty)
229 pub mod RW {}
230 }
231
232 /// VSYNC raw interrupt status
233 pub mod VSYNC_RIS {
234 /// Offset (3 bits)
235 pub const offset: u32 = 3;
236 /// Mask (1 bit: 1 << 3)
237 pub const mask: u32 = 1 << offset;
238 /// Read-only values (empty)
239 pub mod R {}
240 /// Write-only values (empty)
241 pub mod W {}
242 /// Read-write values (empty)
243 pub mod RW {}
244 }
245
246 /// Synchronization error raw interrupt status
247 pub mod ERR_RIS {
248 /// Offset (2 bits)
249 pub const offset: u32 = 2;
250 /// Mask (1 bit: 1 << 2)
251 pub const mask: u32 = 1 << offset;
252 /// Read-only values (empty)
253 pub mod R {}
254 /// Write-only values (empty)
255 pub mod W {}
256 /// Read-write values (empty)
257 pub mod RW {}
258 }
259
260 /// Overrun raw interrupt status
261 pub mod OVR_RIS {
262 /// Offset (1 bits)
263 pub const offset: u32 = 1;
264 /// Mask (1 bit: 1 << 1)
265 pub const mask: u32 = 1 << offset;
266 /// Read-only values (empty)
267 pub mod R {}
268 /// Write-only values (empty)
269 pub mod W {}
270 /// Read-write values (empty)
271 pub mod RW {}
272 }
273
274 /// Capture complete raw interrupt status
275 pub mod FRAME_RIS {
276 /// Offset (0 bits)
277 pub const offset: u32 = 0;
278 /// Mask (1 bit: 1 << 0)
279 pub const mask: u32 = 1 << offset;
280 /// Read-only values (empty)
281 pub mod R {}
282 /// Write-only values (empty)
283 pub mod W {}
284 /// Read-write values (empty)
285 pub mod RW {}
286 }
287}
288
289/// interrupt enable register
290pub mod IER {
291
292 /// Line interrupt enable
293 pub mod LINE_IE {
294 /// Offset (4 bits)
295 pub const offset: u32 = 4;
296 /// Mask (1 bit: 1 << 4)
297 pub const mask: u32 = 1 << offset;
298 /// Read-only values (empty)
299 pub mod R {}
300 /// Write-only values (empty)
301 pub mod W {}
302 /// Read-write values (empty)
303 pub mod RW {}
304 }
305
306 /// VSYNC interrupt enable
307 pub mod VSYNC_IE {
308 /// Offset (3 bits)
309 pub const offset: u32 = 3;
310 /// Mask (1 bit: 1 << 3)
311 pub const mask: u32 = 1 << offset;
312 /// Read-only values (empty)
313 pub mod R {}
314 /// Write-only values (empty)
315 pub mod W {}
316 /// Read-write values (empty)
317 pub mod RW {}
318 }
319
320 /// Synchronization error interrupt enable
321 pub mod ERR_IE {
322 /// Offset (2 bits)
323 pub const offset: u32 = 2;
324 /// Mask (1 bit: 1 << 2)
325 pub const mask: u32 = 1 << offset;
326 /// Read-only values (empty)
327 pub mod R {}
328 /// Write-only values (empty)
329 pub mod W {}
330 /// Read-write values (empty)
331 pub mod RW {}
332 }
333
334 /// Overrun interrupt enable
335 pub mod OVR_IE {
336 /// Offset (1 bits)
337 pub const offset: u32 = 1;
338 /// Mask (1 bit: 1 << 1)
339 pub const mask: u32 = 1 << offset;
340 /// Read-only values (empty)
341 pub mod R {}
342 /// Write-only values (empty)
343 pub mod W {}
344 /// Read-write values (empty)
345 pub mod RW {}
346 }
347
348 /// Capture complete interrupt enable
349 pub mod FRAME_IE {
350 /// Offset (0 bits)
351 pub const offset: u32 = 0;
352 /// Mask (1 bit: 1 << 0)
353 pub const mask: u32 = 1 << offset;
354 /// Read-only values (empty)
355 pub mod R {}
356 /// Write-only values (empty)
357 pub mod W {}
358 /// Read-write values (empty)
359 pub mod RW {}
360 }
361}
362
363/// masked interrupt status register
364pub mod MIS {
365
366 /// Line masked interrupt status
367 pub mod LINE_MIS {
368 /// Offset (4 bits)
369 pub const offset: u32 = 4;
370 /// Mask (1 bit: 1 << 4)
371 pub const mask: u32 = 1 << offset;
372 /// Read-only values (empty)
373 pub mod R {}
374 /// Write-only values (empty)
375 pub mod W {}
376 /// Read-write values (empty)
377 pub mod RW {}
378 }
379
380 /// VSYNC masked interrupt status
381 pub mod VSYNC_MIS {
382 /// Offset (3 bits)
383 pub const offset: u32 = 3;
384 /// Mask (1 bit: 1 << 3)
385 pub const mask: u32 = 1 << offset;
386 /// Read-only values (empty)
387 pub mod R {}
388 /// Write-only values (empty)
389 pub mod W {}
390 /// Read-write values (empty)
391 pub mod RW {}
392 }
393
394 /// Synchronization error masked interrupt status
395 pub mod ERR_MIS {
396 /// Offset (2 bits)
397 pub const offset: u32 = 2;
398 /// Mask (1 bit: 1 << 2)
399 pub const mask: u32 = 1 << offset;
400 /// Read-only values (empty)
401 pub mod R {}
402 /// Write-only values (empty)
403 pub mod W {}
404 /// Read-write values (empty)
405 pub mod RW {}
406 }
407
408 /// Overrun masked interrupt status
409 pub mod OVR_MIS {
410 /// Offset (1 bits)
411 pub const offset: u32 = 1;
412 /// Mask (1 bit: 1 << 1)
413 pub const mask: u32 = 1 << offset;
414 /// Read-only values (empty)
415 pub mod R {}
416 /// Write-only values (empty)
417 pub mod W {}
418 /// Read-write values (empty)
419 pub mod RW {}
420 }
421
422 /// Capture complete masked interrupt status
423 pub mod FRAME_MIS {
424 /// Offset (0 bits)
425 pub const offset: u32 = 0;
426 /// Mask (1 bit: 1 << 0)
427 pub const mask: u32 = 1 << offset;
428 /// Read-only values (empty)
429 pub mod R {}
430 /// Write-only values (empty)
431 pub mod W {}
432 /// Read-write values (empty)
433 pub mod RW {}
434 }
435}
436
437/// interrupt clear register
438pub mod ICR {
439
440 /// line interrupt status clear
441 pub mod LINE_ISC {
442 /// Offset (4 bits)
443 pub const offset: u32 = 4;
444 /// Mask (1 bit: 1 << 4)
445 pub const mask: u32 = 1 << offset;
446 /// Read-only values (empty)
447 pub mod R {}
448 /// Write-only values (empty)
449 pub mod W {}
450 /// Read-write values (empty)
451 pub mod RW {}
452 }
453
454 /// Vertical synch interrupt status clear
455 pub mod VSYNC_ISC {
456 /// Offset (3 bits)
457 pub const offset: u32 = 3;
458 /// Mask (1 bit: 1 << 3)
459 pub const mask: u32 = 1 << offset;
460 /// Read-only values (empty)
461 pub mod R {}
462 /// Write-only values (empty)
463 pub mod W {}
464 /// Read-write values (empty)
465 pub mod RW {}
466 }
467
468 /// Synchronization error interrupt status clear
469 pub mod ERR_ISC {
470 /// Offset (2 bits)
471 pub const offset: u32 = 2;
472 /// Mask (1 bit: 1 << 2)
473 pub const mask: u32 = 1 << offset;
474 /// Read-only values (empty)
475 pub mod R {}
476 /// Write-only values (empty)
477 pub mod W {}
478 /// Read-write values (empty)
479 pub mod RW {}
480 }
481
482 /// Overrun interrupt status clear
483 pub mod OVR_ISC {
484 /// Offset (1 bits)
485 pub const offset: u32 = 1;
486 /// Mask (1 bit: 1 << 1)
487 pub const mask: u32 = 1 << offset;
488 /// Read-only values (empty)
489 pub mod R {}
490 /// Write-only values (empty)
491 pub mod W {}
492 /// Read-write values (empty)
493 pub mod RW {}
494 }
495
496 /// Capture complete interrupt status clear
497 pub mod FRAME_ISC {
498 /// Offset (0 bits)
499 pub const offset: u32 = 0;
500 /// Mask (1 bit: 1 << 0)
501 pub const mask: u32 = 1 << offset;
502 /// Read-only values (empty)
503 pub mod R {}
504 /// Write-only values (empty)
505 pub mod W {}
506 /// Read-write values (empty)
507 pub mod RW {}
508 }
509}
510
511/// embedded synchronization code register
512pub mod ESCR {
513
514 /// Frame end delimiter code
515 pub mod FEC {
516 /// Offset (24 bits)
517 pub const offset: u32 = 24;
518 /// Mask (8 bits: 0xff << 24)
519 pub const mask: u32 = 0xff << offset;
520 /// Read-only values (empty)
521 pub mod R {}
522 /// Write-only values (empty)
523 pub mod W {}
524 /// Read-write values (empty)
525 pub mod RW {}
526 }
527
528 /// Line end delimiter code
529 pub mod LEC {
530 /// Offset (16 bits)
531 pub const offset: u32 = 16;
532 /// Mask (8 bits: 0xff << 16)
533 pub const mask: u32 = 0xff << offset;
534 /// Read-only values (empty)
535 pub mod R {}
536 /// Write-only values (empty)
537 pub mod W {}
538 /// Read-write values (empty)
539 pub mod RW {}
540 }
541
542 /// Line start delimiter code
543 pub mod LSC {
544 /// Offset (8 bits)
545 pub const offset: u32 = 8;
546 /// Mask (8 bits: 0xff << 8)
547 pub const mask: u32 = 0xff << offset;
548 /// Read-only values (empty)
549 pub mod R {}
550 /// Write-only values (empty)
551 pub mod W {}
552 /// Read-write values (empty)
553 pub mod RW {}
554 }
555
556 /// Frame start delimiter code
557 pub mod FSC {
558 /// Offset (0 bits)
559 pub const offset: u32 = 0;
560 /// Mask (8 bits: 0xff << 0)
561 pub const mask: u32 = 0xff << offset;
562 /// Read-only values (empty)
563 pub mod R {}
564 /// Write-only values (empty)
565 pub mod W {}
566 /// Read-write values (empty)
567 pub mod RW {}
568 }
569}
570
571/// embedded synchronization unmask register
572pub mod ESUR {
573
574 /// Frame end delimiter unmask
575 pub mod FEU {
576 /// Offset (24 bits)
577 pub const offset: u32 = 24;
578 /// Mask (8 bits: 0xff << 24)
579 pub const mask: u32 = 0xff << offset;
580 /// Read-only values (empty)
581 pub mod R {}
582 /// Write-only values (empty)
583 pub mod W {}
584 /// Read-write values (empty)
585 pub mod RW {}
586 }
587
588 /// Line end delimiter unmask
589 pub mod LEU {
590 /// Offset (16 bits)
591 pub const offset: u32 = 16;
592 /// Mask (8 bits: 0xff << 16)
593 pub const mask: u32 = 0xff << offset;
594 /// Read-only values (empty)
595 pub mod R {}
596 /// Write-only values (empty)
597 pub mod W {}
598 /// Read-write values (empty)
599 pub mod RW {}
600 }
601
602 /// Line start delimiter unmask
603 pub mod LSU {
604 /// Offset (8 bits)
605 pub const offset: u32 = 8;
606 /// Mask (8 bits: 0xff << 8)
607 pub const mask: u32 = 0xff << offset;
608 /// Read-only values (empty)
609 pub mod R {}
610 /// Write-only values (empty)
611 pub mod W {}
612 /// Read-write values (empty)
613 pub mod RW {}
614 }
615
616 /// Frame start delimiter unmask
617 pub mod FSU {
618 /// Offset (0 bits)
619 pub const offset: u32 = 0;
620 /// Mask (8 bits: 0xff << 0)
621 pub const mask: u32 = 0xff << offset;
622 /// Read-only values (empty)
623 pub mod R {}
624 /// Write-only values (empty)
625 pub mod W {}
626 /// Read-write values (empty)
627 pub mod RW {}
628 }
629}
630
631/// crop window start
632pub mod CWSTRT {
633
634 /// Vertical start line count
635 pub mod VST {
636 /// Offset (16 bits)
637 pub const offset: u32 = 16;
638 /// Mask (13 bits: 0x1fff << 16)
639 pub const mask: u32 = 0x1fff << offset;
640 /// Read-only values (empty)
641 pub mod R {}
642 /// Write-only values (empty)
643 pub mod W {}
644 /// Read-write values (empty)
645 pub mod RW {}
646 }
647
648 /// Horizontal offset count
649 pub mod HOFFCNT {
650 /// Offset (0 bits)
651 pub const offset: u32 = 0;
652 /// Mask (14 bits: 0x3fff << 0)
653 pub const mask: u32 = 0x3fff << offset;
654 /// Read-only values (empty)
655 pub mod R {}
656 /// Write-only values (empty)
657 pub mod W {}
658 /// Read-write values (empty)
659 pub mod RW {}
660 }
661}
662
663/// crop window size
664pub mod CWSIZE {
665
666 /// Vertical line count
667 pub mod VLINE {
668 /// Offset (16 bits)
669 pub const offset: u32 = 16;
670 /// Mask (14 bits: 0x3fff << 16)
671 pub const mask: u32 = 0x3fff << offset;
672 /// Read-only values (empty)
673 pub mod R {}
674 /// Write-only values (empty)
675 pub mod W {}
676 /// Read-write values (empty)
677 pub mod RW {}
678 }
679
680 /// Capture count
681 pub mod CAPCNT {
682 /// Offset (0 bits)
683 pub const offset: u32 = 0;
684 /// Mask (14 bits: 0x3fff << 0)
685 pub const mask: u32 = 0x3fff << offset;
686 /// Read-only values (empty)
687 pub mod R {}
688 /// Write-only values (empty)
689 pub mod W {}
690 /// Read-write values (empty)
691 pub mod RW {}
692 }
693}
694
695/// data register
696pub mod DR {
697
698 /// Data byte 3
699 pub mod Byte3 {
700 /// Offset (24 bits)
701 pub const offset: u32 = 24;
702 /// Mask (8 bits: 0xff << 24)
703 pub const mask: u32 = 0xff << offset;
704 /// Read-only values (empty)
705 pub mod R {}
706 /// Write-only values (empty)
707 pub mod W {}
708 /// Read-write values (empty)
709 pub mod RW {}
710 }
711
712 /// Data byte 2
713 pub mod Byte2 {
714 /// Offset (16 bits)
715 pub const offset: u32 = 16;
716 /// Mask (8 bits: 0xff << 16)
717 pub const mask: u32 = 0xff << offset;
718 /// Read-only values (empty)
719 pub mod R {}
720 /// Write-only values (empty)
721 pub mod W {}
722 /// Read-write values (empty)
723 pub mod RW {}
724 }
725
726 /// Data byte 1
727 pub mod Byte1 {
728 /// Offset (8 bits)
729 pub const offset: u32 = 8;
730 /// Mask (8 bits: 0xff << 8)
731 pub const mask: u32 = 0xff << offset;
732 /// Read-only values (empty)
733 pub mod R {}
734 /// Write-only values (empty)
735 pub mod W {}
736 /// Read-write values (empty)
737 pub mod RW {}
738 }
739
740 /// Data byte 0
741 pub mod Byte0 {
742 /// Offset (0 bits)
743 pub const offset: u32 = 0;
744 /// Mask (8 bits: 0xff << 0)
745 pub const mask: u32 = 0xff << offset;
746 /// Read-only values (empty)
747 pub mod R {}
748 /// Write-only values (empty)
749 pub mod W {}
750 /// Read-write values (empty)
751 pub mod RW {}
752 }
753}
754#[repr(C)]
755pub struct RegisterBlock {
756 /// control register 1
757 pub CR: RWRegister<u32>,
758
759 /// status register
760 pub SR: RORegister<u32>,
761
762 /// raw interrupt status register
763 pub RIS: RORegister<u32>,
764
765 /// interrupt enable register
766 pub IER: RWRegister<u32>,
767
768 /// masked interrupt status register
769 pub MIS: RORegister<u32>,
770
771 /// interrupt clear register
772 pub ICR: WORegister<u32>,
773
774 /// embedded synchronization code register
775 pub ESCR: RWRegister<u32>,
776
777 /// embedded synchronization unmask register
778 pub ESUR: RWRegister<u32>,
779
780 /// crop window start
781 pub CWSTRT: RWRegister<u32>,
782
783 /// crop window size
784 pub CWSIZE: RWRegister<u32>,
785
786 /// data register
787 pub DR: RORegister<u32>,
788}
789pub struct ResetValues {
790 pub CR: u32,
791 pub SR: u32,
792 pub RIS: u32,
793 pub IER: u32,
794 pub MIS: u32,
795 pub ICR: u32,
796 pub ESCR: u32,
797 pub ESUR: u32,
798 pub CWSTRT: u32,
799 pub CWSIZE: u32,
800 pub DR: u32,
801}
802#[cfg(not(feature = "nosync"))]
803pub struct Instance {
804 pub(crate) addr: u32,
805 pub(crate) _marker: PhantomData<*const RegisterBlock>,
806}
807#[cfg(not(feature = "nosync"))]
808impl ::core::ops::Deref for Instance {
809 type Target = RegisterBlock;
810 #[inline(always)]
811 fn deref(&self) -> &RegisterBlock {
812 unsafe { &*(self.addr as *const _) }
813 }
814}
815#[cfg(feature = "rtic")]
816unsafe impl Send for Instance {}