stm32ral/stm32f2/peripherals/adc_common.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Common ADC registers
4//!
5//! Used by: stm32f215, stm32f217
6
7use crate::{RORegister, RWRegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// ADC Common status register
12pub mod CSR {
13
14 /// Overrun flag of ADC3
15 pub mod OVR3 {
16 /// Offset (21 bits)
17 pub const offset: u32 = 21;
18 /// Mask (1 bit: 1 << 21)
19 pub const mask: u32 = 1 << offset;
20 /// Read-only values
21 pub mod R {
22
23 /// 0b0: No overrun occurred
24 pub const NoOverrun: u32 = 0b0;
25
26 /// 0b1: Overrun occurred
27 pub const Overrun: u32 = 0b1;
28 }
29 /// Write-only values (empty)
30 pub mod W {}
31 /// Read-write values (empty)
32 pub mod RW {}
33 }
34
35 /// Regular channel Start flag of ADC 3
36 pub mod STRT3 {
37 /// Offset (20 bits)
38 pub const offset: u32 = 20;
39 /// Mask (1 bit: 1 << 20)
40 pub const mask: u32 = 1 << offset;
41 /// Read-only values
42 pub mod R {
43
44 /// 0b0: No regular channel conversion started
45 pub const NotStarted: u32 = 0b0;
46
47 /// 0b1: Regular channel conversion has started
48 pub const Started: u32 = 0b1;
49 }
50 /// Write-only values (empty)
51 pub mod W {}
52 /// Read-write values (empty)
53 pub mod RW {}
54 }
55
56 /// Injected channel Start flag of ADC 3
57 pub mod JSTRT3 {
58 /// Offset (19 bits)
59 pub const offset: u32 = 19;
60 /// Mask (1 bit: 1 << 19)
61 pub const mask: u32 = 1 << offset;
62 /// Read-only values
63 pub mod R {
64
65 /// 0b0: No injected channel conversion started
66 pub const NotStarted: u32 = 0b0;
67
68 /// 0b1: Injected channel conversion has started
69 pub const Started: u32 = 0b1;
70 }
71 /// Write-only values (empty)
72 pub mod W {}
73 /// Read-write values (empty)
74 pub mod RW {}
75 }
76
77 /// Injected channel end of conversion of ADC 3
78 pub mod JEOC3 {
79 /// Offset (18 bits)
80 pub const offset: u32 = 18;
81 /// Mask (1 bit: 1 << 18)
82 pub const mask: u32 = 1 << offset;
83 /// Read-only values
84 pub mod R {
85
86 /// 0b0: Conversion is not complete
87 pub const NotComplete: u32 = 0b0;
88
89 /// 0b1: Conversion complete
90 pub const Complete: u32 = 0b1;
91 }
92 /// Write-only values (empty)
93 pub mod W {}
94 /// Read-write values (empty)
95 pub mod RW {}
96 }
97
98 /// End of conversion of ADC 3
99 pub mod EOC3 {
100 /// Offset (17 bits)
101 pub const offset: u32 = 17;
102 /// Mask (1 bit: 1 << 17)
103 pub const mask: u32 = 1 << offset;
104 pub use super::JEOC3::R;
105 /// Write-only values (empty)
106 pub mod W {}
107 /// Read-write values (empty)
108 pub mod RW {}
109 }
110
111 /// Analog watchdog flag of ADC 3
112 pub mod AWD3 {
113 /// Offset (16 bits)
114 pub const offset: u32 = 16;
115 /// Mask (1 bit: 1 << 16)
116 pub const mask: u32 = 1 << offset;
117 /// Read-only values
118 pub mod R {
119
120 /// 0b0: No analog watchdog event occurred
121 pub const NoEvent: u32 = 0b0;
122
123 /// 0b1: Analog watchdog event occurred
124 pub const Event: u32 = 0b1;
125 }
126 /// Write-only values (empty)
127 pub mod W {}
128 /// Read-write values (empty)
129 pub mod RW {}
130 }
131
132 /// Overrun flag of ADC 2
133 pub mod OVR2 {
134 /// Offset (13 bits)
135 pub const offset: u32 = 13;
136 /// Mask (1 bit: 1 << 13)
137 pub const mask: u32 = 1 << offset;
138 pub use super::OVR3::R;
139 /// Write-only values (empty)
140 pub mod W {}
141 /// Read-write values (empty)
142 pub mod RW {}
143 }
144
145 /// Regular channel Start flag of ADC 2
146 pub mod STRT2 {
147 /// Offset (12 bits)
148 pub const offset: u32 = 12;
149 /// Mask (1 bit: 1 << 12)
150 pub const mask: u32 = 1 << offset;
151 pub use super::STRT3::R;
152 /// Write-only values (empty)
153 pub mod W {}
154 /// Read-write values (empty)
155 pub mod RW {}
156 }
157
158 /// Injected channel Start flag of ADC 2
159 pub mod JSTRT2 {
160 /// Offset (11 bits)
161 pub const offset: u32 = 11;
162 /// Mask (1 bit: 1 << 11)
163 pub const mask: u32 = 1 << offset;
164 pub use super::JSTRT3::R;
165 /// Write-only values (empty)
166 pub mod W {}
167 /// Read-write values (empty)
168 pub mod RW {}
169 }
170
171 /// Injected channel end of conversion of ADC 2
172 pub mod JEOC2 {
173 /// Offset (10 bits)
174 pub const offset: u32 = 10;
175 /// Mask (1 bit: 1 << 10)
176 pub const mask: u32 = 1 << offset;
177 pub use super::JEOC3::R;
178 /// Write-only values (empty)
179 pub mod W {}
180 /// Read-write values (empty)
181 pub mod RW {}
182 }
183
184 /// End of conversion of ADC 2
185 pub mod EOC2 {
186 /// Offset (9 bits)
187 pub const offset: u32 = 9;
188 /// Mask (1 bit: 1 << 9)
189 pub const mask: u32 = 1 << offset;
190 pub use super::JEOC3::R;
191 /// Write-only values (empty)
192 pub mod W {}
193 /// Read-write values (empty)
194 pub mod RW {}
195 }
196
197 /// Analog watchdog flag of ADC 2
198 pub mod AWD2 {
199 /// Offset (8 bits)
200 pub const offset: u32 = 8;
201 /// Mask (1 bit: 1 << 8)
202 pub const mask: u32 = 1 << offset;
203 pub use super::AWD3::R;
204 /// Write-only values (empty)
205 pub mod W {}
206 /// Read-write values (empty)
207 pub mod RW {}
208 }
209
210 /// Overrun flag of ADC 1
211 pub mod OVR1 {
212 /// Offset (5 bits)
213 pub const offset: u32 = 5;
214 /// Mask (1 bit: 1 << 5)
215 pub const mask: u32 = 1 << offset;
216 pub use super::OVR3::R;
217 /// Write-only values (empty)
218 pub mod W {}
219 /// Read-write values (empty)
220 pub mod RW {}
221 }
222
223 /// Regular channel Start flag of ADC 1
224 pub mod STRT1 {
225 /// Offset (4 bits)
226 pub const offset: u32 = 4;
227 /// Mask (1 bit: 1 << 4)
228 pub const mask: u32 = 1 << offset;
229 pub use super::STRT3::R;
230 /// Write-only values (empty)
231 pub mod W {}
232 /// Read-write values (empty)
233 pub mod RW {}
234 }
235
236 /// Injected channel Start flag of ADC 1
237 pub mod JSTRT1 {
238 /// Offset (3 bits)
239 pub const offset: u32 = 3;
240 /// Mask (1 bit: 1 << 3)
241 pub const mask: u32 = 1 << offset;
242 pub use super::JSTRT3::R;
243 /// Write-only values (empty)
244 pub mod W {}
245 /// Read-write values (empty)
246 pub mod RW {}
247 }
248
249 /// Injected channel end of conversion of ADC 1
250 pub mod JEOC1 {
251 /// Offset (2 bits)
252 pub const offset: u32 = 2;
253 /// Mask (1 bit: 1 << 2)
254 pub const mask: u32 = 1 << offset;
255 pub use super::JEOC3::R;
256 /// Write-only values (empty)
257 pub mod W {}
258 /// Read-write values (empty)
259 pub mod RW {}
260 }
261
262 /// End of conversion of ADC 1
263 pub mod EOC1 {
264 /// Offset (1 bits)
265 pub const offset: u32 = 1;
266 /// Mask (1 bit: 1 << 1)
267 pub const mask: u32 = 1 << offset;
268 pub use super::JEOC3::R;
269 /// Write-only values (empty)
270 pub mod W {}
271 /// Read-write values (empty)
272 pub mod RW {}
273 }
274
275 /// Analog watchdog flag of ADC 1
276 pub mod AWD1 {
277 /// Offset (0 bits)
278 pub const offset: u32 = 0;
279 /// Mask (1 bit: 1 << 0)
280 pub const mask: u32 = 1 << offset;
281 pub use super::AWD3::R;
282 /// Write-only values (empty)
283 pub mod W {}
284 /// Read-write values (empty)
285 pub mod RW {}
286 }
287}
288
289/// ADC common control register
290pub mod CCR {
291
292 /// Temperature sensor and VREFINT enable
293 pub mod TSVREFE {
294 /// Offset (23 bits)
295 pub const offset: u32 = 23;
296 /// Mask (1 bit: 1 << 23)
297 pub const mask: u32 = 1 << offset;
298 /// Read-only values (empty)
299 pub mod R {}
300 /// Write-only values (empty)
301 pub mod W {}
302 /// Read-write values
303 pub mod RW {
304
305 /// 0b0: Temperature sensor and V_REFINT channel disabled
306 pub const Disabled: u32 = 0b0;
307
308 /// 0b1: Temperature sensor and V_REFINT channel enabled
309 pub const Enabled: u32 = 0b1;
310 }
311 }
312
313 /// VBAT enable
314 pub mod VBATE {
315 /// Offset (22 bits)
316 pub const offset: u32 = 22;
317 /// Mask (1 bit: 1 << 22)
318 pub const mask: u32 = 1 << offset;
319 /// Read-only values (empty)
320 pub mod R {}
321 /// Write-only values (empty)
322 pub mod W {}
323 /// Read-write values
324 pub mod RW {
325
326 /// 0b0: V_BAT channel disabled
327 pub const Disabled: u32 = 0b0;
328
329 /// 0b1: V_BAT channel enabled
330 pub const Enabled: u32 = 0b1;
331 }
332 }
333
334 /// ADC prescaler
335 pub mod ADCPRE {
336 /// Offset (16 bits)
337 pub const offset: u32 = 16;
338 /// Mask (2 bits: 0b11 << 16)
339 pub const mask: u32 = 0b11 << offset;
340 /// Read-only values (empty)
341 pub mod R {}
342 /// Write-only values (empty)
343 pub mod W {}
344 /// Read-write values
345 pub mod RW {
346
347 /// 0b00: PCLK2 divided by 2
348 pub const Div2: u32 = 0b00;
349
350 /// 0b01: PCLK2 divided by 4
351 pub const Div4: u32 = 0b01;
352
353 /// 0b10: PCLK2 divided by 6
354 pub const Div6: u32 = 0b10;
355
356 /// 0b11: PCLK2 divided by 8
357 pub const Div8: u32 = 0b11;
358 }
359 }
360
361 /// Direct memory access mode for multi ADC mode
362 pub mod DMA {
363 /// Offset (14 bits)
364 pub const offset: u32 = 14;
365 /// Mask (2 bits: 0b11 << 14)
366 pub const mask: u32 = 0b11 << offset;
367 /// Read-only values (empty)
368 pub mod R {}
369 /// Write-only values (empty)
370 pub mod W {}
371 /// Read-write values
372 pub mod RW {
373
374 /// 0b00: DMA mode disabled
375 pub const Disabled: u32 = 0b00;
376
377 /// 0b01: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)
378 pub const Mode1: u32 = 0b01;
379
380 /// 0b10: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
381 pub const Mode2: u32 = 0b10;
382
383 /// 0b11: DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
384 pub const Mode3: u32 = 0b11;
385 }
386 }
387
388 /// DMA disable selection for multi-ADC mode
389 pub mod DDS {
390 /// Offset (13 bits)
391 pub const offset: u32 = 13;
392 /// Mask (1 bit: 1 << 13)
393 pub const mask: u32 = 1 << offset;
394 /// Read-only values (empty)
395 pub mod R {}
396 /// Write-only values (empty)
397 pub mod W {}
398 /// Read-write values
399 pub mod RW {
400
401 /// 0b0: No new DMA request is issued after the last transfer
402 pub const Single: u32 = 0b0;
403
404 /// 0b1: DMA requests are issued as long as data are converted and DMA=01, 10 or 11
405 pub const Continuous: u32 = 0b1;
406 }
407 }
408
409 /// Delay between 2 sampling phases
410 pub mod DELAY {
411 /// Offset (8 bits)
412 pub const offset: u32 = 8;
413 /// Mask (4 bits: 0b1111 << 8)
414 pub const mask: u32 = 0b1111 << offset;
415 /// Read-only values (empty)
416 pub mod R {}
417 /// Write-only values (empty)
418 pub mod W {}
419 /// Read-write values (empty)
420 pub mod RW {}
421 }
422
423 /// Multi ADC mode selection
424 pub mod MULTI {
425 /// Offset (0 bits)
426 pub const offset: u32 = 0;
427 /// Mask (5 bits: 0b11111 << 0)
428 pub const mask: u32 = 0b11111 << offset;
429 /// Read-only values (empty)
430 pub mod R {}
431 /// Write-only values (empty)
432 pub mod W {}
433 /// Read-write values
434 pub mod RW {
435
436 /// 0b00000: All the ADCs independent: independent mode
437 pub const Independent: u32 = 0b00000;
438
439 /// 0b00001: Dual ADC1 and ADC2, combined regular and injected simultaneous mode
440 pub const DualRJ: u32 = 0b00001;
441
442 /// 0b00010: Dual ADC1 and ADC2, combined regular and alternate trigger mode
443 pub const DualRA: u32 = 0b00010;
444
445 /// 0b00101: Dual ADC1 and ADC2, injected simultaneous mode only
446 pub const DualJ: u32 = 0b00101;
447
448 /// 0b00110: Dual ADC1 and ADC2, regular simultaneous mode only
449 pub const DualR: u32 = 0b00110;
450
451 /// 0b00111: Dual ADC1 and ADC2, interleaved mode only
452 pub const DualI: u32 = 0b00111;
453
454 /// 0b01001: Dual ADC1 and ADC2, alternate trigger mode only
455 pub const DualA: u32 = 0b01001;
456
457 /// 0b10001: Triple ADC, regular and injected simultaneous mode
458 pub const TripleRJ: u32 = 0b10001;
459
460 /// 0b10010: Triple ADC, regular and alternate trigger mode
461 pub const TripleRA: u32 = 0b10010;
462
463 /// 0b10101: Triple ADC, injected simultaneous mode only
464 pub const TripleJ: u32 = 0b10101;
465
466 /// 0b10110: Triple ADC, regular simultaneous mode only
467 pub const TripleR: u32 = 0b10110;
468
469 /// 0b10111: Triple ADC, interleaved mode only
470 pub const TripleI: u32 = 0b10111;
471
472 /// 0b11000: Triple ADC, alternate trigger mode only
473 pub const TripleA: u32 = 0b11000;
474 }
475 }
476}
477
478/// ADC common regular data register for dual and triple modes
479pub mod CDR {
480
481 /// 2nd data item of a pair of regular conversions
482 pub mod DATA2 {
483 /// Offset (16 bits)
484 pub const offset: u32 = 16;
485 /// Mask (16 bits: 0xffff << 16)
486 pub const mask: u32 = 0xffff << offset;
487 /// Read-only values (empty)
488 pub mod R {}
489 /// Write-only values (empty)
490 pub mod W {}
491 /// Read-write values (empty)
492 pub mod RW {}
493 }
494
495 /// 1st data item of a pair of regular conversions
496 pub mod DATA1 {
497 /// Offset (0 bits)
498 pub const offset: u32 = 0;
499 /// Mask (16 bits: 0xffff << 0)
500 pub const mask: u32 = 0xffff << offset;
501 /// Read-only values (empty)
502 pub mod R {}
503 /// Write-only values (empty)
504 pub mod W {}
505 /// Read-write values (empty)
506 pub mod RW {}
507 }
508}
509#[repr(C)]
510pub struct RegisterBlock {
511 /// ADC Common status register
512 pub CSR: RORegister<u32>,
513
514 /// ADC common control register
515 pub CCR: RWRegister<u32>,
516
517 /// ADC common regular data register for dual and triple modes
518 pub CDR: RORegister<u32>,
519}
520pub struct ResetValues {
521 pub CSR: u32,
522 pub CCR: u32,
523 pub CDR: u32,
524}
525#[cfg(not(feature = "nosync"))]
526pub struct Instance {
527 pub(crate) addr: u32,
528 pub(crate) _marker: PhantomData<*const RegisterBlock>,
529}
530#[cfg(not(feature = "nosync"))]
531impl ::core::ops::Deref for Instance {
532 type Target = RegisterBlock;
533 #[inline(always)]
534 fn deref(&self) -> &RegisterBlock {
535 unsafe { &*(self.addr as *const _) }
536 }
537}
538#[cfg(feature = "rtic")]
539unsafe impl Send for Instance {}