stm32ral/stm32f1/stm32f107/can1.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Controller area network
4
5use crate::{RORegister, RWRegister};
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// CAN_MCR
10pub mod MCR {
11
12 /// DBF
13 pub mod DBF {
14 /// Offset (16 bits)
15 pub const offset: u32 = 16;
16 /// Mask (1 bit: 1 << 16)
17 pub const mask: u32 = 1 << offset;
18 /// Read-only values (empty)
19 pub mod R {}
20 /// Write-only values (empty)
21 pub mod W {}
22 /// Read-write values (empty)
23 pub mod RW {}
24 }
25
26 /// RESET
27 pub mod RESET {
28 /// Offset (15 bits)
29 pub const offset: u32 = 15;
30 /// Mask (1 bit: 1 << 15)
31 pub const mask: u32 = 1 << offset;
32 /// Read-only values (empty)
33 pub mod R {}
34 /// Write-only values (empty)
35 pub mod W {}
36 /// Read-write values (empty)
37 pub mod RW {}
38 }
39
40 /// TTCM
41 pub mod TTCM {
42 /// Offset (7 bits)
43 pub const offset: u32 = 7;
44 /// Mask (1 bit: 1 << 7)
45 pub const mask: u32 = 1 << offset;
46 /// Read-only values (empty)
47 pub mod R {}
48 /// Write-only values (empty)
49 pub mod W {}
50 /// Read-write values (empty)
51 pub mod RW {}
52 }
53
54 /// ABOM
55 pub mod ABOM {
56 /// Offset (6 bits)
57 pub const offset: u32 = 6;
58 /// Mask (1 bit: 1 << 6)
59 pub const mask: u32 = 1 << offset;
60 /// Read-only values (empty)
61 pub mod R {}
62 /// Write-only values (empty)
63 pub mod W {}
64 /// Read-write values (empty)
65 pub mod RW {}
66 }
67
68 /// AWUM
69 pub mod AWUM {
70 /// Offset (5 bits)
71 pub const offset: u32 = 5;
72 /// Mask (1 bit: 1 << 5)
73 pub const mask: u32 = 1 << offset;
74 /// Read-only values (empty)
75 pub mod R {}
76 /// Write-only values (empty)
77 pub mod W {}
78 /// Read-write values (empty)
79 pub mod RW {}
80 }
81
82 /// NART
83 pub mod NART {
84 /// Offset (4 bits)
85 pub const offset: u32 = 4;
86 /// Mask (1 bit: 1 << 4)
87 pub const mask: u32 = 1 << offset;
88 /// Read-only values (empty)
89 pub mod R {}
90 /// Write-only values (empty)
91 pub mod W {}
92 /// Read-write values (empty)
93 pub mod RW {}
94 }
95
96 /// RFLM
97 pub mod RFLM {
98 /// Offset (3 bits)
99 pub const offset: u32 = 3;
100 /// Mask (1 bit: 1 << 3)
101 pub const mask: u32 = 1 << offset;
102 /// Read-only values (empty)
103 pub mod R {}
104 /// Write-only values (empty)
105 pub mod W {}
106 /// Read-write values (empty)
107 pub mod RW {}
108 }
109
110 /// TXFP
111 pub mod TXFP {
112 /// Offset (2 bits)
113 pub const offset: u32 = 2;
114 /// Mask (1 bit: 1 << 2)
115 pub const mask: u32 = 1 << offset;
116 /// Read-only values (empty)
117 pub mod R {}
118 /// Write-only values (empty)
119 pub mod W {}
120 /// Read-write values (empty)
121 pub mod RW {}
122 }
123
124 /// SLEEP
125 pub mod SLEEP {
126 /// Offset (1 bits)
127 pub const offset: u32 = 1;
128 /// Mask (1 bit: 1 << 1)
129 pub const mask: u32 = 1 << offset;
130 /// Read-only values (empty)
131 pub mod R {}
132 /// Write-only values (empty)
133 pub mod W {}
134 /// Read-write values (empty)
135 pub mod RW {}
136 }
137
138 /// INRQ
139 pub mod INRQ {
140 /// Offset (0 bits)
141 pub const offset: u32 = 0;
142 /// Mask (1 bit: 1 << 0)
143 pub const mask: u32 = 1 << offset;
144 /// Read-only values (empty)
145 pub mod R {}
146 /// Write-only values (empty)
147 pub mod W {}
148 /// Read-write values (empty)
149 pub mod RW {}
150 }
151}
152
153/// CAN_MSR
154pub mod MSR {
155
156 /// RX
157 pub mod RX {
158 /// Offset (11 bits)
159 pub const offset: u32 = 11;
160 /// Mask (1 bit: 1 << 11)
161 pub const mask: u32 = 1 << offset;
162 /// Read-only values (empty)
163 pub mod R {}
164 /// Write-only values (empty)
165 pub mod W {}
166 /// Read-write values (empty)
167 pub mod RW {}
168 }
169
170 /// SAMP
171 pub mod SAMP {
172 /// Offset (10 bits)
173 pub const offset: u32 = 10;
174 /// Mask (1 bit: 1 << 10)
175 pub const mask: u32 = 1 << offset;
176 /// Read-only values (empty)
177 pub mod R {}
178 /// Write-only values (empty)
179 pub mod W {}
180 /// Read-write values (empty)
181 pub mod RW {}
182 }
183
184 /// RXM
185 pub mod RXM {
186 /// Offset (9 bits)
187 pub const offset: u32 = 9;
188 /// Mask (1 bit: 1 << 9)
189 pub const mask: u32 = 1 << offset;
190 /// Read-only values (empty)
191 pub mod R {}
192 /// Write-only values (empty)
193 pub mod W {}
194 /// Read-write values (empty)
195 pub mod RW {}
196 }
197
198 /// TXM
199 pub mod TXM {
200 /// Offset (8 bits)
201 pub const offset: u32 = 8;
202 /// Mask (1 bit: 1 << 8)
203 pub const mask: u32 = 1 << offset;
204 /// Read-only values (empty)
205 pub mod R {}
206 /// Write-only values (empty)
207 pub mod W {}
208 /// Read-write values (empty)
209 pub mod RW {}
210 }
211
212 /// SLAKI
213 pub mod SLAKI {
214 /// Offset (4 bits)
215 pub const offset: u32 = 4;
216 /// Mask (1 bit: 1 << 4)
217 pub const mask: u32 = 1 << offset;
218 /// Read-only values (empty)
219 pub mod R {}
220 /// Write-only values (empty)
221 pub mod W {}
222 /// Read-write values (empty)
223 pub mod RW {}
224 }
225
226 /// WKUI
227 pub mod WKUI {
228 /// Offset (3 bits)
229 pub const offset: u32 = 3;
230 /// Mask (1 bit: 1 << 3)
231 pub const mask: u32 = 1 << offset;
232 /// Read-only values (empty)
233 pub mod R {}
234 /// Write-only values (empty)
235 pub mod W {}
236 /// Read-write values (empty)
237 pub mod RW {}
238 }
239
240 /// ERRI
241 pub mod ERRI {
242 /// Offset (2 bits)
243 pub const offset: u32 = 2;
244 /// Mask (1 bit: 1 << 2)
245 pub const mask: u32 = 1 << offset;
246 /// Read-only values (empty)
247 pub mod R {}
248 /// Write-only values (empty)
249 pub mod W {}
250 /// Read-write values (empty)
251 pub mod RW {}
252 }
253
254 /// SLAK
255 pub mod SLAK {
256 /// Offset (1 bits)
257 pub const offset: u32 = 1;
258 /// Mask (1 bit: 1 << 1)
259 pub const mask: u32 = 1 << offset;
260 /// Read-only values (empty)
261 pub mod R {}
262 /// Write-only values (empty)
263 pub mod W {}
264 /// Read-write values (empty)
265 pub mod RW {}
266 }
267
268 /// INAK
269 pub mod INAK {
270 /// Offset (0 bits)
271 pub const offset: u32 = 0;
272 /// Mask (1 bit: 1 << 0)
273 pub const mask: u32 = 1 << offset;
274 /// Read-only values (empty)
275 pub mod R {}
276 /// Write-only values (empty)
277 pub mod W {}
278 /// Read-write values (empty)
279 pub mod RW {}
280 }
281}
282
283/// CAN_TSR
284pub mod TSR {
285
286 /// Lowest priority flag for mailbox 2
287 pub mod LOW2 {
288 /// Offset (31 bits)
289 pub const offset: u32 = 31;
290 /// Mask (1 bit: 1 << 31)
291 pub const mask: u32 = 1 << offset;
292 /// Read-only values (empty)
293 pub mod R {}
294 /// Write-only values (empty)
295 pub mod W {}
296 /// Read-write values (empty)
297 pub mod RW {}
298 }
299
300 /// Lowest priority flag for mailbox 1
301 pub mod LOW1 {
302 /// Offset (30 bits)
303 pub const offset: u32 = 30;
304 /// Mask (1 bit: 1 << 30)
305 pub const mask: u32 = 1 << offset;
306 /// Read-only values (empty)
307 pub mod R {}
308 /// Write-only values (empty)
309 pub mod W {}
310 /// Read-write values (empty)
311 pub mod RW {}
312 }
313
314 /// Lowest priority flag for mailbox 0
315 pub mod LOW0 {
316 /// Offset (29 bits)
317 pub const offset: u32 = 29;
318 /// Mask (1 bit: 1 << 29)
319 pub const mask: u32 = 1 << offset;
320 /// Read-only values (empty)
321 pub mod R {}
322 /// Write-only values (empty)
323 pub mod W {}
324 /// Read-write values (empty)
325 pub mod RW {}
326 }
327
328 /// Lowest priority flag for mailbox 2
329 pub mod TME2 {
330 /// Offset (28 bits)
331 pub const offset: u32 = 28;
332 /// Mask (1 bit: 1 << 28)
333 pub const mask: u32 = 1 << offset;
334 /// Read-only values (empty)
335 pub mod R {}
336 /// Write-only values (empty)
337 pub mod W {}
338 /// Read-write values (empty)
339 pub mod RW {}
340 }
341
342 /// Lowest priority flag for mailbox 1
343 pub mod TME1 {
344 /// Offset (27 bits)
345 pub const offset: u32 = 27;
346 /// Mask (1 bit: 1 << 27)
347 pub const mask: u32 = 1 << offset;
348 /// Read-only values (empty)
349 pub mod R {}
350 /// Write-only values (empty)
351 pub mod W {}
352 /// Read-write values (empty)
353 pub mod RW {}
354 }
355
356 /// Lowest priority flag for mailbox 0
357 pub mod TME0 {
358 /// Offset (26 bits)
359 pub const offset: u32 = 26;
360 /// Mask (1 bit: 1 << 26)
361 pub const mask: u32 = 1 << offset;
362 /// Read-only values (empty)
363 pub mod R {}
364 /// Write-only values (empty)
365 pub mod W {}
366 /// Read-write values (empty)
367 pub mod RW {}
368 }
369
370 /// CODE
371 pub mod CODE {
372 /// Offset (24 bits)
373 pub const offset: u32 = 24;
374 /// Mask (2 bits: 0b11 << 24)
375 pub const mask: u32 = 0b11 << offset;
376 /// Read-only values (empty)
377 pub mod R {}
378 /// Write-only values (empty)
379 pub mod W {}
380 /// Read-write values (empty)
381 pub mod RW {}
382 }
383
384 /// ABRQ2
385 pub mod ABRQ2 {
386 /// Offset (23 bits)
387 pub const offset: u32 = 23;
388 /// Mask (1 bit: 1 << 23)
389 pub const mask: u32 = 1 << offset;
390 /// Read-only values (empty)
391 pub mod R {}
392 /// Write-only values (empty)
393 pub mod W {}
394 /// Read-write values (empty)
395 pub mod RW {}
396 }
397
398 /// TERR2
399 pub mod TERR2 {
400 /// Offset (19 bits)
401 pub const offset: u32 = 19;
402 /// Mask (1 bit: 1 << 19)
403 pub const mask: u32 = 1 << offset;
404 /// Read-only values (empty)
405 pub mod R {}
406 /// Write-only values (empty)
407 pub mod W {}
408 /// Read-write values (empty)
409 pub mod RW {}
410 }
411
412 /// ALST2
413 pub mod ALST2 {
414 /// Offset (18 bits)
415 pub const offset: u32 = 18;
416 /// Mask (1 bit: 1 << 18)
417 pub const mask: u32 = 1 << offset;
418 /// Read-only values (empty)
419 pub mod R {}
420 /// Write-only values (empty)
421 pub mod W {}
422 /// Read-write values (empty)
423 pub mod RW {}
424 }
425
426 /// TXOK2
427 pub mod TXOK2 {
428 /// Offset (17 bits)
429 pub const offset: u32 = 17;
430 /// Mask (1 bit: 1 << 17)
431 pub const mask: u32 = 1 << offset;
432 /// Read-only values (empty)
433 pub mod R {}
434 /// Write-only values (empty)
435 pub mod W {}
436 /// Read-write values (empty)
437 pub mod RW {}
438 }
439
440 /// RQCP2
441 pub mod RQCP2 {
442 /// Offset (16 bits)
443 pub const offset: u32 = 16;
444 /// Mask (1 bit: 1 << 16)
445 pub const mask: u32 = 1 << offset;
446 /// Read-only values (empty)
447 pub mod R {}
448 /// Write-only values (empty)
449 pub mod W {}
450 /// Read-write values (empty)
451 pub mod RW {}
452 }
453
454 /// ABRQ1
455 pub mod ABRQ1 {
456 /// Offset (15 bits)
457 pub const offset: u32 = 15;
458 /// Mask (1 bit: 1 << 15)
459 pub const mask: u32 = 1 << offset;
460 /// Read-only values (empty)
461 pub mod R {}
462 /// Write-only values (empty)
463 pub mod W {}
464 /// Read-write values (empty)
465 pub mod RW {}
466 }
467
468 /// TERR1
469 pub mod TERR1 {
470 /// Offset (11 bits)
471 pub const offset: u32 = 11;
472 /// Mask (1 bit: 1 << 11)
473 pub const mask: u32 = 1 << offset;
474 /// Read-only values (empty)
475 pub mod R {}
476 /// Write-only values (empty)
477 pub mod W {}
478 /// Read-write values (empty)
479 pub mod RW {}
480 }
481
482 /// ALST1
483 pub mod ALST1 {
484 /// Offset (10 bits)
485 pub const offset: u32 = 10;
486 /// Mask (1 bit: 1 << 10)
487 pub const mask: u32 = 1 << offset;
488 /// Read-only values (empty)
489 pub mod R {}
490 /// Write-only values (empty)
491 pub mod W {}
492 /// Read-write values (empty)
493 pub mod RW {}
494 }
495
496 /// TXOK1
497 pub mod TXOK1 {
498 /// Offset (9 bits)
499 pub const offset: u32 = 9;
500 /// Mask (1 bit: 1 << 9)
501 pub const mask: u32 = 1 << offset;
502 /// Read-only values (empty)
503 pub mod R {}
504 /// Write-only values (empty)
505 pub mod W {}
506 /// Read-write values (empty)
507 pub mod RW {}
508 }
509
510 /// RQCP1
511 pub mod RQCP1 {
512 /// Offset (8 bits)
513 pub const offset: u32 = 8;
514 /// Mask (1 bit: 1 << 8)
515 pub const mask: u32 = 1 << offset;
516 /// Read-only values (empty)
517 pub mod R {}
518 /// Write-only values (empty)
519 pub mod W {}
520 /// Read-write values (empty)
521 pub mod RW {}
522 }
523
524 /// ABRQ0
525 pub mod ABRQ0 {
526 /// Offset (7 bits)
527 pub const offset: u32 = 7;
528 /// Mask (1 bit: 1 << 7)
529 pub const mask: u32 = 1 << offset;
530 /// Read-only values (empty)
531 pub mod R {}
532 /// Write-only values (empty)
533 pub mod W {}
534 /// Read-write values (empty)
535 pub mod RW {}
536 }
537
538 /// TERR0
539 pub mod TERR0 {
540 /// Offset (3 bits)
541 pub const offset: u32 = 3;
542 /// Mask (1 bit: 1 << 3)
543 pub const mask: u32 = 1 << offset;
544 /// Read-only values (empty)
545 pub mod R {}
546 /// Write-only values (empty)
547 pub mod W {}
548 /// Read-write values (empty)
549 pub mod RW {}
550 }
551
552 /// ALST0
553 pub mod ALST0 {
554 /// Offset (2 bits)
555 pub const offset: u32 = 2;
556 /// Mask (1 bit: 1 << 2)
557 pub const mask: u32 = 1 << offset;
558 /// Read-only values (empty)
559 pub mod R {}
560 /// Write-only values (empty)
561 pub mod W {}
562 /// Read-write values (empty)
563 pub mod RW {}
564 }
565
566 /// TXOK0
567 pub mod TXOK0 {
568 /// Offset (1 bits)
569 pub const offset: u32 = 1;
570 /// Mask (1 bit: 1 << 1)
571 pub const mask: u32 = 1 << offset;
572 /// Read-only values (empty)
573 pub mod R {}
574 /// Write-only values (empty)
575 pub mod W {}
576 /// Read-write values (empty)
577 pub mod RW {}
578 }
579
580 /// RQCP0
581 pub mod RQCP0 {
582 /// Offset (0 bits)
583 pub const offset: u32 = 0;
584 /// Mask (1 bit: 1 << 0)
585 pub const mask: u32 = 1 << offset;
586 /// Read-only values (empty)
587 pub mod R {}
588 /// Write-only values (empty)
589 pub mod W {}
590 /// Read-write values (empty)
591 pub mod RW {}
592 }
593}
594
595/// CAN_RF%sR
596pub mod RF0R {
597
598 /// RFOM0
599 pub mod RFOM {
600 /// Offset (5 bits)
601 pub const offset: u32 = 5;
602 /// Mask (1 bit: 1 << 5)
603 pub const mask: u32 = 1 << offset;
604 /// Read-only values (empty)
605 pub mod R {}
606 /// Write-only values
607 pub mod W {
608
609 /// 0b1: Set by software to release the output mailbox of the FIFO
610 pub const Release: u32 = 0b1;
611 }
612 /// Read-write values (empty)
613 pub mod RW {}
614 }
615
616 /// FOVR0
617 pub mod FOVR {
618 /// Offset (4 bits)
619 pub const offset: u32 = 4;
620 /// Mask (1 bit: 1 << 4)
621 pub const mask: u32 = 1 << offset;
622 /// Read-only values
623 pub mod R {
624
625 /// 0b0: No FIFO x overrun
626 pub const NoOverrun: u32 = 0b0;
627
628 /// 0b1: FIFO x overrun
629 pub const Overrun: u32 = 0b1;
630 }
631 /// Write-only values
632 pub mod W {
633
634 /// 0b1: Clear flag
635 pub const Clear: u32 = 0b1;
636 }
637 /// Read-write values (empty)
638 pub mod RW {}
639 }
640
641 /// FULL0
642 pub mod FULL {
643 /// Offset (3 bits)
644 pub const offset: u32 = 3;
645 /// Mask (1 bit: 1 << 3)
646 pub const mask: u32 = 1 << offset;
647 /// Read-only values
648 pub mod R {
649
650 /// 0b0: FIFO x is not full
651 pub const NotFull: u32 = 0b0;
652
653 /// 0b1: FIFO x is full
654 pub const Full: u32 = 0b1;
655 }
656 pub use super::FOVR::W;
657 /// Read-write values (empty)
658 pub mod RW {}
659 }
660
661 /// FMP0
662 pub mod FMP {
663 /// Offset (0 bits)
664 pub const offset: u32 = 0;
665 /// Mask (2 bits: 0b11 << 0)
666 pub const mask: u32 = 0b11 << offset;
667 /// Read-only values (empty)
668 pub mod R {}
669 /// Write-only values (empty)
670 pub mod W {}
671 /// Read-write values (empty)
672 pub mod RW {}
673 }
674}
675
676/// CAN_RF%sR
677pub mod RF1R {
678 pub use super::RF0R::FMP;
679 pub use super::RF0R::FOVR;
680 pub use super::RF0R::FULL;
681 pub use super::RF0R::RFOM;
682}
683
684/// CAN_IER
685pub mod IER {
686
687 /// SLKIE
688 pub mod SLKIE {
689 /// Offset (17 bits)
690 pub const offset: u32 = 17;
691 /// Mask (1 bit: 1 << 17)
692 pub const mask: u32 = 1 << offset;
693 /// Read-only values (empty)
694 pub mod R {}
695 /// Write-only values (empty)
696 pub mod W {}
697 /// Read-write values
698 pub mod RW {
699
700 /// 0b0: No interrupt when SLAKI bit is set
701 pub const Disabled: u32 = 0b0;
702
703 /// 0b1: Interrupt generated when SLAKI bit is set
704 pub const Enabled: u32 = 0b1;
705 }
706 }
707
708 /// WKUIE
709 pub mod WKUIE {
710 /// Offset (16 bits)
711 pub const offset: u32 = 16;
712 /// Mask (1 bit: 1 << 16)
713 pub const mask: u32 = 1 << offset;
714 /// Read-only values (empty)
715 pub mod R {}
716 /// Write-only values (empty)
717 pub mod W {}
718 /// Read-write values
719 pub mod RW {
720
721 /// 0b0: No interrupt when WKUI is set
722 pub const Disabled: u32 = 0b0;
723
724 /// 0b1: Interrupt generated when WKUI bit is set
725 pub const Enabled: u32 = 0b1;
726 }
727 }
728
729 /// ERRIE
730 pub mod ERRIE {
731 /// Offset (15 bits)
732 pub const offset: u32 = 15;
733 /// Mask (1 bit: 1 << 15)
734 pub const mask: u32 = 1 << offset;
735 /// Read-only values (empty)
736 pub mod R {}
737 /// Write-only values (empty)
738 pub mod W {}
739 /// Read-write values
740 pub mod RW {
741
742 /// 0b0: No interrupt will be generated when an error condition is pending in the CAN_ESR
743 pub const Disabled: u32 = 0b0;
744
745 /// 0b1: An interrupt will be generation when an error condition is pending in the CAN_ESR
746 pub const Enabled: u32 = 0b1;
747 }
748 }
749
750 /// LECIE
751 pub mod LECIE {
752 /// Offset (11 bits)
753 pub const offset: u32 = 11;
754 /// Mask (1 bit: 1 << 11)
755 pub const mask: u32 = 1 << offset;
756 /// Read-only values (empty)
757 pub mod R {}
758 /// Write-only values (empty)
759 pub mod W {}
760 /// Read-write values
761 pub mod RW {
762
763 /// 0b0: ERRI bit will not be set when the error code in LEC\[2:0\] is set by hardware on error detection
764 pub const Disabled: u32 = 0b0;
765
766 /// 0b1: ERRI bit will be set when the error code in LEC\[2:0\] is set by hardware on error detection
767 pub const Enabled: u32 = 0b1;
768 }
769 }
770
771 /// BOFIE
772 pub mod BOFIE {
773 /// Offset (10 bits)
774 pub const offset: u32 = 10;
775 /// Mask (1 bit: 1 << 10)
776 pub const mask: u32 = 1 << offset;
777 /// Read-only values (empty)
778 pub mod R {}
779 /// Write-only values (empty)
780 pub mod W {}
781 /// Read-write values
782 pub mod RW {
783
784 /// 0b0: ERRI bit will not be set when BOFF is set
785 pub const Disabled: u32 = 0b0;
786
787 /// 0b1: ERRI bit will be set when BOFF is set
788 pub const Enabled: u32 = 0b1;
789 }
790 }
791
792 /// EPVIE
793 pub mod EPVIE {
794 /// Offset (9 bits)
795 pub const offset: u32 = 9;
796 /// Mask (1 bit: 1 << 9)
797 pub const mask: u32 = 1 << offset;
798 /// Read-only values (empty)
799 pub mod R {}
800 /// Write-only values (empty)
801 pub mod W {}
802 /// Read-write values
803 pub mod RW {
804
805 /// 0b0: ERRI bit will not be set when EPVF is set
806 pub const Disabled: u32 = 0b0;
807
808 /// 0b1: ERRI bit will be set when EPVF is set
809 pub const Enabled: u32 = 0b1;
810 }
811 }
812
813 /// EWGIE
814 pub mod EWGIE {
815 /// Offset (8 bits)
816 pub const offset: u32 = 8;
817 /// Mask (1 bit: 1 << 8)
818 pub const mask: u32 = 1 << offset;
819 /// Read-only values (empty)
820 pub mod R {}
821 /// Write-only values (empty)
822 pub mod W {}
823 /// Read-write values
824 pub mod RW {
825
826 /// 0b0: ERRI bit will not be set when EWGF is set
827 pub const Disabled: u32 = 0b0;
828
829 /// 0b1: ERRI bit will be set when EWGF is set
830 pub const Enabled: u32 = 0b1;
831 }
832 }
833
834 /// FOVIE1
835 pub mod FOVIE1 {
836 /// Offset (6 bits)
837 pub const offset: u32 = 6;
838 /// Mask (1 bit: 1 << 6)
839 pub const mask: u32 = 1 << offset;
840 /// Read-only values (empty)
841 pub mod R {}
842 /// Write-only values (empty)
843 pub mod W {}
844 /// Read-write values
845 pub mod RW {
846
847 /// 0b0: No interrupt when FOVR is set
848 pub const Disabled: u32 = 0b0;
849
850 /// 0b1: Interrupt generation when FOVR is set
851 pub const Enabled: u32 = 0b1;
852 }
853 }
854
855 /// FFIE1
856 pub mod FFIE1 {
857 /// Offset (5 bits)
858 pub const offset: u32 = 5;
859 /// Mask (1 bit: 1 << 5)
860 pub const mask: u32 = 1 << offset;
861 /// Read-only values (empty)
862 pub mod R {}
863 /// Write-only values (empty)
864 pub mod W {}
865 /// Read-write values
866 pub mod RW {
867
868 /// 0b0: No interrupt when FULL bit is set
869 pub const Disabled: u32 = 0b0;
870
871 /// 0b1: Interrupt generated when FULL bit is set
872 pub const Enabled: u32 = 0b1;
873 }
874 }
875
876 /// FMPIE1
877 pub mod FMPIE1 {
878 /// Offset (4 bits)
879 pub const offset: u32 = 4;
880 /// Mask (1 bit: 1 << 4)
881 pub const mask: u32 = 1 << offset;
882 /// Read-only values (empty)
883 pub mod R {}
884 /// Write-only values (empty)
885 pub mod W {}
886 /// Read-write values
887 pub mod RW {
888
889 /// 0b0: No interrupt generated when state of FMP\[1:0\] bits are not 00b
890 pub const Disabled: u32 = 0b0;
891
892 /// 0b1: Interrupt generated when state of FMP\[1:0\] bits are not 00b
893 pub const Enabled: u32 = 0b1;
894 }
895 }
896
897 /// FOVIE0
898 pub mod FOVIE0 {
899 /// Offset (3 bits)
900 pub const offset: u32 = 3;
901 /// Mask (1 bit: 1 << 3)
902 pub const mask: u32 = 1 << offset;
903 /// Read-only values (empty)
904 pub mod R {}
905 /// Write-only values (empty)
906 pub mod W {}
907 /// Read-write values
908 pub mod RW {
909
910 /// 0b0: No interrupt when FOVR bit is set
911 pub const Disabled: u32 = 0b0;
912
913 /// 0b1: Interrupt generated when FOVR bit is set
914 pub const Enabled: u32 = 0b1;
915 }
916 }
917
918 /// FFIE0
919 pub mod FFIE0 {
920 /// Offset (2 bits)
921 pub const offset: u32 = 2;
922 /// Mask (1 bit: 1 << 2)
923 pub const mask: u32 = 1 << offset;
924 /// Read-only values (empty)
925 pub mod R {}
926 /// Write-only values (empty)
927 pub mod W {}
928 pub use super::FFIE1::RW;
929 }
930
931 /// FMPIE0
932 pub mod FMPIE0 {
933 /// Offset (1 bits)
934 pub const offset: u32 = 1;
935 /// Mask (1 bit: 1 << 1)
936 pub const mask: u32 = 1 << offset;
937 /// Read-only values (empty)
938 pub mod R {}
939 /// Write-only values (empty)
940 pub mod W {}
941 /// Read-write values
942 pub mod RW {
943
944 /// 0b0: No interrupt generated when state of FMP\[1:0\] bits are not 00
945 pub const Disabled: u32 = 0b0;
946
947 /// 0b1: Interrupt generated when state of FMP\[1:0\] bits are not 00b
948 pub const Enabled: u32 = 0b1;
949 }
950 }
951
952 /// TMEIE
953 pub mod TMEIE {
954 /// Offset (0 bits)
955 pub const offset: u32 = 0;
956 /// Mask (1 bit: 1 << 0)
957 pub const mask: u32 = 1 << offset;
958 /// Read-only values (empty)
959 pub mod R {}
960 /// Write-only values (empty)
961 pub mod W {}
962 /// Read-write values
963 pub mod RW {
964
965 /// 0b0: No interrupt when RQCPx bit is set
966 pub const Disabled: u32 = 0b0;
967
968 /// 0b1: Interrupt generated when RQCPx bit is set
969 pub const Enabled: u32 = 0b1;
970 }
971 }
972}
973
974/// CAN_ESR
975pub mod ESR {
976
977 /// REC
978 pub mod REC {
979 /// Offset (24 bits)
980 pub const offset: u32 = 24;
981 /// Mask (8 bits: 0xff << 24)
982 pub const mask: u32 = 0xff << offset;
983 /// Read-only values (empty)
984 pub mod R {}
985 /// Write-only values (empty)
986 pub mod W {}
987 /// Read-write values (empty)
988 pub mod RW {}
989 }
990
991 /// TEC
992 pub mod TEC {
993 /// Offset (16 bits)
994 pub const offset: u32 = 16;
995 /// Mask (8 bits: 0xff << 16)
996 pub const mask: u32 = 0xff << offset;
997 /// Read-only values (empty)
998 pub mod R {}
999 /// Write-only values (empty)
1000 pub mod W {}
1001 /// Read-write values (empty)
1002 pub mod RW {}
1003 }
1004
1005 /// LEC
1006 pub mod LEC {
1007 /// Offset (4 bits)
1008 pub const offset: u32 = 4;
1009 /// Mask (3 bits: 0b111 << 4)
1010 pub const mask: u32 = 0b111 << offset;
1011 /// Read-only values (empty)
1012 pub mod R {}
1013 /// Write-only values (empty)
1014 pub mod W {}
1015 /// Read-write values
1016 pub mod RW {
1017
1018 /// 0b000: No Error
1019 pub const NoError: u32 = 0b000;
1020
1021 /// 0b001: Stuff Error
1022 pub const Stuff: u32 = 0b001;
1023
1024 /// 0b010: Form Error
1025 pub const Form: u32 = 0b010;
1026
1027 /// 0b011: Acknowledgment Error
1028 pub const Ack: u32 = 0b011;
1029
1030 /// 0b100: Bit recessive Error
1031 pub const BitRecessive: u32 = 0b100;
1032
1033 /// 0b101: Bit dominant Error
1034 pub const BitDominant: u32 = 0b101;
1035
1036 /// 0b110: CRC Error
1037 pub const Crc: u32 = 0b110;
1038
1039 /// 0b111: Set by software
1040 pub const Custom: u32 = 0b111;
1041 }
1042 }
1043
1044 /// BOFF
1045 pub mod BOFF {
1046 /// Offset (2 bits)
1047 pub const offset: u32 = 2;
1048 /// Mask (1 bit: 1 << 2)
1049 pub const mask: u32 = 1 << offset;
1050 /// Read-only values (empty)
1051 pub mod R {}
1052 /// Write-only values (empty)
1053 pub mod W {}
1054 /// Read-write values (empty)
1055 pub mod RW {}
1056 }
1057
1058 /// EPVF
1059 pub mod EPVF {
1060 /// Offset (1 bits)
1061 pub const offset: u32 = 1;
1062 /// Mask (1 bit: 1 << 1)
1063 pub const mask: u32 = 1 << offset;
1064 /// Read-only values (empty)
1065 pub mod R {}
1066 /// Write-only values (empty)
1067 pub mod W {}
1068 /// Read-write values (empty)
1069 pub mod RW {}
1070 }
1071
1072 /// EWGF
1073 pub mod EWGF {
1074 /// Offset (0 bits)
1075 pub const offset: u32 = 0;
1076 /// Mask (1 bit: 1 << 0)
1077 pub const mask: u32 = 1 << offset;
1078 /// Read-only values (empty)
1079 pub mod R {}
1080 /// Write-only values (empty)
1081 pub mod W {}
1082 /// Read-write values (empty)
1083 pub mod RW {}
1084 }
1085}
1086
1087/// CAN_BTR
1088pub mod BTR {
1089
1090 /// SILM
1091 pub mod SILM {
1092 /// Offset (31 bits)
1093 pub const offset: u32 = 31;
1094 /// Mask (1 bit: 1 << 31)
1095 pub const mask: u32 = 1 << offset;
1096 /// Read-only values (empty)
1097 pub mod R {}
1098 /// Write-only values (empty)
1099 pub mod W {}
1100 /// Read-write values
1101 pub mod RW {
1102
1103 /// 0b0: Normal operation
1104 pub const Normal: u32 = 0b0;
1105
1106 /// 0b1: Silent Mode
1107 pub const Silent: u32 = 0b1;
1108 }
1109 }
1110
1111 /// LBKM
1112 pub mod LBKM {
1113 /// Offset (30 bits)
1114 pub const offset: u32 = 30;
1115 /// Mask (1 bit: 1 << 30)
1116 pub const mask: u32 = 1 << offset;
1117 /// Read-only values (empty)
1118 pub mod R {}
1119 /// Write-only values (empty)
1120 pub mod W {}
1121 /// Read-write values
1122 pub mod RW {
1123
1124 /// 0b0: Loop Back Mode disabled
1125 pub const Disabled: u32 = 0b0;
1126
1127 /// 0b1: Loop Back Mode enabled
1128 pub const Enabled: u32 = 0b1;
1129 }
1130 }
1131
1132 /// SJW
1133 pub mod SJW {
1134 /// Offset (24 bits)
1135 pub const offset: u32 = 24;
1136 /// Mask (2 bits: 0b11 << 24)
1137 pub const mask: u32 = 0b11 << offset;
1138 /// Read-only values (empty)
1139 pub mod R {}
1140 /// Write-only values (empty)
1141 pub mod W {}
1142 /// Read-write values (empty)
1143 pub mod RW {}
1144 }
1145
1146 /// TS2
1147 pub mod TS2 {
1148 /// Offset (20 bits)
1149 pub const offset: u32 = 20;
1150 /// Mask (3 bits: 0b111 << 20)
1151 pub const mask: u32 = 0b111 << offset;
1152 /// Read-only values (empty)
1153 pub mod R {}
1154 /// Write-only values (empty)
1155 pub mod W {}
1156 /// Read-write values (empty)
1157 pub mod RW {}
1158 }
1159
1160 /// TS1
1161 pub mod TS1 {
1162 /// Offset (16 bits)
1163 pub const offset: u32 = 16;
1164 /// Mask (4 bits: 0b1111 << 16)
1165 pub const mask: u32 = 0b1111 << offset;
1166 /// Read-only values (empty)
1167 pub mod R {}
1168 /// Write-only values (empty)
1169 pub mod W {}
1170 /// Read-write values (empty)
1171 pub mod RW {}
1172 }
1173
1174 /// BRP
1175 pub mod BRP {
1176 /// Offset (0 bits)
1177 pub const offset: u32 = 0;
1178 /// Mask (10 bits: 0x3ff << 0)
1179 pub const mask: u32 = 0x3ff << offset;
1180 /// Read-only values (empty)
1181 pub mod R {}
1182 /// Write-only values (empty)
1183 pub mod W {}
1184 /// Read-write values (empty)
1185 pub mod RW {}
1186 }
1187}
1188
1189/// CAN_FMR
1190pub mod FMR {
1191
1192 /// CAN2SB
1193 pub mod CAN2SB {
1194 /// Offset (8 bits)
1195 pub const offset: u32 = 8;
1196 /// Mask (6 bits: 0x3f << 8)
1197 pub const mask: u32 = 0x3f << offset;
1198 /// Read-only values (empty)
1199 pub mod R {}
1200 /// Write-only values (empty)
1201 pub mod W {}
1202 /// Read-write values (empty)
1203 pub mod RW {}
1204 }
1205
1206 /// FINIT
1207 pub mod FINIT {
1208 /// Offset (0 bits)
1209 pub const offset: u32 = 0;
1210 /// Mask (1 bit: 1 << 0)
1211 pub const mask: u32 = 1 << offset;
1212 /// Read-only values (empty)
1213 pub mod R {}
1214 /// Write-only values (empty)
1215 pub mod W {}
1216 /// Read-write values (empty)
1217 pub mod RW {}
1218 }
1219}
1220
1221/// CAN_FM1R
1222pub mod FM1R {
1223
1224 /// Filter mode
1225 pub mod FBM0 {
1226 /// Offset (0 bits)
1227 pub const offset: u32 = 0;
1228 /// Mask (1 bit: 1 << 0)
1229 pub const mask: u32 = 1 << offset;
1230 /// Read-only values (empty)
1231 pub mod R {}
1232 /// Write-only values (empty)
1233 pub mod W {}
1234 /// Read-write values (empty)
1235 pub mod RW {}
1236 }
1237
1238 /// Filter mode
1239 pub mod FBM1 {
1240 /// Offset (1 bits)
1241 pub const offset: u32 = 1;
1242 /// Mask (1 bit: 1 << 1)
1243 pub const mask: u32 = 1 << offset;
1244 /// Read-only values (empty)
1245 pub mod R {}
1246 /// Write-only values (empty)
1247 pub mod W {}
1248 /// Read-write values (empty)
1249 pub mod RW {}
1250 }
1251
1252 /// Filter mode
1253 pub mod FBM2 {
1254 /// Offset (2 bits)
1255 pub const offset: u32 = 2;
1256 /// Mask (1 bit: 1 << 2)
1257 pub const mask: u32 = 1 << offset;
1258 /// Read-only values (empty)
1259 pub mod R {}
1260 /// Write-only values (empty)
1261 pub mod W {}
1262 /// Read-write values (empty)
1263 pub mod RW {}
1264 }
1265
1266 /// Filter mode
1267 pub mod FBM3 {
1268 /// Offset (3 bits)
1269 pub const offset: u32 = 3;
1270 /// Mask (1 bit: 1 << 3)
1271 pub const mask: u32 = 1 << offset;
1272 /// Read-only values (empty)
1273 pub mod R {}
1274 /// Write-only values (empty)
1275 pub mod W {}
1276 /// Read-write values (empty)
1277 pub mod RW {}
1278 }
1279
1280 /// Filter mode
1281 pub mod FBM4 {
1282 /// Offset (4 bits)
1283 pub const offset: u32 = 4;
1284 /// Mask (1 bit: 1 << 4)
1285 pub const mask: u32 = 1 << offset;
1286 /// Read-only values (empty)
1287 pub mod R {}
1288 /// Write-only values (empty)
1289 pub mod W {}
1290 /// Read-write values (empty)
1291 pub mod RW {}
1292 }
1293
1294 /// Filter mode
1295 pub mod FBM5 {
1296 /// Offset (5 bits)
1297 pub const offset: u32 = 5;
1298 /// Mask (1 bit: 1 << 5)
1299 pub const mask: u32 = 1 << offset;
1300 /// Read-only values (empty)
1301 pub mod R {}
1302 /// Write-only values (empty)
1303 pub mod W {}
1304 /// Read-write values (empty)
1305 pub mod RW {}
1306 }
1307
1308 /// Filter mode
1309 pub mod FBM6 {
1310 /// Offset (6 bits)
1311 pub const offset: u32 = 6;
1312 /// Mask (1 bit: 1 << 6)
1313 pub const mask: u32 = 1 << offset;
1314 /// Read-only values (empty)
1315 pub mod R {}
1316 /// Write-only values (empty)
1317 pub mod W {}
1318 /// Read-write values (empty)
1319 pub mod RW {}
1320 }
1321
1322 /// Filter mode
1323 pub mod FBM7 {
1324 /// Offset (7 bits)
1325 pub const offset: u32 = 7;
1326 /// Mask (1 bit: 1 << 7)
1327 pub const mask: u32 = 1 << offset;
1328 /// Read-only values (empty)
1329 pub mod R {}
1330 /// Write-only values (empty)
1331 pub mod W {}
1332 /// Read-write values (empty)
1333 pub mod RW {}
1334 }
1335
1336 /// Filter mode
1337 pub mod FBM8 {
1338 /// Offset (8 bits)
1339 pub const offset: u32 = 8;
1340 /// Mask (1 bit: 1 << 8)
1341 pub const mask: u32 = 1 << offset;
1342 /// Read-only values (empty)
1343 pub mod R {}
1344 /// Write-only values (empty)
1345 pub mod W {}
1346 /// Read-write values (empty)
1347 pub mod RW {}
1348 }
1349
1350 /// Filter mode
1351 pub mod FBM9 {
1352 /// Offset (9 bits)
1353 pub const offset: u32 = 9;
1354 /// Mask (1 bit: 1 << 9)
1355 pub const mask: u32 = 1 << offset;
1356 /// Read-only values (empty)
1357 pub mod R {}
1358 /// Write-only values (empty)
1359 pub mod W {}
1360 /// Read-write values (empty)
1361 pub mod RW {}
1362 }
1363
1364 /// Filter mode
1365 pub mod FBM10 {
1366 /// Offset (10 bits)
1367 pub const offset: u32 = 10;
1368 /// Mask (1 bit: 1 << 10)
1369 pub const mask: u32 = 1 << offset;
1370 /// Read-only values (empty)
1371 pub mod R {}
1372 /// Write-only values (empty)
1373 pub mod W {}
1374 /// Read-write values (empty)
1375 pub mod RW {}
1376 }
1377
1378 /// Filter mode
1379 pub mod FBM11 {
1380 /// Offset (11 bits)
1381 pub const offset: u32 = 11;
1382 /// Mask (1 bit: 1 << 11)
1383 pub const mask: u32 = 1 << offset;
1384 /// Read-only values (empty)
1385 pub mod R {}
1386 /// Write-only values (empty)
1387 pub mod W {}
1388 /// Read-write values (empty)
1389 pub mod RW {}
1390 }
1391
1392 /// Filter mode
1393 pub mod FBM12 {
1394 /// Offset (12 bits)
1395 pub const offset: u32 = 12;
1396 /// Mask (1 bit: 1 << 12)
1397 pub const mask: u32 = 1 << offset;
1398 /// Read-only values (empty)
1399 pub mod R {}
1400 /// Write-only values (empty)
1401 pub mod W {}
1402 /// Read-write values (empty)
1403 pub mod RW {}
1404 }
1405
1406 /// Filter mode
1407 pub mod FBM13 {
1408 /// Offset (13 bits)
1409 pub const offset: u32 = 13;
1410 /// Mask (1 bit: 1 << 13)
1411 pub const mask: u32 = 1 << offset;
1412 /// Read-only values (empty)
1413 pub mod R {}
1414 /// Write-only values (empty)
1415 pub mod W {}
1416 /// Read-write values (empty)
1417 pub mod RW {}
1418 }
1419
1420 /// Filter mode
1421 pub mod FBM14 {
1422 /// Offset (14 bits)
1423 pub const offset: u32 = 14;
1424 /// Mask (1 bit: 1 << 14)
1425 pub const mask: u32 = 1 << offset;
1426 /// Read-only values (empty)
1427 pub mod R {}
1428 /// Write-only values (empty)
1429 pub mod W {}
1430 /// Read-write values (empty)
1431 pub mod RW {}
1432 }
1433
1434 /// Filter mode
1435 pub mod FBM15 {
1436 /// Offset (15 bits)
1437 pub const offset: u32 = 15;
1438 /// Mask (1 bit: 1 << 15)
1439 pub const mask: u32 = 1 << offset;
1440 /// Read-only values (empty)
1441 pub mod R {}
1442 /// Write-only values (empty)
1443 pub mod W {}
1444 /// Read-write values (empty)
1445 pub mod RW {}
1446 }
1447
1448 /// Filter mode
1449 pub mod FBM16 {
1450 /// Offset (16 bits)
1451 pub const offset: u32 = 16;
1452 /// Mask (1 bit: 1 << 16)
1453 pub const mask: u32 = 1 << offset;
1454 /// Read-only values (empty)
1455 pub mod R {}
1456 /// Write-only values (empty)
1457 pub mod W {}
1458 /// Read-write values (empty)
1459 pub mod RW {}
1460 }
1461
1462 /// Filter mode
1463 pub mod FBM17 {
1464 /// Offset (17 bits)
1465 pub const offset: u32 = 17;
1466 /// Mask (1 bit: 1 << 17)
1467 pub const mask: u32 = 1 << offset;
1468 /// Read-only values (empty)
1469 pub mod R {}
1470 /// Write-only values (empty)
1471 pub mod W {}
1472 /// Read-write values (empty)
1473 pub mod RW {}
1474 }
1475
1476 /// Filter mode
1477 pub mod FBM18 {
1478 /// Offset (18 bits)
1479 pub const offset: u32 = 18;
1480 /// Mask (1 bit: 1 << 18)
1481 pub const mask: u32 = 1 << offset;
1482 /// Read-only values (empty)
1483 pub mod R {}
1484 /// Write-only values (empty)
1485 pub mod W {}
1486 /// Read-write values (empty)
1487 pub mod RW {}
1488 }
1489
1490 /// Filter mode
1491 pub mod FBM19 {
1492 /// Offset (19 bits)
1493 pub const offset: u32 = 19;
1494 /// Mask (1 bit: 1 << 19)
1495 pub const mask: u32 = 1 << offset;
1496 /// Read-only values (empty)
1497 pub mod R {}
1498 /// Write-only values (empty)
1499 pub mod W {}
1500 /// Read-write values (empty)
1501 pub mod RW {}
1502 }
1503
1504 /// Filter mode
1505 pub mod FBM20 {
1506 /// Offset (20 bits)
1507 pub const offset: u32 = 20;
1508 /// Mask (1 bit: 1 << 20)
1509 pub const mask: u32 = 1 << offset;
1510 /// Read-only values (empty)
1511 pub mod R {}
1512 /// Write-only values (empty)
1513 pub mod W {}
1514 /// Read-write values (empty)
1515 pub mod RW {}
1516 }
1517
1518 /// Filter mode
1519 pub mod FBM21 {
1520 /// Offset (21 bits)
1521 pub const offset: u32 = 21;
1522 /// Mask (1 bit: 1 << 21)
1523 pub const mask: u32 = 1 << offset;
1524 /// Read-only values (empty)
1525 pub mod R {}
1526 /// Write-only values (empty)
1527 pub mod W {}
1528 /// Read-write values (empty)
1529 pub mod RW {}
1530 }
1531
1532 /// Filter mode
1533 pub mod FBM22 {
1534 /// Offset (22 bits)
1535 pub const offset: u32 = 22;
1536 /// Mask (1 bit: 1 << 22)
1537 pub const mask: u32 = 1 << offset;
1538 /// Read-only values (empty)
1539 pub mod R {}
1540 /// Write-only values (empty)
1541 pub mod W {}
1542 /// Read-write values (empty)
1543 pub mod RW {}
1544 }
1545
1546 /// Filter mode
1547 pub mod FBM23 {
1548 /// Offset (23 bits)
1549 pub const offset: u32 = 23;
1550 /// Mask (1 bit: 1 << 23)
1551 pub const mask: u32 = 1 << offset;
1552 /// Read-only values (empty)
1553 pub mod R {}
1554 /// Write-only values (empty)
1555 pub mod W {}
1556 /// Read-write values (empty)
1557 pub mod RW {}
1558 }
1559
1560 /// Filter mode
1561 pub mod FBM24 {
1562 /// Offset (24 bits)
1563 pub const offset: u32 = 24;
1564 /// Mask (1 bit: 1 << 24)
1565 pub const mask: u32 = 1 << offset;
1566 /// Read-only values (empty)
1567 pub mod R {}
1568 /// Write-only values (empty)
1569 pub mod W {}
1570 /// Read-write values (empty)
1571 pub mod RW {}
1572 }
1573
1574 /// Filter mode
1575 pub mod FBM25 {
1576 /// Offset (25 bits)
1577 pub const offset: u32 = 25;
1578 /// Mask (1 bit: 1 << 25)
1579 pub const mask: u32 = 1 << offset;
1580 /// Read-only values (empty)
1581 pub mod R {}
1582 /// Write-only values (empty)
1583 pub mod W {}
1584 /// Read-write values (empty)
1585 pub mod RW {}
1586 }
1587
1588 /// Filter mode
1589 pub mod FBM26 {
1590 /// Offset (26 bits)
1591 pub const offset: u32 = 26;
1592 /// Mask (1 bit: 1 << 26)
1593 pub const mask: u32 = 1 << offset;
1594 /// Read-only values (empty)
1595 pub mod R {}
1596 /// Write-only values (empty)
1597 pub mod W {}
1598 /// Read-write values (empty)
1599 pub mod RW {}
1600 }
1601
1602 /// Filter mode
1603 pub mod FBM27 {
1604 /// Offset (27 bits)
1605 pub const offset: u32 = 27;
1606 /// Mask (1 bit: 1 << 27)
1607 pub const mask: u32 = 1 << offset;
1608 /// Read-only values (empty)
1609 pub mod R {}
1610 /// Write-only values (empty)
1611 pub mod W {}
1612 /// Read-write values (empty)
1613 pub mod RW {}
1614 }
1615}
1616
1617/// CAN_FS1R
1618pub mod FS1R {
1619
1620 /// Filter scale configuration
1621 pub mod FSC0 {
1622 /// Offset (0 bits)
1623 pub const offset: u32 = 0;
1624 /// Mask (1 bit: 1 << 0)
1625 pub const mask: u32 = 1 << offset;
1626 /// Read-only values (empty)
1627 pub mod R {}
1628 /// Write-only values (empty)
1629 pub mod W {}
1630 /// Read-write values (empty)
1631 pub mod RW {}
1632 }
1633
1634 /// Filter scale configuration
1635 pub mod FSC1 {
1636 /// Offset (1 bits)
1637 pub const offset: u32 = 1;
1638 /// Mask (1 bit: 1 << 1)
1639 pub const mask: u32 = 1 << offset;
1640 /// Read-only values (empty)
1641 pub mod R {}
1642 /// Write-only values (empty)
1643 pub mod W {}
1644 /// Read-write values (empty)
1645 pub mod RW {}
1646 }
1647
1648 /// Filter scale configuration
1649 pub mod FSC2 {
1650 /// Offset (2 bits)
1651 pub const offset: u32 = 2;
1652 /// Mask (1 bit: 1 << 2)
1653 pub const mask: u32 = 1 << offset;
1654 /// Read-only values (empty)
1655 pub mod R {}
1656 /// Write-only values (empty)
1657 pub mod W {}
1658 /// Read-write values (empty)
1659 pub mod RW {}
1660 }
1661
1662 /// Filter scale configuration
1663 pub mod FSC3 {
1664 /// Offset (3 bits)
1665 pub const offset: u32 = 3;
1666 /// Mask (1 bit: 1 << 3)
1667 pub const mask: u32 = 1 << offset;
1668 /// Read-only values (empty)
1669 pub mod R {}
1670 /// Write-only values (empty)
1671 pub mod W {}
1672 /// Read-write values (empty)
1673 pub mod RW {}
1674 }
1675
1676 /// Filter scale configuration
1677 pub mod FSC4 {
1678 /// Offset (4 bits)
1679 pub const offset: u32 = 4;
1680 /// Mask (1 bit: 1 << 4)
1681 pub const mask: u32 = 1 << offset;
1682 /// Read-only values (empty)
1683 pub mod R {}
1684 /// Write-only values (empty)
1685 pub mod W {}
1686 /// Read-write values (empty)
1687 pub mod RW {}
1688 }
1689
1690 /// Filter scale configuration
1691 pub mod FSC5 {
1692 /// Offset (5 bits)
1693 pub const offset: u32 = 5;
1694 /// Mask (1 bit: 1 << 5)
1695 pub const mask: u32 = 1 << offset;
1696 /// Read-only values (empty)
1697 pub mod R {}
1698 /// Write-only values (empty)
1699 pub mod W {}
1700 /// Read-write values (empty)
1701 pub mod RW {}
1702 }
1703
1704 /// Filter scale configuration
1705 pub mod FSC6 {
1706 /// Offset (6 bits)
1707 pub const offset: u32 = 6;
1708 /// Mask (1 bit: 1 << 6)
1709 pub const mask: u32 = 1 << offset;
1710 /// Read-only values (empty)
1711 pub mod R {}
1712 /// Write-only values (empty)
1713 pub mod W {}
1714 /// Read-write values (empty)
1715 pub mod RW {}
1716 }
1717
1718 /// Filter scale configuration
1719 pub mod FSC7 {
1720 /// Offset (7 bits)
1721 pub const offset: u32 = 7;
1722 /// Mask (1 bit: 1 << 7)
1723 pub const mask: u32 = 1 << offset;
1724 /// Read-only values (empty)
1725 pub mod R {}
1726 /// Write-only values (empty)
1727 pub mod W {}
1728 /// Read-write values (empty)
1729 pub mod RW {}
1730 }
1731
1732 /// Filter scale configuration
1733 pub mod FSC8 {
1734 /// Offset (8 bits)
1735 pub const offset: u32 = 8;
1736 /// Mask (1 bit: 1 << 8)
1737 pub const mask: u32 = 1 << offset;
1738 /// Read-only values (empty)
1739 pub mod R {}
1740 /// Write-only values (empty)
1741 pub mod W {}
1742 /// Read-write values (empty)
1743 pub mod RW {}
1744 }
1745
1746 /// Filter scale configuration
1747 pub mod FSC9 {
1748 /// Offset (9 bits)
1749 pub const offset: u32 = 9;
1750 /// Mask (1 bit: 1 << 9)
1751 pub const mask: u32 = 1 << offset;
1752 /// Read-only values (empty)
1753 pub mod R {}
1754 /// Write-only values (empty)
1755 pub mod W {}
1756 /// Read-write values (empty)
1757 pub mod RW {}
1758 }
1759
1760 /// Filter scale configuration
1761 pub mod FSC10 {
1762 /// Offset (10 bits)
1763 pub const offset: u32 = 10;
1764 /// Mask (1 bit: 1 << 10)
1765 pub const mask: u32 = 1 << offset;
1766 /// Read-only values (empty)
1767 pub mod R {}
1768 /// Write-only values (empty)
1769 pub mod W {}
1770 /// Read-write values (empty)
1771 pub mod RW {}
1772 }
1773
1774 /// Filter scale configuration
1775 pub mod FSC11 {
1776 /// Offset (11 bits)
1777 pub const offset: u32 = 11;
1778 /// Mask (1 bit: 1 << 11)
1779 pub const mask: u32 = 1 << offset;
1780 /// Read-only values (empty)
1781 pub mod R {}
1782 /// Write-only values (empty)
1783 pub mod W {}
1784 /// Read-write values (empty)
1785 pub mod RW {}
1786 }
1787
1788 /// Filter scale configuration
1789 pub mod FSC12 {
1790 /// Offset (12 bits)
1791 pub const offset: u32 = 12;
1792 /// Mask (1 bit: 1 << 12)
1793 pub const mask: u32 = 1 << offset;
1794 /// Read-only values (empty)
1795 pub mod R {}
1796 /// Write-only values (empty)
1797 pub mod W {}
1798 /// Read-write values (empty)
1799 pub mod RW {}
1800 }
1801
1802 /// Filter scale configuration
1803 pub mod FSC13 {
1804 /// Offset (13 bits)
1805 pub const offset: u32 = 13;
1806 /// Mask (1 bit: 1 << 13)
1807 pub const mask: u32 = 1 << offset;
1808 /// Read-only values (empty)
1809 pub mod R {}
1810 /// Write-only values (empty)
1811 pub mod W {}
1812 /// Read-write values (empty)
1813 pub mod RW {}
1814 }
1815
1816 /// Filter scale configuration
1817 pub mod FSC14 {
1818 /// Offset (14 bits)
1819 pub const offset: u32 = 14;
1820 /// Mask (1 bit: 1 << 14)
1821 pub const mask: u32 = 1 << offset;
1822 /// Read-only values (empty)
1823 pub mod R {}
1824 /// Write-only values (empty)
1825 pub mod W {}
1826 /// Read-write values (empty)
1827 pub mod RW {}
1828 }
1829
1830 /// Filter scale configuration
1831 pub mod FSC15 {
1832 /// Offset (15 bits)
1833 pub const offset: u32 = 15;
1834 /// Mask (1 bit: 1 << 15)
1835 pub const mask: u32 = 1 << offset;
1836 /// Read-only values (empty)
1837 pub mod R {}
1838 /// Write-only values (empty)
1839 pub mod W {}
1840 /// Read-write values (empty)
1841 pub mod RW {}
1842 }
1843
1844 /// Filter scale configuration
1845 pub mod FSC16 {
1846 /// Offset (16 bits)
1847 pub const offset: u32 = 16;
1848 /// Mask (1 bit: 1 << 16)
1849 pub const mask: u32 = 1 << offset;
1850 /// Read-only values (empty)
1851 pub mod R {}
1852 /// Write-only values (empty)
1853 pub mod W {}
1854 /// Read-write values (empty)
1855 pub mod RW {}
1856 }
1857
1858 /// Filter scale configuration
1859 pub mod FSC17 {
1860 /// Offset (17 bits)
1861 pub const offset: u32 = 17;
1862 /// Mask (1 bit: 1 << 17)
1863 pub const mask: u32 = 1 << offset;
1864 /// Read-only values (empty)
1865 pub mod R {}
1866 /// Write-only values (empty)
1867 pub mod W {}
1868 /// Read-write values (empty)
1869 pub mod RW {}
1870 }
1871
1872 /// Filter scale configuration
1873 pub mod FSC18 {
1874 /// Offset (18 bits)
1875 pub const offset: u32 = 18;
1876 /// Mask (1 bit: 1 << 18)
1877 pub const mask: u32 = 1 << offset;
1878 /// Read-only values (empty)
1879 pub mod R {}
1880 /// Write-only values (empty)
1881 pub mod W {}
1882 /// Read-write values (empty)
1883 pub mod RW {}
1884 }
1885
1886 /// Filter scale configuration
1887 pub mod FSC19 {
1888 /// Offset (19 bits)
1889 pub const offset: u32 = 19;
1890 /// Mask (1 bit: 1 << 19)
1891 pub const mask: u32 = 1 << offset;
1892 /// Read-only values (empty)
1893 pub mod R {}
1894 /// Write-only values (empty)
1895 pub mod W {}
1896 /// Read-write values (empty)
1897 pub mod RW {}
1898 }
1899
1900 /// Filter scale configuration
1901 pub mod FSC20 {
1902 /// Offset (20 bits)
1903 pub const offset: u32 = 20;
1904 /// Mask (1 bit: 1 << 20)
1905 pub const mask: u32 = 1 << offset;
1906 /// Read-only values (empty)
1907 pub mod R {}
1908 /// Write-only values (empty)
1909 pub mod W {}
1910 /// Read-write values (empty)
1911 pub mod RW {}
1912 }
1913
1914 /// Filter scale configuration
1915 pub mod FSC21 {
1916 /// Offset (21 bits)
1917 pub const offset: u32 = 21;
1918 /// Mask (1 bit: 1 << 21)
1919 pub const mask: u32 = 1 << offset;
1920 /// Read-only values (empty)
1921 pub mod R {}
1922 /// Write-only values (empty)
1923 pub mod W {}
1924 /// Read-write values (empty)
1925 pub mod RW {}
1926 }
1927
1928 /// Filter scale configuration
1929 pub mod FSC22 {
1930 /// Offset (22 bits)
1931 pub const offset: u32 = 22;
1932 /// Mask (1 bit: 1 << 22)
1933 pub const mask: u32 = 1 << offset;
1934 /// Read-only values (empty)
1935 pub mod R {}
1936 /// Write-only values (empty)
1937 pub mod W {}
1938 /// Read-write values (empty)
1939 pub mod RW {}
1940 }
1941
1942 /// Filter scale configuration
1943 pub mod FSC23 {
1944 /// Offset (23 bits)
1945 pub const offset: u32 = 23;
1946 /// Mask (1 bit: 1 << 23)
1947 pub const mask: u32 = 1 << offset;
1948 /// Read-only values (empty)
1949 pub mod R {}
1950 /// Write-only values (empty)
1951 pub mod W {}
1952 /// Read-write values (empty)
1953 pub mod RW {}
1954 }
1955
1956 /// Filter scale configuration
1957 pub mod FSC24 {
1958 /// Offset (24 bits)
1959 pub const offset: u32 = 24;
1960 /// Mask (1 bit: 1 << 24)
1961 pub const mask: u32 = 1 << offset;
1962 /// Read-only values (empty)
1963 pub mod R {}
1964 /// Write-only values (empty)
1965 pub mod W {}
1966 /// Read-write values (empty)
1967 pub mod RW {}
1968 }
1969
1970 /// Filter scale configuration
1971 pub mod FSC25 {
1972 /// Offset (25 bits)
1973 pub const offset: u32 = 25;
1974 /// Mask (1 bit: 1 << 25)
1975 pub const mask: u32 = 1 << offset;
1976 /// Read-only values (empty)
1977 pub mod R {}
1978 /// Write-only values (empty)
1979 pub mod W {}
1980 /// Read-write values (empty)
1981 pub mod RW {}
1982 }
1983
1984 /// Filter scale configuration
1985 pub mod FSC26 {
1986 /// Offset (26 bits)
1987 pub const offset: u32 = 26;
1988 /// Mask (1 bit: 1 << 26)
1989 pub const mask: u32 = 1 << offset;
1990 /// Read-only values (empty)
1991 pub mod R {}
1992 /// Write-only values (empty)
1993 pub mod W {}
1994 /// Read-write values (empty)
1995 pub mod RW {}
1996 }
1997
1998 /// Filter scale configuration
1999 pub mod FSC27 {
2000 /// Offset (27 bits)
2001 pub const offset: u32 = 27;
2002 /// Mask (1 bit: 1 << 27)
2003 pub const mask: u32 = 1 << offset;
2004 /// Read-only values (empty)
2005 pub mod R {}
2006 /// Write-only values (empty)
2007 pub mod W {}
2008 /// Read-write values (empty)
2009 pub mod RW {}
2010 }
2011}
2012
2013/// CAN_FFA1R
2014pub mod FFA1R {
2015
2016 /// Filter FIFO assignment for filter 0
2017 pub mod FFA0 {
2018 /// Offset (0 bits)
2019 pub const offset: u32 = 0;
2020 /// Mask (1 bit: 1 << 0)
2021 pub const mask: u32 = 1 << offset;
2022 /// Read-only values (empty)
2023 pub mod R {}
2024 /// Write-only values (empty)
2025 pub mod W {}
2026 /// Read-write values (empty)
2027 pub mod RW {}
2028 }
2029
2030 /// Filter FIFO assignment for filter 1
2031 pub mod FFA1 {
2032 /// Offset (1 bits)
2033 pub const offset: u32 = 1;
2034 /// Mask (1 bit: 1 << 1)
2035 pub const mask: u32 = 1 << offset;
2036 /// Read-only values (empty)
2037 pub mod R {}
2038 /// Write-only values (empty)
2039 pub mod W {}
2040 /// Read-write values (empty)
2041 pub mod RW {}
2042 }
2043
2044 /// Filter FIFO assignment for filter 2
2045 pub mod FFA2 {
2046 /// Offset (2 bits)
2047 pub const offset: u32 = 2;
2048 /// Mask (1 bit: 1 << 2)
2049 pub const mask: u32 = 1 << offset;
2050 /// Read-only values (empty)
2051 pub mod R {}
2052 /// Write-only values (empty)
2053 pub mod W {}
2054 /// Read-write values (empty)
2055 pub mod RW {}
2056 }
2057
2058 /// Filter FIFO assignment for filter 3
2059 pub mod FFA3 {
2060 /// Offset (3 bits)
2061 pub const offset: u32 = 3;
2062 /// Mask (1 bit: 1 << 3)
2063 pub const mask: u32 = 1 << offset;
2064 /// Read-only values (empty)
2065 pub mod R {}
2066 /// Write-only values (empty)
2067 pub mod W {}
2068 /// Read-write values (empty)
2069 pub mod RW {}
2070 }
2071
2072 /// Filter FIFO assignment for filter 4
2073 pub mod FFA4 {
2074 /// Offset (4 bits)
2075 pub const offset: u32 = 4;
2076 /// Mask (1 bit: 1 << 4)
2077 pub const mask: u32 = 1 << offset;
2078 /// Read-only values (empty)
2079 pub mod R {}
2080 /// Write-only values (empty)
2081 pub mod W {}
2082 /// Read-write values (empty)
2083 pub mod RW {}
2084 }
2085
2086 /// Filter FIFO assignment for filter 5
2087 pub mod FFA5 {
2088 /// Offset (5 bits)
2089 pub const offset: u32 = 5;
2090 /// Mask (1 bit: 1 << 5)
2091 pub const mask: u32 = 1 << offset;
2092 /// Read-only values (empty)
2093 pub mod R {}
2094 /// Write-only values (empty)
2095 pub mod W {}
2096 /// Read-write values (empty)
2097 pub mod RW {}
2098 }
2099
2100 /// Filter FIFO assignment for filter 6
2101 pub mod FFA6 {
2102 /// Offset (6 bits)
2103 pub const offset: u32 = 6;
2104 /// Mask (1 bit: 1 << 6)
2105 pub const mask: u32 = 1 << offset;
2106 /// Read-only values (empty)
2107 pub mod R {}
2108 /// Write-only values (empty)
2109 pub mod W {}
2110 /// Read-write values (empty)
2111 pub mod RW {}
2112 }
2113
2114 /// Filter FIFO assignment for filter 7
2115 pub mod FFA7 {
2116 /// Offset (7 bits)
2117 pub const offset: u32 = 7;
2118 /// Mask (1 bit: 1 << 7)
2119 pub const mask: u32 = 1 << offset;
2120 /// Read-only values (empty)
2121 pub mod R {}
2122 /// Write-only values (empty)
2123 pub mod W {}
2124 /// Read-write values (empty)
2125 pub mod RW {}
2126 }
2127
2128 /// Filter FIFO assignment for filter 8
2129 pub mod FFA8 {
2130 /// Offset (8 bits)
2131 pub const offset: u32 = 8;
2132 /// Mask (1 bit: 1 << 8)
2133 pub const mask: u32 = 1 << offset;
2134 /// Read-only values (empty)
2135 pub mod R {}
2136 /// Write-only values (empty)
2137 pub mod W {}
2138 /// Read-write values (empty)
2139 pub mod RW {}
2140 }
2141
2142 /// Filter FIFO assignment for filter 9
2143 pub mod FFA9 {
2144 /// Offset (9 bits)
2145 pub const offset: u32 = 9;
2146 /// Mask (1 bit: 1 << 9)
2147 pub const mask: u32 = 1 << offset;
2148 /// Read-only values (empty)
2149 pub mod R {}
2150 /// Write-only values (empty)
2151 pub mod W {}
2152 /// Read-write values (empty)
2153 pub mod RW {}
2154 }
2155
2156 /// Filter FIFO assignment for filter 10
2157 pub mod FFA10 {
2158 /// Offset (10 bits)
2159 pub const offset: u32 = 10;
2160 /// Mask (1 bit: 1 << 10)
2161 pub const mask: u32 = 1 << offset;
2162 /// Read-only values (empty)
2163 pub mod R {}
2164 /// Write-only values (empty)
2165 pub mod W {}
2166 /// Read-write values (empty)
2167 pub mod RW {}
2168 }
2169
2170 /// Filter FIFO assignment for filter 11
2171 pub mod FFA11 {
2172 /// Offset (11 bits)
2173 pub const offset: u32 = 11;
2174 /// Mask (1 bit: 1 << 11)
2175 pub const mask: u32 = 1 << offset;
2176 /// Read-only values (empty)
2177 pub mod R {}
2178 /// Write-only values (empty)
2179 pub mod W {}
2180 /// Read-write values (empty)
2181 pub mod RW {}
2182 }
2183
2184 /// Filter FIFO assignment for filter 12
2185 pub mod FFA12 {
2186 /// Offset (12 bits)
2187 pub const offset: u32 = 12;
2188 /// Mask (1 bit: 1 << 12)
2189 pub const mask: u32 = 1 << offset;
2190 /// Read-only values (empty)
2191 pub mod R {}
2192 /// Write-only values (empty)
2193 pub mod W {}
2194 /// Read-write values (empty)
2195 pub mod RW {}
2196 }
2197
2198 /// Filter FIFO assignment for filter 13
2199 pub mod FFA13 {
2200 /// Offset (13 bits)
2201 pub const offset: u32 = 13;
2202 /// Mask (1 bit: 1 << 13)
2203 pub const mask: u32 = 1 << offset;
2204 /// Read-only values (empty)
2205 pub mod R {}
2206 /// Write-only values (empty)
2207 pub mod W {}
2208 /// Read-write values (empty)
2209 pub mod RW {}
2210 }
2211
2212 /// Filter FIFO assignment for filter 14
2213 pub mod FFA14 {
2214 /// Offset (14 bits)
2215 pub const offset: u32 = 14;
2216 /// Mask (1 bit: 1 << 14)
2217 pub const mask: u32 = 1 << offset;
2218 /// Read-only values (empty)
2219 pub mod R {}
2220 /// Write-only values (empty)
2221 pub mod W {}
2222 /// Read-write values (empty)
2223 pub mod RW {}
2224 }
2225
2226 /// Filter FIFO assignment for filter 15
2227 pub mod FFA15 {
2228 /// Offset (15 bits)
2229 pub const offset: u32 = 15;
2230 /// Mask (1 bit: 1 << 15)
2231 pub const mask: u32 = 1 << offset;
2232 /// Read-only values (empty)
2233 pub mod R {}
2234 /// Write-only values (empty)
2235 pub mod W {}
2236 /// Read-write values (empty)
2237 pub mod RW {}
2238 }
2239
2240 /// Filter FIFO assignment for filter 16
2241 pub mod FFA16 {
2242 /// Offset (16 bits)
2243 pub const offset: u32 = 16;
2244 /// Mask (1 bit: 1 << 16)
2245 pub const mask: u32 = 1 << offset;
2246 /// Read-only values (empty)
2247 pub mod R {}
2248 /// Write-only values (empty)
2249 pub mod W {}
2250 /// Read-write values (empty)
2251 pub mod RW {}
2252 }
2253
2254 /// Filter FIFO assignment for filter 17
2255 pub mod FFA17 {
2256 /// Offset (17 bits)
2257 pub const offset: u32 = 17;
2258 /// Mask (1 bit: 1 << 17)
2259 pub const mask: u32 = 1 << offset;
2260 /// Read-only values (empty)
2261 pub mod R {}
2262 /// Write-only values (empty)
2263 pub mod W {}
2264 /// Read-write values (empty)
2265 pub mod RW {}
2266 }
2267
2268 /// Filter FIFO assignment for filter 18
2269 pub mod FFA18 {
2270 /// Offset (18 bits)
2271 pub const offset: u32 = 18;
2272 /// Mask (1 bit: 1 << 18)
2273 pub const mask: u32 = 1 << offset;
2274 /// Read-only values (empty)
2275 pub mod R {}
2276 /// Write-only values (empty)
2277 pub mod W {}
2278 /// Read-write values (empty)
2279 pub mod RW {}
2280 }
2281
2282 /// Filter FIFO assignment for filter 19
2283 pub mod FFA19 {
2284 /// Offset (19 bits)
2285 pub const offset: u32 = 19;
2286 /// Mask (1 bit: 1 << 19)
2287 pub const mask: u32 = 1 << offset;
2288 /// Read-only values (empty)
2289 pub mod R {}
2290 /// Write-only values (empty)
2291 pub mod W {}
2292 /// Read-write values (empty)
2293 pub mod RW {}
2294 }
2295
2296 /// Filter FIFO assignment for filter 20
2297 pub mod FFA20 {
2298 /// Offset (20 bits)
2299 pub const offset: u32 = 20;
2300 /// Mask (1 bit: 1 << 20)
2301 pub const mask: u32 = 1 << offset;
2302 /// Read-only values (empty)
2303 pub mod R {}
2304 /// Write-only values (empty)
2305 pub mod W {}
2306 /// Read-write values (empty)
2307 pub mod RW {}
2308 }
2309
2310 /// Filter FIFO assignment for filter 21
2311 pub mod FFA21 {
2312 /// Offset (21 bits)
2313 pub const offset: u32 = 21;
2314 /// Mask (1 bit: 1 << 21)
2315 pub const mask: u32 = 1 << offset;
2316 /// Read-only values (empty)
2317 pub mod R {}
2318 /// Write-only values (empty)
2319 pub mod W {}
2320 /// Read-write values (empty)
2321 pub mod RW {}
2322 }
2323
2324 /// Filter FIFO assignment for filter 22
2325 pub mod FFA22 {
2326 /// Offset (22 bits)
2327 pub const offset: u32 = 22;
2328 /// Mask (1 bit: 1 << 22)
2329 pub const mask: u32 = 1 << offset;
2330 /// Read-only values (empty)
2331 pub mod R {}
2332 /// Write-only values (empty)
2333 pub mod W {}
2334 /// Read-write values (empty)
2335 pub mod RW {}
2336 }
2337
2338 /// Filter FIFO assignment for filter 23
2339 pub mod FFA23 {
2340 /// Offset (23 bits)
2341 pub const offset: u32 = 23;
2342 /// Mask (1 bit: 1 << 23)
2343 pub const mask: u32 = 1 << offset;
2344 /// Read-only values (empty)
2345 pub mod R {}
2346 /// Write-only values (empty)
2347 pub mod W {}
2348 /// Read-write values (empty)
2349 pub mod RW {}
2350 }
2351
2352 /// Filter FIFO assignment for filter 24
2353 pub mod FFA24 {
2354 /// Offset (24 bits)
2355 pub const offset: u32 = 24;
2356 /// Mask (1 bit: 1 << 24)
2357 pub const mask: u32 = 1 << offset;
2358 /// Read-only values (empty)
2359 pub mod R {}
2360 /// Write-only values (empty)
2361 pub mod W {}
2362 /// Read-write values (empty)
2363 pub mod RW {}
2364 }
2365
2366 /// Filter FIFO assignment for filter 25
2367 pub mod FFA25 {
2368 /// Offset (25 bits)
2369 pub const offset: u32 = 25;
2370 /// Mask (1 bit: 1 << 25)
2371 pub const mask: u32 = 1 << offset;
2372 /// Read-only values (empty)
2373 pub mod R {}
2374 /// Write-only values (empty)
2375 pub mod W {}
2376 /// Read-write values (empty)
2377 pub mod RW {}
2378 }
2379
2380 /// Filter FIFO assignment for filter 26
2381 pub mod FFA26 {
2382 /// Offset (26 bits)
2383 pub const offset: u32 = 26;
2384 /// Mask (1 bit: 1 << 26)
2385 pub const mask: u32 = 1 << offset;
2386 /// Read-only values (empty)
2387 pub mod R {}
2388 /// Write-only values (empty)
2389 pub mod W {}
2390 /// Read-write values (empty)
2391 pub mod RW {}
2392 }
2393
2394 /// Filter FIFO assignment for filter 27
2395 pub mod FFA27 {
2396 /// Offset (27 bits)
2397 pub const offset: u32 = 27;
2398 /// Mask (1 bit: 1 << 27)
2399 pub const mask: u32 = 1 << offset;
2400 /// Read-only values (empty)
2401 pub mod R {}
2402 /// Write-only values (empty)
2403 pub mod W {}
2404 /// Read-write values (empty)
2405 pub mod RW {}
2406 }
2407}
2408
2409/// CAN_FA1R
2410pub mod FA1R {
2411
2412 /// Filter active
2413 pub mod FACT0 {
2414 /// Offset (0 bits)
2415 pub const offset: u32 = 0;
2416 /// Mask (1 bit: 1 << 0)
2417 pub const mask: u32 = 1 << offset;
2418 /// Read-only values (empty)
2419 pub mod R {}
2420 /// Write-only values (empty)
2421 pub mod W {}
2422 /// Read-write values (empty)
2423 pub mod RW {}
2424 }
2425
2426 /// Filter active
2427 pub mod FACT1 {
2428 /// Offset (1 bits)
2429 pub const offset: u32 = 1;
2430 /// Mask (1 bit: 1 << 1)
2431 pub const mask: u32 = 1 << offset;
2432 /// Read-only values (empty)
2433 pub mod R {}
2434 /// Write-only values (empty)
2435 pub mod W {}
2436 /// Read-write values (empty)
2437 pub mod RW {}
2438 }
2439
2440 /// Filter active
2441 pub mod FACT2 {
2442 /// Offset (2 bits)
2443 pub const offset: u32 = 2;
2444 /// Mask (1 bit: 1 << 2)
2445 pub const mask: u32 = 1 << offset;
2446 /// Read-only values (empty)
2447 pub mod R {}
2448 /// Write-only values (empty)
2449 pub mod W {}
2450 /// Read-write values (empty)
2451 pub mod RW {}
2452 }
2453
2454 /// Filter active
2455 pub mod FACT3 {
2456 /// Offset (3 bits)
2457 pub const offset: u32 = 3;
2458 /// Mask (1 bit: 1 << 3)
2459 pub const mask: u32 = 1 << offset;
2460 /// Read-only values (empty)
2461 pub mod R {}
2462 /// Write-only values (empty)
2463 pub mod W {}
2464 /// Read-write values (empty)
2465 pub mod RW {}
2466 }
2467
2468 /// Filter active
2469 pub mod FACT4 {
2470 /// Offset (4 bits)
2471 pub const offset: u32 = 4;
2472 /// Mask (1 bit: 1 << 4)
2473 pub const mask: u32 = 1 << offset;
2474 /// Read-only values (empty)
2475 pub mod R {}
2476 /// Write-only values (empty)
2477 pub mod W {}
2478 /// Read-write values (empty)
2479 pub mod RW {}
2480 }
2481
2482 /// Filter active
2483 pub mod FACT5 {
2484 /// Offset (5 bits)
2485 pub const offset: u32 = 5;
2486 /// Mask (1 bit: 1 << 5)
2487 pub const mask: u32 = 1 << offset;
2488 /// Read-only values (empty)
2489 pub mod R {}
2490 /// Write-only values (empty)
2491 pub mod W {}
2492 /// Read-write values (empty)
2493 pub mod RW {}
2494 }
2495
2496 /// Filter active
2497 pub mod FACT6 {
2498 /// Offset (6 bits)
2499 pub const offset: u32 = 6;
2500 /// Mask (1 bit: 1 << 6)
2501 pub const mask: u32 = 1 << offset;
2502 /// Read-only values (empty)
2503 pub mod R {}
2504 /// Write-only values (empty)
2505 pub mod W {}
2506 /// Read-write values (empty)
2507 pub mod RW {}
2508 }
2509
2510 /// Filter active
2511 pub mod FACT7 {
2512 /// Offset (7 bits)
2513 pub const offset: u32 = 7;
2514 /// Mask (1 bit: 1 << 7)
2515 pub const mask: u32 = 1 << offset;
2516 /// Read-only values (empty)
2517 pub mod R {}
2518 /// Write-only values (empty)
2519 pub mod W {}
2520 /// Read-write values (empty)
2521 pub mod RW {}
2522 }
2523
2524 /// Filter active
2525 pub mod FACT8 {
2526 /// Offset (8 bits)
2527 pub const offset: u32 = 8;
2528 /// Mask (1 bit: 1 << 8)
2529 pub const mask: u32 = 1 << offset;
2530 /// Read-only values (empty)
2531 pub mod R {}
2532 /// Write-only values (empty)
2533 pub mod W {}
2534 /// Read-write values (empty)
2535 pub mod RW {}
2536 }
2537
2538 /// Filter active
2539 pub mod FACT9 {
2540 /// Offset (9 bits)
2541 pub const offset: u32 = 9;
2542 /// Mask (1 bit: 1 << 9)
2543 pub const mask: u32 = 1 << offset;
2544 /// Read-only values (empty)
2545 pub mod R {}
2546 /// Write-only values (empty)
2547 pub mod W {}
2548 /// Read-write values (empty)
2549 pub mod RW {}
2550 }
2551
2552 /// Filter active
2553 pub mod FACT10 {
2554 /// Offset (10 bits)
2555 pub const offset: u32 = 10;
2556 /// Mask (1 bit: 1 << 10)
2557 pub const mask: u32 = 1 << offset;
2558 /// Read-only values (empty)
2559 pub mod R {}
2560 /// Write-only values (empty)
2561 pub mod W {}
2562 /// Read-write values (empty)
2563 pub mod RW {}
2564 }
2565
2566 /// Filter active
2567 pub mod FACT11 {
2568 /// Offset (11 bits)
2569 pub const offset: u32 = 11;
2570 /// Mask (1 bit: 1 << 11)
2571 pub const mask: u32 = 1 << offset;
2572 /// Read-only values (empty)
2573 pub mod R {}
2574 /// Write-only values (empty)
2575 pub mod W {}
2576 /// Read-write values (empty)
2577 pub mod RW {}
2578 }
2579
2580 /// Filter active
2581 pub mod FACT12 {
2582 /// Offset (12 bits)
2583 pub const offset: u32 = 12;
2584 /// Mask (1 bit: 1 << 12)
2585 pub const mask: u32 = 1 << offset;
2586 /// Read-only values (empty)
2587 pub mod R {}
2588 /// Write-only values (empty)
2589 pub mod W {}
2590 /// Read-write values (empty)
2591 pub mod RW {}
2592 }
2593
2594 /// Filter active
2595 pub mod FACT13 {
2596 /// Offset (13 bits)
2597 pub const offset: u32 = 13;
2598 /// Mask (1 bit: 1 << 13)
2599 pub const mask: u32 = 1 << offset;
2600 /// Read-only values (empty)
2601 pub mod R {}
2602 /// Write-only values (empty)
2603 pub mod W {}
2604 /// Read-write values (empty)
2605 pub mod RW {}
2606 }
2607
2608 /// Filter active
2609 pub mod FACT14 {
2610 /// Offset (14 bits)
2611 pub const offset: u32 = 14;
2612 /// Mask (1 bit: 1 << 14)
2613 pub const mask: u32 = 1 << offset;
2614 /// Read-only values (empty)
2615 pub mod R {}
2616 /// Write-only values (empty)
2617 pub mod W {}
2618 /// Read-write values (empty)
2619 pub mod RW {}
2620 }
2621
2622 /// Filter active
2623 pub mod FACT15 {
2624 /// Offset (15 bits)
2625 pub const offset: u32 = 15;
2626 /// Mask (1 bit: 1 << 15)
2627 pub const mask: u32 = 1 << offset;
2628 /// Read-only values (empty)
2629 pub mod R {}
2630 /// Write-only values (empty)
2631 pub mod W {}
2632 /// Read-write values (empty)
2633 pub mod RW {}
2634 }
2635
2636 /// Filter active
2637 pub mod FACT16 {
2638 /// Offset (16 bits)
2639 pub const offset: u32 = 16;
2640 /// Mask (1 bit: 1 << 16)
2641 pub const mask: u32 = 1 << offset;
2642 /// Read-only values (empty)
2643 pub mod R {}
2644 /// Write-only values (empty)
2645 pub mod W {}
2646 /// Read-write values (empty)
2647 pub mod RW {}
2648 }
2649
2650 /// Filter active
2651 pub mod FACT17 {
2652 /// Offset (17 bits)
2653 pub const offset: u32 = 17;
2654 /// Mask (1 bit: 1 << 17)
2655 pub const mask: u32 = 1 << offset;
2656 /// Read-only values (empty)
2657 pub mod R {}
2658 /// Write-only values (empty)
2659 pub mod W {}
2660 /// Read-write values (empty)
2661 pub mod RW {}
2662 }
2663
2664 /// Filter active
2665 pub mod FACT18 {
2666 /// Offset (18 bits)
2667 pub const offset: u32 = 18;
2668 /// Mask (1 bit: 1 << 18)
2669 pub const mask: u32 = 1 << offset;
2670 /// Read-only values (empty)
2671 pub mod R {}
2672 /// Write-only values (empty)
2673 pub mod W {}
2674 /// Read-write values (empty)
2675 pub mod RW {}
2676 }
2677
2678 /// Filter active
2679 pub mod FACT19 {
2680 /// Offset (19 bits)
2681 pub const offset: u32 = 19;
2682 /// Mask (1 bit: 1 << 19)
2683 pub const mask: u32 = 1 << offset;
2684 /// Read-only values (empty)
2685 pub mod R {}
2686 /// Write-only values (empty)
2687 pub mod W {}
2688 /// Read-write values (empty)
2689 pub mod RW {}
2690 }
2691
2692 /// Filter active
2693 pub mod FACT20 {
2694 /// Offset (20 bits)
2695 pub const offset: u32 = 20;
2696 /// Mask (1 bit: 1 << 20)
2697 pub const mask: u32 = 1 << offset;
2698 /// Read-only values (empty)
2699 pub mod R {}
2700 /// Write-only values (empty)
2701 pub mod W {}
2702 /// Read-write values (empty)
2703 pub mod RW {}
2704 }
2705
2706 /// Filter active
2707 pub mod FACT21 {
2708 /// Offset (21 bits)
2709 pub const offset: u32 = 21;
2710 /// Mask (1 bit: 1 << 21)
2711 pub const mask: u32 = 1 << offset;
2712 /// Read-only values (empty)
2713 pub mod R {}
2714 /// Write-only values (empty)
2715 pub mod W {}
2716 /// Read-write values (empty)
2717 pub mod RW {}
2718 }
2719
2720 /// Filter active
2721 pub mod FACT22 {
2722 /// Offset (22 bits)
2723 pub const offset: u32 = 22;
2724 /// Mask (1 bit: 1 << 22)
2725 pub const mask: u32 = 1 << offset;
2726 /// Read-only values (empty)
2727 pub mod R {}
2728 /// Write-only values (empty)
2729 pub mod W {}
2730 /// Read-write values (empty)
2731 pub mod RW {}
2732 }
2733
2734 /// Filter active
2735 pub mod FACT23 {
2736 /// Offset (23 bits)
2737 pub const offset: u32 = 23;
2738 /// Mask (1 bit: 1 << 23)
2739 pub const mask: u32 = 1 << offset;
2740 /// Read-only values (empty)
2741 pub mod R {}
2742 /// Write-only values (empty)
2743 pub mod W {}
2744 /// Read-write values (empty)
2745 pub mod RW {}
2746 }
2747
2748 /// Filter active
2749 pub mod FACT24 {
2750 /// Offset (24 bits)
2751 pub const offset: u32 = 24;
2752 /// Mask (1 bit: 1 << 24)
2753 pub const mask: u32 = 1 << offset;
2754 /// Read-only values (empty)
2755 pub mod R {}
2756 /// Write-only values (empty)
2757 pub mod W {}
2758 /// Read-write values (empty)
2759 pub mod RW {}
2760 }
2761
2762 /// Filter active
2763 pub mod FACT25 {
2764 /// Offset (25 bits)
2765 pub const offset: u32 = 25;
2766 /// Mask (1 bit: 1 << 25)
2767 pub const mask: u32 = 1 << offset;
2768 /// Read-only values (empty)
2769 pub mod R {}
2770 /// Write-only values (empty)
2771 pub mod W {}
2772 /// Read-write values (empty)
2773 pub mod RW {}
2774 }
2775
2776 /// Filter active
2777 pub mod FACT26 {
2778 /// Offset (26 bits)
2779 pub const offset: u32 = 26;
2780 /// Mask (1 bit: 1 << 26)
2781 pub const mask: u32 = 1 << offset;
2782 /// Read-only values (empty)
2783 pub mod R {}
2784 /// Write-only values (empty)
2785 pub mod W {}
2786 /// Read-write values (empty)
2787 pub mod RW {}
2788 }
2789
2790 /// Filter active
2791 pub mod FACT27 {
2792 /// Offset (27 bits)
2793 pub const offset: u32 = 27;
2794 /// Mask (1 bit: 1 << 27)
2795 pub const mask: u32 = 1 << offset;
2796 /// Read-only values (empty)
2797 pub mod R {}
2798 /// Write-only values (empty)
2799 pub mod W {}
2800 /// Read-write values (empty)
2801 pub mod RW {}
2802 }
2803}
2804
2805/// CAN_TI0R
2806pub mod TIR0 {
2807
2808 /// STID
2809 pub mod STID {
2810 /// Offset (21 bits)
2811 pub const offset: u32 = 21;
2812 /// Mask (11 bits: 0x7ff << 21)
2813 pub const mask: u32 = 0x7ff << offset;
2814 /// Read-only values (empty)
2815 pub mod R {}
2816 /// Write-only values (empty)
2817 pub mod W {}
2818 /// Read-write values (empty)
2819 pub mod RW {}
2820 }
2821
2822 /// EXID
2823 pub mod EXID {
2824 /// Offset (3 bits)
2825 pub const offset: u32 = 3;
2826 /// Mask (18 bits: 0x3ffff << 3)
2827 pub const mask: u32 = 0x3ffff << offset;
2828 /// Read-only values (empty)
2829 pub mod R {}
2830 /// Write-only values (empty)
2831 pub mod W {}
2832 /// Read-write values (empty)
2833 pub mod RW {}
2834 }
2835
2836 /// IDE
2837 pub mod IDE {
2838 /// Offset (2 bits)
2839 pub const offset: u32 = 2;
2840 /// Mask (1 bit: 1 << 2)
2841 pub const mask: u32 = 1 << offset;
2842 /// Read-only values (empty)
2843 pub mod R {}
2844 /// Write-only values (empty)
2845 pub mod W {}
2846 /// Read-write values
2847 pub mod RW {
2848
2849 /// 0b0: Standard identifier
2850 pub const Standard: u32 = 0b0;
2851
2852 /// 0b1: Extended identifier
2853 pub const Extended: u32 = 0b1;
2854 }
2855 }
2856
2857 /// RTR
2858 pub mod RTR {
2859 /// Offset (1 bits)
2860 pub const offset: u32 = 1;
2861 /// Mask (1 bit: 1 << 1)
2862 pub const mask: u32 = 1 << offset;
2863 /// Read-only values (empty)
2864 pub mod R {}
2865 /// Write-only values (empty)
2866 pub mod W {}
2867 /// Read-write values
2868 pub mod RW {
2869
2870 /// 0b0: Data frame
2871 pub const Data: u32 = 0b0;
2872
2873 /// 0b1: Remote frame
2874 pub const Remote: u32 = 0b1;
2875 }
2876 }
2877
2878 /// TXRQ
2879 pub mod TXRQ {
2880 /// Offset (0 bits)
2881 pub const offset: u32 = 0;
2882 /// Mask (1 bit: 1 << 0)
2883 pub const mask: u32 = 1 << offset;
2884 /// Read-only values (empty)
2885 pub mod R {}
2886 /// Write-only values (empty)
2887 pub mod W {}
2888 /// Read-write values (empty)
2889 pub mod RW {}
2890 }
2891}
2892
2893/// CAN_TDT0R
2894pub mod TDTR0 {
2895
2896 /// TIME
2897 pub mod TIME {
2898 /// Offset (16 bits)
2899 pub const offset: u32 = 16;
2900 /// Mask (16 bits: 0xffff << 16)
2901 pub const mask: u32 = 0xffff << offset;
2902 /// Read-only values (empty)
2903 pub mod R {}
2904 /// Write-only values (empty)
2905 pub mod W {}
2906 /// Read-write values (empty)
2907 pub mod RW {}
2908 }
2909
2910 /// TGT
2911 pub mod TGT {
2912 /// Offset (8 bits)
2913 pub const offset: u32 = 8;
2914 /// Mask (1 bit: 1 << 8)
2915 pub const mask: u32 = 1 << offset;
2916 /// Read-only values (empty)
2917 pub mod R {}
2918 /// Write-only values (empty)
2919 pub mod W {}
2920 /// Read-write values (empty)
2921 pub mod RW {}
2922 }
2923
2924 /// DLC
2925 pub mod DLC {
2926 /// Offset (0 bits)
2927 pub const offset: u32 = 0;
2928 /// Mask (4 bits: 0b1111 << 0)
2929 pub const mask: u32 = 0b1111 << offset;
2930 /// Read-only values (empty)
2931 pub mod R {}
2932 /// Write-only values (empty)
2933 pub mod W {}
2934 /// Read-write values (empty)
2935 pub mod RW {}
2936 }
2937}
2938
2939/// CAN_TDL0R
2940pub mod TDLR0 {
2941
2942 /// DATA3
2943 pub mod DATA3 {
2944 /// Offset (24 bits)
2945 pub const offset: u32 = 24;
2946 /// Mask (8 bits: 0xff << 24)
2947 pub const mask: u32 = 0xff << offset;
2948 /// Read-only values (empty)
2949 pub mod R {}
2950 /// Write-only values (empty)
2951 pub mod W {}
2952 /// Read-write values (empty)
2953 pub mod RW {}
2954 }
2955
2956 /// DATA2
2957 pub mod DATA2 {
2958 /// Offset (16 bits)
2959 pub const offset: u32 = 16;
2960 /// Mask (8 bits: 0xff << 16)
2961 pub const mask: u32 = 0xff << offset;
2962 /// Read-only values (empty)
2963 pub mod R {}
2964 /// Write-only values (empty)
2965 pub mod W {}
2966 /// Read-write values (empty)
2967 pub mod RW {}
2968 }
2969
2970 /// DATA1
2971 pub mod DATA1 {
2972 /// Offset (8 bits)
2973 pub const offset: u32 = 8;
2974 /// Mask (8 bits: 0xff << 8)
2975 pub const mask: u32 = 0xff << offset;
2976 /// Read-only values (empty)
2977 pub mod R {}
2978 /// Write-only values (empty)
2979 pub mod W {}
2980 /// Read-write values (empty)
2981 pub mod RW {}
2982 }
2983
2984 /// DATA0
2985 pub mod DATA0 {
2986 /// Offset (0 bits)
2987 pub const offset: u32 = 0;
2988 /// Mask (8 bits: 0xff << 0)
2989 pub const mask: u32 = 0xff << offset;
2990 /// Read-only values (empty)
2991 pub mod R {}
2992 /// Write-only values (empty)
2993 pub mod W {}
2994 /// Read-write values (empty)
2995 pub mod RW {}
2996 }
2997}
2998
2999/// CAN_TDH0R
3000pub mod TDHR0 {
3001
3002 /// DATA7
3003 pub mod DATA7 {
3004 /// Offset (24 bits)
3005 pub const offset: u32 = 24;
3006 /// Mask (8 bits: 0xff << 24)
3007 pub const mask: u32 = 0xff << offset;
3008 /// Read-only values (empty)
3009 pub mod R {}
3010 /// Write-only values (empty)
3011 pub mod W {}
3012 /// Read-write values (empty)
3013 pub mod RW {}
3014 }
3015
3016 /// DATA6
3017 pub mod DATA6 {
3018 /// Offset (16 bits)
3019 pub const offset: u32 = 16;
3020 /// Mask (8 bits: 0xff << 16)
3021 pub const mask: u32 = 0xff << offset;
3022 /// Read-only values (empty)
3023 pub mod R {}
3024 /// Write-only values (empty)
3025 pub mod W {}
3026 /// Read-write values (empty)
3027 pub mod RW {}
3028 }
3029
3030 /// DATA5
3031 pub mod DATA5 {
3032 /// Offset (8 bits)
3033 pub const offset: u32 = 8;
3034 /// Mask (8 bits: 0xff << 8)
3035 pub const mask: u32 = 0xff << offset;
3036 /// Read-only values (empty)
3037 pub mod R {}
3038 /// Write-only values (empty)
3039 pub mod W {}
3040 /// Read-write values (empty)
3041 pub mod RW {}
3042 }
3043
3044 /// DATA4
3045 pub mod DATA4 {
3046 /// Offset (0 bits)
3047 pub const offset: u32 = 0;
3048 /// Mask (8 bits: 0xff << 0)
3049 pub const mask: u32 = 0xff << offset;
3050 /// Read-only values (empty)
3051 pub mod R {}
3052 /// Write-only values (empty)
3053 pub mod W {}
3054 /// Read-write values (empty)
3055 pub mod RW {}
3056 }
3057}
3058
3059/// CAN_TI0R
3060pub mod TIR1 {
3061 pub use super::TIR0::EXID;
3062 pub use super::TIR0::IDE;
3063 pub use super::TIR0::RTR;
3064 pub use super::TIR0::STID;
3065 pub use super::TIR0::TXRQ;
3066}
3067
3068/// CAN_TDT0R
3069pub mod TDTR1 {
3070 pub use super::TDTR0::DLC;
3071 pub use super::TDTR0::TGT;
3072 pub use super::TDTR0::TIME;
3073}
3074
3075/// CAN_TDL0R
3076pub mod TDLR1 {
3077 pub use super::TDLR0::DATA0;
3078 pub use super::TDLR0::DATA1;
3079 pub use super::TDLR0::DATA2;
3080 pub use super::TDLR0::DATA3;
3081}
3082
3083/// CAN_TDH0R
3084pub mod TDHR1 {
3085 pub use super::TDHR0::DATA4;
3086 pub use super::TDHR0::DATA5;
3087 pub use super::TDHR0::DATA6;
3088 pub use super::TDHR0::DATA7;
3089}
3090
3091/// CAN_TI0R
3092pub mod TIR2 {
3093 pub use super::TIR0::EXID;
3094 pub use super::TIR0::IDE;
3095 pub use super::TIR0::RTR;
3096 pub use super::TIR0::STID;
3097 pub use super::TIR0::TXRQ;
3098}
3099
3100/// CAN_TDT0R
3101pub mod TDTR2 {
3102 pub use super::TDTR0::DLC;
3103 pub use super::TDTR0::TGT;
3104 pub use super::TDTR0::TIME;
3105}
3106
3107/// CAN_TDL0R
3108pub mod TDLR2 {
3109 pub use super::TDLR0::DATA0;
3110 pub use super::TDLR0::DATA1;
3111 pub use super::TDLR0::DATA2;
3112 pub use super::TDLR0::DATA3;
3113}
3114
3115/// CAN_TDH0R
3116pub mod TDHR2 {
3117 pub use super::TDHR0::DATA4;
3118 pub use super::TDHR0::DATA5;
3119 pub use super::TDHR0::DATA6;
3120 pub use super::TDHR0::DATA7;
3121}
3122
3123/// CAN_RI0R
3124pub mod RIR0 {
3125
3126 /// STID
3127 pub mod STID {
3128 /// Offset (21 bits)
3129 pub const offset: u32 = 21;
3130 /// Mask (11 bits: 0x7ff << 21)
3131 pub const mask: u32 = 0x7ff << offset;
3132 /// Read-only values (empty)
3133 pub mod R {}
3134 /// Write-only values (empty)
3135 pub mod W {}
3136 /// Read-write values (empty)
3137 pub mod RW {}
3138 }
3139
3140 /// EXID
3141 pub mod EXID {
3142 /// Offset (3 bits)
3143 pub const offset: u32 = 3;
3144 /// Mask (18 bits: 0x3ffff << 3)
3145 pub const mask: u32 = 0x3ffff << offset;
3146 /// Read-only values (empty)
3147 pub mod R {}
3148 /// Write-only values (empty)
3149 pub mod W {}
3150 /// Read-write values (empty)
3151 pub mod RW {}
3152 }
3153
3154 /// IDE
3155 pub mod IDE {
3156 /// Offset (2 bits)
3157 pub const offset: u32 = 2;
3158 /// Mask (1 bit: 1 << 2)
3159 pub const mask: u32 = 1 << offset;
3160 /// Read-only values
3161 pub mod R {
3162
3163 /// 0b0: Standard identifier
3164 pub const Standard: u32 = 0b0;
3165
3166 /// 0b1: Extended identifier
3167 pub const Extended: u32 = 0b1;
3168 }
3169 /// Write-only values (empty)
3170 pub mod W {}
3171 /// Read-write values (empty)
3172 pub mod RW {}
3173 }
3174
3175 /// RTR
3176 pub mod RTR {
3177 /// Offset (1 bits)
3178 pub const offset: u32 = 1;
3179 /// Mask (1 bit: 1 << 1)
3180 pub const mask: u32 = 1 << offset;
3181 /// Read-only values
3182 pub mod R {
3183
3184 /// 0b0: Data frame
3185 pub const Data: u32 = 0b0;
3186
3187 /// 0b1: Remote frame
3188 pub const Remote: u32 = 0b1;
3189 }
3190 /// Write-only values (empty)
3191 pub mod W {}
3192 /// Read-write values (empty)
3193 pub mod RW {}
3194 }
3195}
3196
3197/// CAN_RDT0R
3198pub mod RDTR0 {
3199
3200 /// TIME
3201 pub mod TIME {
3202 /// Offset (16 bits)
3203 pub const offset: u32 = 16;
3204 /// Mask (16 bits: 0xffff << 16)
3205 pub const mask: u32 = 0xffff << offset;
3206 /// Read-only values (empty)
3207 pub mod R {}
3208 /// Write-only values (empty)
3209 pub mod W {}
3210 /// Read-write values (empty)
3211 pub mod RW {}
3212 }
3213
3214 /// FMI
3215 pub mod FMI {
3216 /// Offset (8 bits)
3217 pub const offset: u32 = 8;
3218 /// Mask (8 bits: 0xff << 8)
3219 pub const mask: u32 = 0xff << offset;
3220 /// Read-only values (empty)
3221 pub mod R {}
3222 /// Write-only values (empty)
3223 pub mod W {}
3224 /// Read-write values (empty)
3225 pub mod RW {}
3226 }
3227
3228 /// DLC
3229 pub mod DLC {
3230 /// Offset (0 bits)
3231 pub const offset: u32 = 0;
3232 /// Mask (4 bits: 0b1111 << 0)
3233 pub const mask: u32 = 0b1111 << offset;
3234 /// Read-only values (empty)
3235 pub mod R {}
3236 /// Write-only values (empty)
3237 pub mod W {}
3238 /// Read-write values (empty)
3239 pub mod RW {}
3240 }
3241}
3242
3243/// CAN_RDL0R
3244pub mod RDLR0 {
3245
3246 /// DATA3
3247 pub mod DATA3 {
3248 /// Offset (24 bits)
3249 pub const offset: u32 = 24;
3250 /// Mask (8 bits: 0xff << 24)
3251 pub const mask: u32 = 0xff << offset;
3252 /// Read-only values (empty)
3253 pub mod R {}
3254 /// Write-only values (empty)
3255 pub mod W {}
3256 /// Read-write values (empty)
3257 pub mod RW {}
3258 }
3259
3260 /// DATA2
3261 pub mod DATA2 {
3262 /// Offset (16 bits)
3263 pub const offset: u32 = 16;
3264 /// Mask (8 bits: 0xff << 16)
3265 pub const mask: u32 = 0xff << offset;
3266 /// Read-only values (empty)
3267 pub mod R {}
3268 /// Write-only values (empty)
3269 pub mod W {}
3270 /// Read-write values (empty)
3271 pub mod RW {}
3272 }
3273
3274 /// DATA1
3275 pub mod DATA1 {
3276 /// Offset (8 bits)
3277 pub const offset: u32 = 8;
3278 /// Mask (8 bits: 0xff << 8)
3279 pub const mask: u32 = 0xff << offset;
3280 /// Read-only values (empty)
3281 pub mod R {}
3282 /// Write-only values (empty)
3283 pub mod W {}
3284 /// Read-write values (empty)
3285 pub mod RW {}
3286 }
3287
3288 /// DATA0
3289 pub mod DATA0 {
3290 /// Offset (0 bits)
3291 pub const offset: u32 = 0;
3292 /// Mask (8 bits: 0xff << 0)
3293 pub const mask: u32 = 0xff << offset;
3294 /// Read-only values (empty)
3295 pub mod R {}
3296 /// Write-only values (empty)
3297 pub mod W {}
3298 /// Read-write values (empty)
3299 pub mod RW {}
3300 }
3301}
3302
3303/// CAN_RDH0R
3304pub mod RDHR0 {
3305
3306 /// DATA7
3307 pub mod DATA7 {
3308 /// Offset (24 bits)
3309 pub const offset: u32 = 24;
3310 /// Mask (8 bits: 0xff << 24)
3311 pub const mask: u32 = 0xff << offset;
3312 /// Read-only values (empty)
3313 pub mod R {}
3314 /// Write-only values (empty)
3315 pub mod W {}
3316 /// Read-write values (empty)
3317 pub mod RW {}
3318 }
3319
3320 /// DATA6
3321 pub mod DATA6 {
3322 /// Offset (16 bits)
3323 pub const offset: u32 = 16;
3324 /// Mask (8 bits: 0xff << 16)
3325 pub const mask: u32 = 0xff << offset;
3326 /// Read-only values (empty)
3327 pub mod R {}
3328 /// Write-only values (empty)
3329 pub mod W {}
3330 /// Read-write values (empty)
3331 pub mod RW {}
3332 }
3333
3334 /// DATA5
3335 pub mod DATA5 {
3336 /// Offset (8 bits)
3337 pub const offset: u32 = 8;
3338 /// Mask (8 bits: 0xff << 8)
3339 pub const mask: u32 = 0xff << offset;
3340 /// Read-only values (empty)
3341 pub mod R {}
3342 /// Write-only values (empty)
3343 pub mod W {}
3344 /// Read-write values (empty)
3345 pub mod RW {}
3346 }
3347
3348 /// DATA4
3349 pub mod DATA4 {
3350 /// Offset (0 bits)
3351 pub const offset: u32 = 0;
3352 /// Mask (8 bits: 0xff << 0)
3353 pub const mask: u32 = 0xff << offset;
3354 /// Read-only values (empty)
3355 pub mod R {}
3356 /// Write-only values (empty)
3357 pub mod W {}
3358 /// Read-write values (empty)
3359 pub mod RW {}
3360 }
3361}
3362
3363/// CAN_RI0R
3364pub mod RIR1 {
3365 pub use super::RIR0::EXID;
3366 pub use super::RIR0::IDE;
3367 pub use super::RIR0::RTR;
3368 pub use super::RIR0::STID;
3369}
3370
3371/// CAN_RDT0R
3372pub mod RDTR1 {
3373 pub use super::RDTR0::DLC;
3374 pub use super::RDTR0::FMI;
3375 pub use super::RDTR0::TIME;
3376}
3377
3378/// CAN_RDL0R
3379pub mod RDLR1 {
3380 pub use super::RDLR0::DATA0;
3381 pub use super::RDLR0::DATA1;
3382 pub use super::RDLR0::DATA2;
3383 pub use super::RDLR0::DATA3;
3384}
3385
3386/// CAN_RDH0R
3387pub mod RDHR1 {
3388 pub use super::RDHR0::DATA4;
3389 pub use super::RDHR0::DATA5;
3390 pub use super::RDHR0::DATA6;
3391 pub use super::RDHR0::DATA7;
3392}
3393
3394/// Filter bank 0 register 1
3395pub mod FR10 {
3396
3397 /// Filter bits
3398 pub mod FB {
3399 /// Offset (0 bits)
3400 pub const offset: u32 = 0;
3401 /// Mask (32 bits: 0xffffffff << 0)
3402 pub const mask: u32 = 0xffffffff << offset;
3403 /// Read-only values (empty)
3404 pub mod R {}
3405 /// Write-only values (empty)
3406 pub mod W {}
3407 /// Read-write values (empty)
3408 pub mod RW {}
3409 }
3410}
3411
3412/// Filter bank 0 register 2
3413pub mod FR20 {
3414 pub use super::FR10::FB;
3415}
3416
3417/// Filter bank 0 register 1
3418pub mod FR11 {
3419 pub use super::FR10::FB;
3420}
3421
3422/// Filter bank 0 register 2
3423pub mod FR21 {
3424 pub use super::FR10::FB;
3425}
3426
3427/// Filter bank 0 register 1
3428pub mod FR12 {
3429 pub use super::FR10::FB;
3430}
3431
3432/// Filter bank 0 register 2
3433pub mod FR22 {
3434 pub use super::FR10::FB;
3435}
3436
3437/// Filter bank 0 register 1
3438pub mod FR13 {
3439 pub use super::FR10::FB;
3440}
3441
3442/// Filter bank 0 register 2
3443pub mod FR23 {
3444 pub use super::FR10::FB;
3445}
3446
3447/// Filter bank 0 register 1
3448pub mod FR14 {
3449 pub use super::FR10::FB;
3450}
3451
3452/// Filter bank 0 register 2
3453pub mod FR24 {
3454 pub use super::FR10::FB;
3455}
3456
3457/// Filter bank 0 register 1
3458pub mod FR15 {
3459 pub use super::FR10::FB;
3460}
3461
3462/// Filter bank 0 register 2
3463pub mod FR25 {
3464 pub use super::FR10::FB;
3465}
3466
3467/// Filter bank 0 register 1
3468pub mod FR16 {
3469 pub use super::FR10::FB;
3470}
3471
3472/// Filter bank 0 register 2
3473pub mod FR26 {
3474 pub use super::FR10::FB;
3475}
3476
3477/// Filter bank 0 register 1
3478pub mod FR17 {
3479 pub use super::FR10::FB;
3480}
3481
3482/// Filter bank 0 register 2
3483pub mod FR27 {
3484 pub use super::FR10::FB;
3485}
3486
3487/// Filter bank 0 register 1
3488pub mod FR18 {
3489 pub use super::FR10::FB;
3490}
3491
3492/// Filter bank 0 register 2
3493pub mod FR28 {
3494 pub use super::FR10::FB;
3495}
3496
3497/// Filter bank 0 register 1
3498pub mod FR19 {
3499 pub use super::FR10::FB;
3500}
3501
3502/// Filter bank 0 register 2
3503pub mod FR29 {
3504 pub use super::FR10::FB;
3505}
3506
3507/// Filter bank 0 register 1
3508pub mod FR110 {
3509 pub use super::FR10::FB;
3510}
3511
3512/// Filter bank 0 register 2
3513pub mod FR210 {
3514 pub use super::FR10::FB;
3515}
3516
3517/// Filter bank 0 register 1
3518pub mod FR111 {
3519 pub use super::FR10::FB;
3520}
3521
3522/// Filter bank 0 register 2
3523pub mod FR211 {
3524 pub use super::FR10::FB;
3525}
3526
3527/// Filter bank 0 register 1
3528pub mod FR112 {
3529 pub use super::FR10::FB;
3530}
3531
3532/// Filter bank 0 register 2
3533pub mod FR212 {
3534 pub use super::FR10::FB;
3535}
3536
3537/// Filter bank 0 register 1
3538pub mod FR113 {
3539 pub use super::FR10::FB;
3540}
3541
3542/// Filter bank 0 register 2
3543pub mod FR213 {
3544 pub use super::FR10::FB;
3545}
3546
3547/// Filter bank 0 register 1
3548pub mod FR114 {
3549 pub use super::FR10::FB;
3550}
3551
3552/// Filter bank 0 register 2
3553pub mod FR214 {
3554 pub use super::FR10::FB;
3555}
3556
3557/// Filter bank 0 register 1
3558pub mod FR115 {
3559 pub use super::FR10::FB;
3560}
3561
3562/// Filter bank 0 register 2
3563pub mod FR215 {
3564 pub use super::FR10::FB;
3565}
3566
3567/// Filter bank 0 register 1
3568pub mod FR116 {
3569 pub use super::FR10::FB;
3570}
3571
3572/// Filter bank 0 register 2
3573pub mod FR216 {
3574 pub use super::FR10::FB;
3575}
3576
3577/// Filter bank 0 register 1
3578pub mod FR117 {
3579 pub use super::FR10::FB;
3580}
3581
3582/// Filter bank 0 register 2
3583pub mod FR217 {
3584 pub use super::FR10::FB;
3585}
3586
3587/// Filter bank 0 register 1
3588pub mod FR118 {
3589 pub use super::FR10::FB;
3590}
3591
3592/// Filter bank 0 register 2
3593pub mod FR218 {
3594 pub use super::FR10::FB;
3595}
3596
3597/// Filter bank 0 register 1
3598pub mod FR119 {
3599 pub use super::FR10::FB;
3600}
3601
3602/// Filter bank 0 register 2
3603pub mod FR219 {
3604 pub use super::FR10::FB;
3605}
3606
3607/// Filter bank 0 register 1
3608pub mod FR120 {
3609 pub use super::FR10::FB;
3610}
3611
3612/// Filter bank 0 register 2
3613pub mod FR220 {
3614 pub use super::FR10::FB;
3615}
3616
3617/// Filter bank 0 register 1
3618pub mod FR121 {
3619 pub use super::FR10::FB;
3620}
3621
3622/// Filter bank 0 register 2
3623pub mod FR221 {
3624 pub use super::FR10::FB;
3625}
3626
3627/// Filter bank 0 register 1
3628pub mod FR122 {
3629 pub use super::FR10::FB;
3630}
3631
3632/// Filter bank 0 register 2
3633pub mod FR222 {
3634 pub use super::FR10::FB;
3635}
3636
3637/// Filter bank 0 register 1
3638pub mod FR123 {
3639 pub use super::FR10::FB;
3640}
3641
3642/// Filter bank 0 register 2
3643pub mod FR223 {
3644 pub use super::FR10::FB;
3645}
3646
3647/// Filter bank 0 register 1
3648pub mod FR124 {
3649 pub use super::FR10::FB;
3650}
3651
3652/// Filter bank 0 register 2
3653pub mod FR224 {
3654 pub use super::FR10::FB;
3655}
3656
3657/// Filter bank 0 register 1
3658pub mod FR125 {
3659 pub use super::FR10::FB;
3660}
3661
3662/// Filter bank 0 register 2
3663pub mod FR225 {
3664 pub use super::FR10::FB;
3665}
3666
3667/// Filter bank 0 register 1
3668pub mod FR126 {
3669 pub use super::FR10::FB;
3670}
3671
3672/// Filter bank 0 register 2
3673pub mod FR226 {
3674 pub use super::FR10::FB;
3675}
3676
3677/// Filter bank 0 register 1
3678pub mod FR127 {
3679 pub use super::FR10::FB;
3680}
3681
3682/// Filter bank 0 register 2
3683pub mod FR227 {
3684 pub use super::FR10::FB;
3685}
3686#[repr(C)]
3687pub struct RegisterBlock {
3688 /// CAN_MCR
3689 pub MCR: RWRegister<u32>,
3690
3691 /// CAN_MSR
3692 pub MSR: RWRegister<u32>,
3693
3694 /// CAN_TSR
3695 pub TSR: RWRegister<u32>,
3696
3697 /// CAN_RF%sR
3698 pub RF0R: RWRegister<u32>,
3699
3700 /// CAN_RF%sR
3701 pub RF1R: RWRegister<u32>,
3702
3703 /// CAN_IER
3704 pub IER: RWRegister<u32>,
3705
3706 /// CAN_ESR
3707 pub ESR: RWRegister<u32>,
3708
3709 /// CAN_BTR
3710 pub BTR: RWRegister<u32>,
3711
3712 _reserved1: [u8; 352],
3713
3714 /// CAN_TI0R
3715 pub TIR0: RWRegister<u32>,
3716
3717 /// CAN_TDT0R
3718 pub TDTR0: RWRegister<u32>,
3719
3720 /// CAN_TDL0R
3721 pub TDLR0: RWRegister<u32>,
3722
3723 /// CAN_TDH0R
3724 pub TDHR0: RWRegister<u32>,
3725
3726 /// CAN_TI0R
3727 pub TIR1: RWRegister<u32>,
3728
3729 /// CAN_TDT0R
3730 pub TDTR1: RWRegister<u32>,
3731
3732 /// CAN_TDL0R
3733 pub TDLR1: RWRegister<u32>,
3734
3735 /// CAN_TDH0R
3736 pub TDHR1: RWRegister<u32>,
3737
3738 /// CAN_TI0R
3739 pub TIR2: RWRegister<u32>,
3740
3741 /// CAN_TDT0R
3742 pub TDTR2: RWRegister<u32>,
3743
3744 /// CAN_TDL0R
3745 pub TDLR2: RWRegister<u32>,
3746
3747 /// CAN_TDH0R
3748 pub TDHR2: RWRegister<u32>,
3749
3750 /// CAN_RI0R
3751 pub RIR0: RORegister<u32>,
3752
3753 /// CAN_RDT0R
3754 pub RDTR0: RORegister<u32>,
3755
3756 /// CAN_RDL0R
3757 pub RDLR0: RORegister<u32>,
3758
3759 /// CAN_RDH0R
3760 pub RDHR0: RORegister<u32>,
3761
3762 /// CAN_RI0R
3763 pub RIR1: RORegister<u32>,
3764
3765 /// CAN_RDT0R
3766 pub RDTR1: RORegister<u32>,
3767
3768 /// CAN_RDL0R
3769 pub RDLR1: RORegister<u32>,
3770
3771 /// CAN_RDH0R
3772 pub RDHR1: RORegister<u32>,
3773
3774 _reserved2: [u8; 48],
3775
3776 /// CAN_FMR
3777 pub FMR: RWRegister<u32>,
3778
3779 /// CAN_FM1R
3780 pub FM1R: RWRegister<u32>,
3781
3782 _reserved3: [u8; 4],
3783
3784 /// CAN_FS1R
3785 pub FS1R: RWRegister<u32>,
3786
3787 _reserved4: [u8; 4],
3788
3789 /// CAN_FFA1R
3790 pub FFA1R: RWRegister<u32>,
3791
3792 _reserved5: [u8; 4],
3793
3794 /// CAN_FA1R
3795 pub FA1R: RWRegister<u32>,
3796
3797 _reserved6: [u8; 32],
3798
3799 /// Filter bank 0 register 1
3800 pub FR10: RWRegister<u32>,
3801
3802 /// Filter bank 0 register 2
3803 pub FR20: RWRegister<u32>,
3804
3805 /// Filter bank 0 register 1
3806 pub FR11: RWRegister<u32>,
3807
3808 /// Filter bank 0 register 2
3809 pub FR21: RWRegister<u32>,
3810
3811 /// Filter bank 0 register 1
3812 pub FR12: RWRegister<u32>,
3813
3814 /// Filter bank 0 register 2
3815 pub FR22: RWRegister<u32>,
3816
3817 /// Filter bank 0 register 1
3818 pub FR13: RWRegister<u32>,
3819
3820 /// Filter bank 0 register 2
3821 pub FR23: RWRegister<u32>,
3822
3823 /// Filter bank 0 register 1
3824 pub FR14: RWRegister<u32>,
3825
3826 /// Filter bank 0 register 2
3827 pub FR24: RWRegister<u32>,
3828
3829 /// Filter bank 0 register 1
3830 pub FR15: RWRegister<u32>,
3831
3832 /// Filter bank 0 register 2
3833 pub FR25: RWRegister<u32>,
3834
3835 /// Filter bank 0 register 1
3836 pub FR16: RWRegister<u32>,
3837
3838 /// Filter bank 0 register 2
3839 pub FR26: RWRegister<u32>,
3840
3841 /// Filter bank 0 register 1
3842 pub FR17: RWRegister<u32>,
3843
3844 /// Filter bank 0 register 2
3845 pub FR27: RWRegister<u32>,
3846
3847 /// Filter bank 0 register 1
3848 pub FR18: RWRegister<u32>,
3849
3850 /// Filter bank 0 register 2
3851 pub FR28: RWRegister<u32>,
3852
3853 /// Filter bank 0 register 1
3854 pub FR19: RWRegister<u32>,
3855
3856 /// Filter bank 0 register 2
3857 pub FR29: RWRegister<u32>,
3858
3859 /// Filter bank 0 register 1
3860 pub FR110: RWRegister<u32>,
3861
3862 /// Filter bank 0 register 2
3863 pub FR210: RWRegister<u32>,
3864
3865 /// Filter bank 0 register 1
3866 pub FR111: RWRegister<u32>,
3867
3868 /// Filter bank 0 register 2
3869 pub FR211: RWRegister<u32>,
3870
3871 /// Filter bank 0 register 1
3872 pub FR112: RWRegister<u32>,
3873
3874 /// Filter bank 0 register 2
3875 pub FR212: RWRegister<u32>,
3876
3877 /// Filter bank 0 register 1
3878 pub FR113: RWRegister<u32>,
3879
3880 /// Filter bank 0 register 2
3881 pub FR213: RWRegister<u32>,
3882
3883 /// Filter bank 0 register 1
3884 pub FR114: RWRegister<u32>,
3885
3886 /// Filter bank 0 register 2
3887 pub FR214: RWRegister<u32>,
3888
3889 /// Filter bank 0 register 1
3890 pub FR115: RWRegister<u32>,
3891
3892 /// Filter bank 0 register 2
3893 pub FR215: RWRegister<u32>,
3894
3895 /// Filter bank 0 register 1
3896 pub FR116: RWRegister<u32>,
3897
3898 /// Filter bank 0 register 2
3899 pub FR216: RWRegister<u32>,
3900
3901 /// Filter bank 0 register 1
3902 pub FR117: RWRegister<u32>,
3903
3904 /// Filter bank 0 register 2
3905 pub FR217: RWRegister<u32>,
3906
3907 /// Filter bank 0 register 1
3908 pub FR118: RWRegister<u32>,
3909
3910 /// Filter bank 0 register 2
3911 pub FR218: RWRegister<u32>,
3912
3913 /// Filter bank 0 register 1
3914 pub FR119: RWRegister<u32>,
3915
3916 /// Filter bank 0 register 2
3917 pub FR219: RWRegister<u32>,
3918
3919 /// Filter bank 0 register 1
3920 pub FR120: RWRegister<u32>,
3921
3922 /// Filter bank 0 register 2
3923 pub FR220: RWRegister<u32>,
3924
3925 /// Filter bank 0 register 1
3926 pub FR121: RWRegister<u32>,
3927
3928 /// Filter bank 0 register 2
3929 pub FR221: RWRegister<u32>,
3930
3931 /// Filter bank 0 register 1
3932 pub FR122: RWRegister<u32>,
3933
3934 /// Filter bank 0 register 2
3935 pub FR222: RWRegister<u32>,
3936
3937 /// Filter bank 0 register 1
3938 pub FR123: RWRegister<u32>,
3939
3940 /// Filter bank 0 register 2
3941 pub FR223: RWRegister<u32>,
3942
3943 /// Filter bank 0 register 1
3944 pub FR124: RWRegister<u32>,
3945
3946 /// Filter bank 0 register 2
3947 pub FR224: RWRegister<u32>,
3948
3949 /// Filter bank 0 register 1
3950 pub FR125: RWRegister<u32>,
3951
3952 /// Filter bank 0 register 2
3953 pub FR225: RWRegister<u32>,
3954
3955 /// Filter bank 0 register 1
3956 pub FR126: RWRegister<u32>,
3957
3958 /// Filter bank 0 register 2
3959 pub FR226: RWRegister<u32>,
3960
3961 /// Filter bank 0 register 1
3962 pub FR127: RWRegister<u32>,
3963
3964 /// Filter bank 0 register 2
3965 pub FR227: RWRegister<u32>,
3966}
3967pub struct ResetValues {
3968 pub MCR: u32,
3969 pub MSR: u32,
3970 pub TSR: u32,
3971 pub RF0R: u32,
3972 pub RF1R: u32,
3973 pub IER: u32,
3974 pub ESR: u32,
3975 pub BTR: u32,
3976 pub TIR0: u32,
3977 pub TDTR0: u32,
3978 pub TDLR0: u32,
3979 pub TDHR0: u32,
3980 pub TIR1: u32,
3981 pub TDTR1: u32,
3982 pub TDLR1: u32,
3983 pub TDHR1: u32,
3984 pub TIR2: u32,
3985 pub TDTR2: u32,
3986 pub TDLR2: u32,
3987 pub TDHR2: u32,
3988 pub RIR0: u32,
3989 pub RDTR0: u32,
3990 pub RDLR0: u32,
3991 pub RDHR0: u32,
3992 pub RIR1: u32,
3993 pub RDTR1: u32,
3994 pub RDLR1: u32,
3995 pub RDHR1: u32,
3996 pub FMR: u32,
3997 pub FM1R: u32,
3998 pub FS1R: u32,
3999 pub FFA1R: u32,
4000 pub FA1R: u32,
4001 pub FR10: u32,
4002 pub FR20: u32,
4003 pub FR11: u32,
4004 pub FR21: u32,
4005 pub FR12: u32,
4006 pub FR22: u32,
4007 pub FR13: u32,
4008 pub FR23: u32,
4009 pub FR14: u32,
4010 pub FR24: u32,
4011 pub FR15: u32,
4012 pub FR25: u32,
4013 pub FR16: u32,
4014 pub FR26: u32,
4015 pub FR17: u32,
4016 pub FR27: u32,
4017 pub FR18: u32,
4018 pub FR28: u32,
4019 pub FR19: u32,
4020 pub FR29: u32,
4021 pub FR110: u32,
4022 pub FR210: u32,
4023 pub FR111: u32,
4024 pub FR211: u32,
4025 pub FR112: u32,
4026 pub FR212: u32,
4027 pub FR113: u32,
4028 pub FR213: u32,
4029 pub FR114: u32,
4030 pub FR214: u32,
4031 pub FR115: u32,
4032 pub FR215: u32,
4033 pub FR116: u32,
4034 pub FR216: u32,
4035 pub FR117: u32,
4036 pub FR217: u32,
4037 pub FR118: u32,
4038 pub FR218: u32,
4039 pub FR119: u32,
4040 pub FR219: u32,
4041 pub FR120: u32,
4042 pub FR220: u32,
4043 pub FR121: u32,
4044 pub FR221: u32,
4045 pub FR122: u32,
4046 pub FR222: u32,
4047 pub FR123: u32,
4048 pub FR223: u32,
4049 pub FR124: u32,
4050 pub FR224: u32,
4051 pub FR125: u32,
4052 pub FR225: u32,
4053 pub FR126: u32,
4054 pub FR226: u32,
4055 pub FR127: u32,
4056 pub FR227: u32,
4057}
4058#[cfg(not(feature = "nosync"))]
4059pub struct Instance {
4060 pub(crate) addr: u32,
4061 pub(crate) _marker: PhantomData<*const RegisterBlock>,
4062}
4063#[cfg(not(feature = "nosync"))]
4064impl ::core::ops::Deref for Instance {
4065 type Target = RegisterBlock;
4066 #[inline(always)]
4067 fn deref(&self) -> &RegisterBlock {
4068 unsafe { &*(self.addr as *const _) }
4069 }
4070}
4071#[cfg(feature = "rtic")]
4072unsafe impl Send for Instance {}
4073
4074/// Access functions for the CAN1 peripheral instance
4075pub mod CAN1 {
4076 use super::ResetValues;
4077
4078 #[cfg(not(feature = "nosync"))]
4079 use super::Instance;
4080
4081 #[cfg(not(feature = "nosync"))]
4082 const INSTANCE: Instance = Instance {
4083 addr: 0x40006400,
4084 _marker: ::core::marker::PhantomData,
4085 };
4086
4087 /// Reset values for each field in CAN1
4088 pub const reset: ResetValues = ResetValues {
4089 MCR: 0x00000000,
4090 MSR: 0x00000000,
4091 TSR: 0x00000000,
4092 RF0R: 0x00000000,
4093 RF1R: 0x00000000,
4094 IER: 0x00000000,
4095 ESR: 0x00000000,
4096 BTR: 0x00000000,
4097 FMR: 0x00000000,
4098 FM1R: 0x00000000,
4099 FS1R: 0x00000000,
4100 FFA1R: 0x00000000,
4101 FA1R: 0x00000000,
4102 TIR0: 0x00000000,
4103 TDTR0: 0x00000000,
4104 TDLR0: 0x00000000,
4105 TDHR0: 0x00000000,
4106 TIR1: 0x00000000,
4107 TDTR1: 0x00000000,
4108 TDLR1: 0x00000000,
4109 TDHR1: 0x00000000,
4110 TIR2: 0x00000000,
4111 TDTR2: 0x00000000,
4112 TDLR2: 0x00000000,
4113 TDHR2: 0x00000000,
4114 RIR0: 0x00000000,
4115 RDTR0: 0x00000000,
4116 RDLR0: 0x00000000,
4117 RDHR0: 0x00000000,
4118 RIR1: 0x00000000,
4119 RDTR1: 0x00000000,
4120 RDLR1: 0x00000000,
4121 RDHR1: 0x00000000,
4122 FR10: 0x00000000,
4123 FR20: 0x00000000,
4124 FR11: 0x00000000,
4125 FR21: 0x00000000,
4126 FR12: 0x00000000,
4127 FR22: 0x00000000,
4128 FR13: 0x00000000,
4129 FR23: 0x00000000,
4130 FR14: 0x00000000,
4131 FR24: 0x00000000,
4132 FR15: 0x00000000,
4133 FR25: 0x00000000,
4134 FR16: 0x00000000,
4135 FR26: 0x00000000,
4136 FR17: 0x00000000,
4137 FR27: 0x00000000,
4138 FR18: 0x00000000,
4139 FR28: 0x00000000,
4140 FR19: 0x00000000,
4141 FR29: 0x00000000,
4142 FR110: 0x00000000,
4143 FR210: 0x00000000,
4144 FR111: 0x00000000,
4145 FR211: 0x00000000,
4146 FR112: 0x00000000,
4147 FR212: 0x00000000,
4148 FR113: 0x00000000,
4149 FR213: 0x00000000,
4150 FR114: 0x00000000,
4151 FR214: 0x00000000,
4152 FR115: 0x00000000,
4153 FR215: 0x00000000,
4154 FR116: 0x00000000,
4155 FR216: 0x00000000,
4156 FR117: 0x00000000,
4157 FR217: 0x00000000,
4158 FR118: 0x00000000,
4159 FR218: 0x00000000,
4160 FR119: 0x00000000,
4161 FR219: 0x00000000,
4162 FR120: 0x00000000,
4163 FR220: 0x00000000,
4164 FR121: 0x00000000,
4165 FR221: 0x00000000,
4166 FR122: 0x00000000,
4167 FR222: 0x00000000,
4168 FR123: 0x00000000,
4169 FR223: 0x00000000,
4170 FR124: 0x00000000,
4171 FR224: 0x00000000,
4172 FR125: 0x00000000,
4173 FR225: 0x00000000,
4174 FR126: 0x00000000,
4175 FR226: 0x00000000,
4176 FR127: 0x00000000,
4177 FR227: 0x00000000,
4178 };
4179
4180 #[cfg(not(feature = "nosync"))]
4181 #[allow(renamed_and_removed_lints)]
4182 #[allow(private_no_mangle_statics)]
4183 #[no_mangle]
4184 static mut CAN1_TAKEN: bool = false;
4185
4186 /// Safe access to CAN1
4187 ///
4188 /// This function returns `Some(Instance)` if this instance is not
4189 /// currently taken, and `None` if it is. This ensures that if you
4190 /// do get `Some(Instance)`, you are ensured unique access to
4191 /// the peripheral and there cannot be data races (unless other
4192 /// code uses `unsafe`, of course). You can then pass the
4193 /// `Instance` around to other functions as required. When you're
4194 /// done with it, you can call `release(instance)` to return it.
4195 ///
4196 /// `Instance` itself dereferences to a `RegisterBlock`, which
4197 /// provides access to the peripheral's registers.
4198 #[cfg(not(feature = "nosync"))]
4199 #[inline]
4200 pub fn take() -> Option<Instance> {
4201 external_cortex_m::interrupt::free(|_| unsafe {
4202 if CAN1_TAKEN {
4203 None
4204 } else {
4205 CAN1_TAKEN = true;
4206 Some(INSTANCE)
4207 }
4208 })
4209 }
4210
4211 /// Release exclusive access to CAN1
4212 ///
4213 /// This function allows you to return an `Instance` so that it
4214 /// is available to `take()` again. This function will panic if
4215 /// you return a different `Instance` or if this instance is not
4216 /// already taken.
4217 #[cfg(not(feature = "nosync"))]
4218 #[inline]
4219 pub fn release(inst: Instance) {
4220 external_cortex_m::interrupt::free(|_| unsafe {
4221 if CAN1_TAKEN && inst.addr == INSTANCE.addr {
4222 CAN1_TAKEN = false;
4223 } else {
4224 panic!("Released a peripheral which was not taken");
4225 }
4226 });
4227 }
4228
4229 /// Unsafely steal CAN1
4230 ///
4231 /// This function is similar to take() but forcibly takes the
4232 /// Instance, marking it as taken irregardless of its previous
4233 /// state.
4234 #[cfg(not(feature = "nosync"))]
4235 #[inline]
4236 pub unsafe fn steal() -> Instance {
4237 CAN1_TAKEN = true;
4238 INSTANCE
4239 }
4240}
4241
4242/// Raw pointer to CAN1
4243///
4244/// Dereferencing this is unsafe because you are not ensured unique
4245/// access to the peripheral, so you may encounter data races with
4246/// other users of this peripheral. It is up to you to ensure you
4247/// will not cause data races.
4248///
4249/// This constant is provided for ease of use in unsafe code: you can
4250/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
4251pub const CAN1: *const RegisterBlock = 0x40006400 as *const _;