stm32ral/stm32f1/stm32f103/sdio.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Secure digital input/output interface
4
5use crate::{RORegister, RWRegister};
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// Bits 1:0 = PWRCTRL: Power supply control bits
10pub mod POWER {
11
12 /// PWRCTRL
13 pub mod PWRCTRL {
14 /// Offset (0 bits)
15 pub const offset: u32 = 0;
16 /// Mask (2 bits: 0b11 << 0)
17 pub const mask: u32 = 0b11 << offset;
18 /// Read-only values (empty)
19 pub mod R {}
20 /// Write-only values (empty)
21 pub mod W {}
22 /// Read-write values (empty)
23 pub mod RW {}
24 }
25}
26
27/// SDI clock control register (SDIO_CLKCR)
28pub mod CLKCR {
29
30 /// Clock divide factor
31 pub mod CLKDIV {
32 /// Offset (0 bits)
33 pub const offset: u32 = 0;
34 /// Mask (8 bits: 0xff << 0)
35 pub const mask: u32 = 0xff << offset;
36 /// Read-only values (empty)
37 pub mod R {}
38 /// Write-only values (empty)
39 pub mod W {}
40 /// Read-write values (empty)
41 pub mod RW {}
42 }
43
44 /// Clock enable bit
45 pub mod CLKEN {
46 /// Offset (8 bits)
47 pub const offset: u32 = 8;
48 /// Mask (1 bit: 1 << 8)
49 pub const mask: u32 = 1 << offset;
50 /// Read-only values (empty)
51 pub mod R {}
52 /// Write-only values (empty)
53 pub mod W {}
54 /// Read-write values (empty)
55 pub mod RW {}
56 }
57
58 /// Power saving configuration bit
59 pub mod PWRSAV {
60 /// Offset (9 bits)
61 pub const offset: u32 = 9;
62 /// Mask (1 bit: 1 << 9)
63 pub const mask: u32 = 1 << offset;
64 /// Read-only values (empty)
65 pub mod R {}
66 /// Write-only values (empty)
67 pub mod W {}
68 /// Read-write values (empty)
69 pub mod RW {}
70 }
71
72 /// Clock divider bypass enable bit
73 pub mod BYPASS {
74 /// Offset (10 bits)
75 pub const offset: u32 = 10;
76 /// Mask (1 bit: 1 << 10)
77 pub const mask: u32 = 1 << offset;
78 /// Read-only values (empty)
79 pub mod R {}
80 /// Write-only values (empty)
81 pub mod W {}
82 /// Read-write values (empty)
83 pub mod RW {}
84 }
85
86 /// Wide bus mode enable bit
87 pub mod WIDBUS {
88 /// Offset (11 bits)
89 pub const offset: u32 = 11;
90 /// Mask (2 bits: 0b11 << 11)
91 pub const mask: u32 = 0b11 << offset;
92 /// Read-only values (empty)
93 pub mod R {}
94 /// Write-only values (empty)
95 pub mod W {}
96 /// Read-write values (empty)
97 pub mod RW {}
98 }
99
100 /// SDIO_CK dephasing selection bit
101 pub mod NEGEDGE {
102 /// Offset (13 bits)
103 pub const offset: u32 = 13;
104 /// Mask (1 bit: 1 << 13)
105 pub const mask: u32 = 1 << offset;
106 /// Read-only values (empty)
107 pub mod R {}
108 /// Write-only values (empty)
109 pub mod W {}
110 /// Read-write values (empty)
111 pub mod RW {}
112 }
113
114 /// HW Flow Control enable
115 pub mod HWFC_EN {
116 /// Offset (14 bits)
117 pub const offset: u32 = 14;
118 /// Mask (1 bit: 1 << 14)
119 pub const mask: u32 = 1 << offset;
120 /// Read-only values (empty)
121 pub mod R {}
122 /// Write-only values (empty)
123 pub mod W {}
124 /// Read-write values (empty)
125 pub mod RW {}
126 }
127}
128
129/// Bits 31:0 = : Command argument
130pub mod ARG {
131
132 /// Command argument
133 pub mod CMDARG {
134 /// Offset (0 bits)
135 pub const offset: u32 = 0;
136 /// Mask (32 bits: 0xffffffff << 0)
137 pub const mask: u32 = 0xffffffff << offset;
138 /// Read-only values (empty)
139 pub mod R {}
140 /// Write-only values (empty)
141 pub mod W {}
142 /// Read-write values (empty)
143 pub mod RW {}
144 }
145}
146
147/// SDIO command register (SDIO_CMD)
148pub mod CMD {
149
150 /// CMDINDEX
151 pub mod CMDINDEX {
152 /// Offset (0 bits)
153 pub const offset: u32 = 0;
154 /// Mask (6 bits: 0x3f << 0)
155 pub const mask: u32 = 0x3f << offset;
156 /// Read-only values (empty)
157 pub mod R {}
158 /// Write-only values (empty)
159 pub mod W {}
160 /// Read-write values (empty)
161 pub mod RW {}
162 }
163
164 /// WAITRESP
165 pub mod WAITRESP {
166 /// Offset (6 bits)
167 pub const offset: u32 = 6;
168 /// Mask (2 bits: 0b11 << 6)
169 pub const mask: u32 = 0b11 << offset;
170 /// Read-only values (empty)
171 pub mod R {}
172 /// Write-only values (empty)
173 pub mod W {}
174 /// Read-write values (empty)
175 pub mod RW {}
176 }
177
178 /// WAITINT
179 pub mod WAITINT {
180 /// Offset (8 bits)
181 pub const offset: u32 = 8;
182 /// Mask (1 bit: 1 << 8)
183 pub const mask: u32 = 1 << offset;
184 /// Read-only values (empty)
185 pub mod R {}
186 /// Write-only values (empty)
187 pub mod W {}
188 /// Read-write values (empty)
189 pub mod RW {}
190 }
191
192 /// WAITPEND
193 pub mod WAITPEND {
194 /// Offset (9 bits)
195 pub const offset: u32 = 9;
196 /// Mask (1 bit: 1 << 9)
197 pub const mask: u32 = 1 << offset;
198 /// Read-only values (empty)
199 pub mod R {}
200 /// Write-only values (empty)
201 pub mod W {}
202 /// Read-write values (empty)
203 pub mod RW {}
204 }
205
206 /// CPSMEN
207 pub mod CPSMEN {
208 /// Offset (10 bits)
209 pub const offset: u32 = 10;
210 /// Mask (1 bit: 1 << 10)
211 pub const mask: u32 = 1 << offset;
212 /// Read-only values (empty)
213 pub mod R {}
214 /// Write-only values (empty)
215 pub mod W {}
216 /// Read-write values (empty)
217 pub mod RW {}
218 }
219
220 /// SDIOSuspend
221 pub mod SDIOSuspend {
222 /// Offset (11 bits)
223 pub const offset: u32 = 11;
224 /// Mask (1 bit: 1 << 11)
225 pub const mask: u32 = 1 << offset;
226 /// Read-only values (empty)
227 pub mod R {}
228 /// Write-only values (empty)
229 pub mod W {}
230 /// Read-write values (empty)
231 pub mod RW {}
232 }
233
234 /// ENCMDcompl
235 pub mod ENCMDcompl {
236 /// Offset (12 bits)
237 pub const offset: u32 = 12;
238 /// Mask (1 bit: 1 << 12)
239 pub const mask: u32 = 1 << offset;
240 /// Read-only values (empty)
241 pub mod R {}
242 /// Write-only values (empty)
243 pub mod W {}
244 /// Read-write values (empty)
245 pub mod RW {}
246 }
247
248 /// nIEN
249 pub mod nIEN {
250 /// Offset (13 bits)
251 pub const offset: u32 = 13;
252 /// Mask (1 bit: 1 << 13)
253 pub const mask: u32 = 1 << offset;
254 /// Read-only values (empty)
255 pub mod R {}
256 /// Write-only values (empty)
257 pub mod W {}
258 /// Read-write values (empty)
259 pub mod RW {}
260 }
261
262 /// CE_ATACMD
263 pub mod CE_ATACMD {
264 /// Offset (14 bits)
265 pub const offset: u32 = 14;
266 /// Mask (1 bit: 1 << 14)
267 pub const mask: u32 = 1 << offset;
268 /// Read-only values (empty)
269 pub mod R {}
270 /// Write-only values (empty)
271 pub mod W {}
272 /// Read-write values (empty)
273 pub mod RW {}
274 }
275}
276
277/// SDIO command register
278pub mod RESPCMD {
279
280 /// RESPCMD
281 pub mod RESPCMD {
282 /// Offset (0 bits)
283 pub const offset: u32 = 0;
284 /// Mask (6 bits: 0x3f << 0)
285 pub const mask: u32 = 0x3f << offset;
286 /// Read-only values (empty)
287 pub mod R {}
288 /// Write-only values (empty)
289 pub mod W {}
290 /// Read-write values (empty)
291 pub mod RW {}
292 }
293}
294
295/// Bits 31:0 = CARDSTATUS1
296pub mod RESPI1 {
297
298 /// CARDSTATUS1
299 pub mod CARDSTATUS1 {
300 /// Offset (0 bits)
301 pub const offset: u32 = 0;
302 /// Mask (32 bits: 0xffffffff << 0)
303 pub const mask: u32 = 0xffffffff << offset;
304 /// Read-only values (empty)
305 pub mod R {}
306 /// Write-only values (empty)
307 pub mod W {}
308 /// Read-write values (empty)
309 pub mod RW {}
310 }
311}
312
313/// Bits 31:0 = CARDSTATUS2
314pub mod RESP2 {
315
316 /// CARDSTATUS2
317 pub mod CARDSTATUS2 {
318 /// Offset (0 bits)
319 pub const offset: u32 = 0;
320 /// Mask (32 bits: 0xffffffff << 0)
321 pub const mask: u32 = 0xffffffff << offset;
322 /// Read-only values (empty)
323 pub mod R {}
324 /// Write-only values (empty)
325 pub mod W {}
326 /// Read-write values (empty)
327 pub mod RW {}
328 }
329}
330
331/// Bits 31:0 = CARDSTATUS2
332pub mod RESP3 {
333 pub use super::RESP2::CARDSTATUS2;
334}
335
336/// Bits 31:0 = CARDSTATUS2
337pub mod RESP4 {
338 pub use super::RESP2::CARDSTATUS2;
339}
340
341/// Bits 31:0 = DATATIME: Data timeout period
342pub mod DTIMER {
343
344 /// Data timeout period
345 pub mod DATATIME {
346 /// Offset (0 bits)
347 pub const offset: u32 = 0;
348 /// Mask (32 bits: 0xffffffff << 0)
349 pub const mask: u32 = 0xffffffff << offset;
350 /// Read-only values (empty)
351 pub mod R {}
352 /// Write-only values (empty)
353 pub mod W {}
354 /// Read-write values (empty)
355 pub mod RW {}
356 }
357}
358
359/// Bits 24:0 = DATALENGTH: Data length value
360pub mod DLEN {
361
362 /// Data length value
363 pub mod DATALENGTH {
364 /// Offset (0 bits)
365 pub const offset: u32 = 0;
366 /// Mask (25 bits: 0x1ffffff << 0)
367 pub const mask: u32 = 0x1ffffff << offset;
368 /// Read-only values (empty)
369 pub mod R {}
370 /// Write-only values (empty)
371 pub mod W {}
372 /// Read-write values (empty)
373 pub mod RW {}
374 }
375}
376
377/// SDIO data control register (SDIO_DCTRL)
378pub mod DCTRL {
379
380 /// DTEN
381 pub mod DTEN {
382 /// Offset (0 bits)
383 pub const offset: u32 = 0;
384 /// Mask (1 bit: 1 << 0)
385 pub const mask: u32 = 1 << offset;
386 /// Read-only values (empty)
387 pub mod R {}
388 /// Write-only values (empty)
389 pub mod W {}
390 /// Read-write values (empty)
391 pub mod RW {}
392 }
393
394 /// DTDIR
395 pub mod DTDIR {
396 /// Offset (1 bits)
397 pub const offset: u32 = 1;
398 /// Mask (1 bit: 1 << 1)
399 pub const mask: u32 = 1 << offset;
400 /// Read-only values (empty)
401 pub mod R {}
402 /// Write-only values (empty)
403 pub mod W {}
404 /// Read-write values (empty)
405 pub mod RW {}
406 }
407
408 /// DTMODE
409 pub mod DTMODE {
410 /// Offset (2 bits)
411 pub const offset: u32 = 2;
412 /// Mask (1 bit: 1 << 2)
413 pub const mask: u32 = 1 << offset;
414 /// Read-only values (empty)
415 pub mod R {}
416 /// Write-only values (empty)
417 pub mod W {}
418 /// Read-write values (empty)
419 pub mod RW {}
420 }
421
422 /// DMAEN
423 pub mod DMAEN {
424 /// Offset (3 bits)
425 pub const offset: u32 = 3;
426 /// Mask (1 bit: 1 << 3)
427 pub const mask: u32 = 1 << offset;
428 /// Read-only values (empty)
429 pub mod R {}
430 /// Write-only values (empty)
431 pub mod W {}
432 /// Read-write values (empty)
433 pub mod RW {}
434 }
435
436 /// DBLOCKSIZE
437 pub mod DBLOCKSIZE {
438 /// Offset (4 bits)
439 pub const offset: u32 = 4;
440 /// Mask (4 bits: 0b1111 << 4)
441 pub const mask: u32 = 0b1111 << offset;
442 /// Read-only values (empty)
443 pub mod R {}
444 /// Write-only values (empty)
445 pub mod W {}
446 /// Read-write values (empty)
447 pub mod RW {}
448 }
449
450 /// PWSTART
451 pub mod PWSTART {
452 /// Offset (8 bits)
453 pub const offset: u32 = 8;
454 /// Mask (1 bit: 1 << 8)
455 pub const mask: u32 = 1 << offset;
456 /// Read-only values (empty)
457 pub mod R {}
458 /// Write-only values (empty)
459 pub mod W {}
460 /// Read-write values (empty)
461 pub mod RW {}
462 }
463
464 /// PWSTOP
465 pub mod PWSTOP {
466 /// Offset (9 bits)
467 pub const offset: u32 = 9;
468 /// Mask (1 bit: 1 << 9)
469 pub const mask: u32 = 1 << offset;
470 /// Read-only values (empty)
471 pub mod R {}
472 /// Write-only values (empty)
473 pub mod W {}
474 /// Read-write values (empty)
475 pub mod RW {}
476 }
477
478 /// RWMOD
479 pub mod RWMOD {
480 /// Offset (10 bits)
481 pub const offset: u32 = 10;
482 /// Mask (1 bit: 1 << 10)
483 pub const mask: u32 = 1 << offset;
484 /// Read-only values (empty)
485 pub mod R {}
486 /// Write-only values (empty)
487 pub mod W {}
488 /// Read-write values (empty)
489 pub mod RW {}
490 }
491
492 /// SDIOEN
493 pub mod SDIOEN {
494 /// Offset (11 bits)
495 pub const offset: u32 = 11;
496 /// Mask (1 bit: 1 << 11)
497 pub const mask: u32 = 1 << offset;
498 /// Read-only values (empty)
499 pub mod R {}
500 /// Write-only values (empty)
501 pub mod W {}
502 /// Read-write values (empty)
503 pub mod RW {}
504 }
505}
506
507/// Bits 24:0 = DATACOUNT: Data count value
508pub mod DCOUNT {
509
510 /// Data count value
511 pub mod DATACOUNT {
512 /// Offset (0 bits)
513 pub const offset: u32 = 0;
514 /// Mask (25 bits: 0x1ffffff << 0)
515 pub const mask: u32 = 0x1ffffff << offset;
516 /// Read-only values (empty)
517 pub mod R {}
518 /// Write-only values (empty)
519 pub mod W {}
520 /// Read-write values (empty)
521 pub mod RW {}
522 }
523}
524
525/// SDIO status register (SDIO_STA)
526pub mod STA {
527
528 /// CCRCFAIL
529 pub mod CCRCFAIL {
530 /// Offset (0 bits)
531 pub const offset: u32 = 0;
532 /// Mask (1 bit: 1 << 0)
533 pub const mask: u32 = 1 << offset;
534 /// Read-only values (empty)
535 pub mod R {}
536 /// Write-only values (empty)
537 pub mod W {}
538 /// Read-write values (empty)
539 pub mod RW {}
540 }
541
542 /// DCRCFAIL
543 pub mod DCRCFAIL {
544 /// Offset (1 bits)
545 pub const offset: u32 = 1;
546 /// Mask (1 bit: 1 << 1)
547 pub const mask: u32 = 1 << offset;
548 /// Read-only values (empty)
549 pub mod R {}
550 /// Write-only values (empty)
551 pub mod W {}
552 /// Read-write values (empty)
553 pub mod RW {}
554 }
555
556 /// CTIMEOUT
557 pub mod CTIMEOUT {
558 /// Offset (2 bits)
559 pub const offset: u32 = 2;
560 /// Mask (1 bit: 1 << 2)
561 pub const mask: u32 = 1 << offset;
562 /// Read-only values (empty)
563 pub mod R {}
564 /// Write-only values (empty)
565 pub mod W {}
566 /// Read-write values (empty)
567 pub mod RW {}
568 }
569
570 /// DTIMEOUT
571 pub mod DTIMEOUT {
572 /// Offset (3 bits)
573 pub const offset: u32 = 3;
574 /// Mask (1 bit: 1 << 3)
575 pub const mask: u32 = 1 << offset;
576 /// Read-only values (empty)
577 pub mod R {}
578 /// Write-only values (empty)
579 pub mod W {}
580 /// Read-write values (empty)
581 pub mod RW {}
582 }
583
584 /// TXUNDERR
585 pub mod TXUNDERR {
586 /// Offset (4 bits)
587 pub const offset: u32 = 4;
588 /// Mask (1 bit: 1 << 4)
589 pub const mask: u32 = 1 << offset;
590 /// Read-only values (empty)
591 pub mod R {}
592 /// Write-only values (empty)
593 pub mod W {}
594 /// Read-write values (empty)
595 pub mod RW {}
596 }
597
598 /// RXOVERR
599 pub mod RXOVERR {
600 /// Offset (5 bits)
601 pub const offset: u32 = 5;
602 /// Mask (1 bit: 1 << 5)
603 pub const mask: u32 = 1 << offset;
604 /// Read-only values (empty)
605 pub mod R {}
606 /// Write-only values (empty)
607 pub mod W {}
608 /// Read-write values (empty)
609 pub mod RW {}
610 }
611
612 /// CMDREND
613 pub mod CMDREND {
614 /// Offset (6 bits)
615 pub const offset: u32 = 6;
616 /// Mask (1 bit: 1 << 6)
617 pub const mask: u32 = 1 << offset;
618 /// Read-only values (empty)
619 pub mod R {}
620 /// Write-only values (empty)
621 pub mod W {}
622 /// Read-write values (empty)
623 pub mod RW {}
624 }
625
626 /// CMDSENT
627 pub mod CMDSENT {
628 /// Offset (7 bits)
629 pub const offset: u32 = 7;
630 /// Mask (1 bit: 1 << 7)
631 pub const mask: u32 = 1 << offset;
632 /// Read-only values (empty)
633 pub mod R {}
634 /// Write-only values (empty)
635 pub mod W {}
636 /// Read-write values (empty)
637 pub mod RW {}
638 }
639
640 /// DATAEND
641 pub mod DATAEND {
642 /// Offset (8 bits)
643 pub const offset: u32 = 8;
644 /// Mask (1 bit: 1 << 8)
645 pub const mask: u32 = 1 << offset;
646 /// Read-only values (empty)
647 pub mod R {}
648 /// Write-only values (empty)
649 pub mod W {}
650 /// Read-write values (empty)
651 pub mod RW {}
652 }
653
654 /// STBITERR
655 pub mod STBITERR {
656 /// Offset (9 bits)
657 pub const offset: u32 = 9;
658 /// Mask (1 bit: 1 << 9)
659 pub const mask: u32 = 1 << offset;
660 /// Read-only values (empty)
661 pub mod R {}
662 /// Write-only values (empty)
663 pub mod W {}
664 /// Read-write values (empty)
665 pub mod RW {}
666 }
667
668 /// DBCKEND
669 pub mod DBCKEND {
670 /// Offset (10 bits)
671 pub const offset: u32 = 10;
672 /// Mask (1 bit: 1 << 10)
673 pub const mask: u32 = 1 << offset;
674 /// Read-only values (empty)
675 pub mod R {}
676 /// Write-only values (empty)
677 pub mod W {}
678 /// Read-write values (empty)
679 pub mod RW {}
680 }
681
682 /// CMDACT
683 pub mod CMDACT {
684 /// Offset (11 bits)
685 pub const offset: u32 = 11;
686 /// Mask (1 bit: 1 << 11)
687 pub const mask: u32 = 1 << offset;
688 /// Read-only values (empty)
689 pub mod R {}
690 /// Write-only values (empty)
691 pub mod W {}
692 /// Read-write values (empty)
693 pub mod RW {}
694 }
695
696 /// TXACT
697 pub mod TXACT {
698 /// Offset (12 bits)
699 pub const offset: u32 = 12;
700 /// Mask (1 bit: 1 << 12)
701 pub const mask: u32 = 1 << offset;
702 /// Read-only values (empty)
703 pub mod R {}
704 /// Write-only values (empty)
705 pub mod W {}
706 /// Read-write values (empty)
707 pub mod RW {}
708 }
709
710 /// RXACT
711 pub mod RXACT {
712 /// Offset (13 bits)
713 pub const offset: u32 = 13;
714 /// Mask (1 bit: 1 << 13)
715 pub const mask: u32 = 1 << offset;
716 /// Read-only values (empty)
717 pub mod R {}
718 /// Write-only values (empty)
719 pub mod W {}
720 /// Read-write values (empty)
721 pub mod RW {}
722 }
723
724 /// TXFIFOHE
725 pub mod TXFIFOHE {
726 /// Offset (14 bits)
727 pub const offset: u32 = 14;
728 /// Mask (1 bit: 1 << 14)
729 pub const mask: u32 = 1 << offset;
730 /// Read-only values (empty)
731 pub mod R {}
732 /// Write-only values (empty)
733 pub mod W {}
734 /// Read-write values (empty)
735 pub mod RW {}
736 }
737
738 /// RXFIFOHF
739 pub mod RXFIFOHF {
740 /// Offset (15 bits)
741 pub const offset: u32 = 15;
742 /// Mask (1 bit: 1 << 15)
743 pub const mask: u32 = 1 << offset;
744 /// Read-only values (empty)
745 pub mod R {}
746 /// Write-only values (empty)
747 pub mod W {}
748 /// Read-write values (empty)
749 pub mod RW {}
750 }
751
752 /// TXFIFOF
753 pub mod TXFIFOF {
754 /// Offset (16 bits)
755 pub const offset: u32 = 16;
756 /// Mask (1 bit: 1 << 16)
757 pub const mask: u32 = 1 << offset;
758 /// Read-only values (empty)
759 pub mod R {}
760 /// Write-only values (empty)
761 pub mod W {}
762 /// Read-write values (empty)
763 pub mod RW {}
764 }
765
766 /// RXFIFOF
767 pub mod RXFIFOF {
768 /// Offset (17 bits)
769 pub const offset: u32 = 17;
770 /// Mask (1 bit: 1 << 17)
771 pub const mask: u32 = 1 << offset;
772 /// Read-only values (empty)
773 pub mod R {}
774 /// Write-only values (empty)
775 pub mod W {}
776 /// Read-write values (empty)
777 pub mod RW {}
778 }
779
780 /// TXFIFOE
781 pub mod TXFIFOE {
782 /// Offset (18 bits)
783 pub const offset: u32 = 18;
784 /// Mask (1 bit: 1 << 18)
785 pub const mask: u32 = 1 << offset;
786 /// Read-only values (empty)
787 pub mod R {}
788 /// Write-only values (empty)
789 pub mod W {}
790 /// Read-write values (empty)
791 pub mod RW {}
792 }
793
794 /// RXFIFOE
795 pub mod RXFIFOE {
796 /// Offset (19 bits)
797 pub const offset: u32 = 19;
798 /// Mask (1 bit: 1 << 19)
799 pub const mask: u32 = 1 << offset;
800 /// Read-only values (empty)
801 pub mod R {}
802 /// Write-only values (empty)
803 pub mod W {}
804 /// Read-write values (empty)
805 pub mod RW {}
806 }
807
808 /// TXDAVL
809 pub mod TXDAVL {
810 /// Offset (20 bits)
811 pub const offset: u32 = 20;
812 /// Mask (1 bit: 1 << 20)
813 pub const mask: u32 = 1 << offset;
814 /// Read-only values (empty)
815 pub mod R {}
816 /// Write-only values (empty)
817 pub mod W {}
818 /// Read-write values (empty)
819 pub mod RW {}
820 }
821
822 /// RXDAVL
823 pub mod RXDAVL {
824 /// Offset (21 bits)
825 pub const offset: u32 = 21;
826 /// Mask (1 bit: 1 << 21)
827 pub const mask: u32 = 1 << offset;
828 /// Read-only values (empty)
829 pub mod R {}
830 /// Write-only values (empty)
831 pub mod W {}
832 /// Read-write values (empty)
833 pub mod RW {}
834 }
835
836 /// SDIOIT
837 pub mod SDIOIT {
838 /// Offset (22 bits)
839 pub const offset: u32 = 22;
840 /// Mask (1 bit: 1 << 22)
841 pub const mask: u32 = 1 << offset;
842 /// Read-only values (empty)
843 pub mod R {}
844 /// Write-only values (empty)
845 pub mod W {}
846 /// Read-write values (empty)
847 pub mod RW {}
848 }
849
850 /// CEATAEND
851 pub mod CEATAEND {
852 /// Offset (23 bits)
853 pub const offset: u32 = 23;
854 /// Mask (1 bit: 1 << 23)
855 pub const mask: u32 = 1 << offset;
856 /// Read-only values (empty)
857 pub mod R {}
858 /// Write-only values (empty)
859 pub mod W {}
860 /// Read-write values (empty)
861 pub mod RW {}
862 }
863}
864
865/// SDIO interrupt clear register (SDIO_ICR)
866pub mod ICR {
867
868 /// CCRCFAILC
869 pub mod CCRCFAILC {
870 /// Offset (0 bits)
871 pub const offset: u32 = 0;
872 /// Mask (1 bit: 1 << 0)
873 pub const mask: u32 = 1 << offset;
874 /// Read-only values (empty)
875 pub mod R {}
876 /// Write-only values (empty)
877 pub mod W {}
878 /// Read-write values (empty)
879 pub mod RW {}
880 }
881
882 /// DCRCFAILC
883 pub mod DCRCFAILC {
884 /// Offset (1 bits)
885 pub const offset: u32 = 1;
886 /// Mask (1 bit: 1 << 1)
887 pub const mask: u32 = 1 << offset;
888 /// Read-only values (empty)
889 pub mod R {}
890 /// Write-only values (empty)
891 pub mod W {}
892 /// Read-write values (empty)
893 pub mod RW {}
894 }
895
896 /// CTIMEOUTC
897 pub mod CTIMEOUTC {
898 /// Offset (2 bits)
899 pub const offset: u32 = 2;
900 /// Mask (1 bit: 1 << 2)
901 pub const mask: u32 = 1 << offset;
902 /// Read-only values (empty)
903 pub mod R {}
904 /// Write-only values (empty)
905 pub mod W {}
906 /// Read-write values (empty)
907 pub mod RW {}
908 }
909
910 /// DTIMEOUTC
911 pub mod DTIMEOUTC {
912 /// Offset (3 bits)
913 pub const offset: u32 = 3;
914 /// Mask (1 bit: 1 << 3)
915 pub const mask: u32 = 1 << offset;
916 /// Read-only values (empty)
917 pub mod R {}
918 /// Write-only values (empty)
919 pub mod W {}
920 /// Read-write values (empty)
921 pub mod RW {}
922 }
923
924 /// TXUNDERRC
925 pub mod TXUNDERRC {
926 /// Offset (4 bits)
927 pub const offset: u32 = 4;
928 /// Mask (1 bit: 1 << 4)
929 pub const mask: u32 = 1 << offset;
930 /// Read-only values (empty)
931 pub mod R {}
932 /// Write-only values (empty)
933 pub mod W {}
934 /// Read-write values (empty)
935 pub mod RW {}
936 }
937
938 /// RXOVERRC
939 pub mod RXOVERRC {
940 /// Offset (5 bits)
941 pub const offset: u32 = 5;
942 /// Mask (1 bit: 1 << 5)
943 pub const mask: u32 = 1 << offset;
944 /// Read-only values (empty)
945 pub mod R {}
946 /// Write-only values (empty)
947 pub mod W {}
948 /// Read-write values (empty)
949 pub mod RW {}
950 }
951
952 /// CMDRENDC
953 pub mod CMDRENDC {
954 /// Offset (6 bits)
955 pub const offset: u32 = 6;
956 /// Mask (1 bit: 1 << 6)
957 pub const mask: u32 = 1 << offset;
958 /// Read-only values (empty)
959 pub mod R {}
960 /// Write-only values (empty)
961 pub mod W {}
962 /// Read-write values (empty)
963 pub mod RW {}
964 }
965
966 /// CMDSENTC
967 pub mod CMDSENTC {
968 /// Offset (7 bits)
969 pub const offset: u32 = 7;
970 /// Mask (1 bit: 1 << 7)
971 pub const mask: u32 = 1 << offset;
972 /// Read-only values (empty)
973 pub mod R {}
974 /// Write-only values (empty)
975 pub mod W {}
976 /// Read-write values (empty)
977 pub mod RW {}
978 }
979
980 /// DATAENDC
981 pub mod DATAENDC {
982 /// Offset (8 bits)
983 pub const offset: u32 = 8;
984 /// Mask (1 bit: 1 << 8)
985 pub const mask: u32 = 1 << offset;
986 /// Read-only values (empty)
987 pub mod R {}
988 /// Write-only values (empty)
989 pub mod W {}
990 /// Read-write values (empty)
991 pub mod RW {}
992 }
993
994 /// STBITERRC
995 pub mod STBITERRC {
996 /// Offset (9 bits)
997 pub const offset: u32 = 9;
998 /// Mask (1 bit: 1 << 9)
999 pub const mask: u32 = 1 << offset;
1000 /// Read-only values (empty)
1001 pub mod R {}
1002 /// Write-only values (empty)
1003 pub mod W {}
1004 /// Read-write values (empty)
1005 pub mod RW {}
1006 }
1007
1008 /// DBCKENDC
1009 pub mod DBCKENDC {
1010 /// Offset (10 bits)
1011 pub const offset: u32 = 10;
1012 /// Mask (1 bit: 1 << 10)
1013 pub const mask: u32 = 1 << offset;
1014 /// Read-only values (empty)
1015 pub mod R {}
1016 /// Write-only values (empty)
1017 pub mod W {}
1018 /// Read-write values (empty)
1019 pub mod RW {}
1020 }
1021
1022 /// SDIOITC
1023 pub mod SDIOITC {
1024 /// Offset (22 bits)
1025 pub const offset: u32 = 22;
1026 /// Mask (1 bit: 1 << 22)
1027 pub const mask: u32 = 1 << offset;
1028 /// Read-only values (empty)
1029 pub mod R {}
1030 /// Write-only values (empty)
1031 pub mod W {}
1032 /// Read-write values (empty)
1033 pub mod RW {}
1034 }
1035
1036 /// CEATAENDC
1037 pub mod CEATAENDC {
1038 /// Offset (23 bits)
1039 pub const offset: u32 = 23;
1040 /// Mask (1 bit: 1 << 23)
1041 pub const mask: u32 = 1 << offset;
1042 /// Read-only values (empty)
1043 pub mod R {}
1044 /// Write-only values (empty)
1045 pub mod W {}
1046 /// Read-write values (empty)
1047 pub mod RW {}
1048 }
1049}
1050
1051/// SDIO mask register (SDIO_MASK)
1052pub mod MASK {
1053
1054 /// CCRCFAILIE
1055 pub mod CCRCFAILIE {
1056 /// Offset (0 bits)
1057 pub const offset: u32 = 0;
1058 /// Mask (1 bit: 1 << 0)
1059 pub const mask: u32 = 1 << offset;
1060 /// Read-only values (empty)
1061 pub mod R {}
1062 /// Write-only values (empty)
1063 pub mod W {}
1064 /// Read-write values (empty)
1065 pub mod RW {}
1066 }
1067
1068 /// DCRCFAILIE
1069 pub mod DCRCFAILIE {
1070 /// Offset (1 bits)
1071 pub const offset: u32 = 1;
1072 /// Mask (1 bit: 1 << 1)
1073 pub const mask: u32 = 1 << offset;
1074 /// Read-only values (empty)
1075 pub mod R {}
1076 /// Write-only values (empty)
1077 pub mod W {}
1078 /// Read-write values (empty)
1079 pub mod RW {}
1080 }
1081
1082 /// CTIMEOUTIE
1083 pub mod CTIMEOUTIE {
1084 /// Offset (2 bits)
1085 pub const offset: u32 = 2;
1086 /// Mask (1 bit: 1 << 2)
1087 pub const mask: u32 = 1 << offset;
1088 /// Read-only values (empty)
1089 pub mod R {}
1090 /// Write-only values (empty)
1091 pub mod W {}
1092 /// Read-write values (empty)
1093 pub mod RW {}
1094 }
1095
1096 /// DTIMEOUTIE
1097 pub mod DTIMEOUTIE {
1098 /// Offset (3 bits)
1099 pub const offset: u32 = 3;
1100 /// Mask (1 bit: 1 << 3)
1101 pub const mask: u32 = 1 << offset;
1102 /// Read-only values (empty)
1103 pub mod R {}
1104 /// Write-only values (empty)
1105 pub mod W {}
1106 /// Read-write values (empty)
1107 pub mod RW {}
1108 }
1109
1110 /// TXUNDERRIE
1111 pub mod TXUNDERRIE {
1112 /// Offset (4 bits)
1113 pub const offset: u32 = 4;
1114 /// Mask (1 bit: 1 << 4)
1115 pub const mask: u32 = 1 << offset;
1116 /// Read-only values (empty)
1117 pub mod R {}
1118 /// Write-only values (empty)
1119 pub mod W {}
1120 /// Read-write values (empty)
1121 pub mod RW {}
1122 }
1123
1124 /// RXOVERRIE
1125 pub mod RXOVERRIE {
1126 /// Offset (5 bits)
1127 pub const offset: u32 = 5;
1128 /// Mask (1 bit: 1 << 5)
1129 pub const mask: u32 = 1 << offset;
1130 /// Read-only values (empty)
1131 pub mod R {}
1132 /// Write-only values (empty)
1133 pub mod W {}
1134 /// Read-write values (empty)
1135 pub mod RW {}
1136 }
1137
1138 /// CMDRENDIE
1139 pub mod CMDRENDIE {
1140 /// Offset (6 bits)
1141 pub const offset: u32 = 6;
1142 /// Mask (1 bit: 1 << 6)
1143 pub const mask: u32 = 1 << offset;
1144 /// Read-only values (empty)
1145 pub mod R {}
1146 /// Write-only values (empty)
1147 pub mod W {}
1148 /// Read-write values (empty)
1149 pub mod RW {}
1150 }
1151
1152 /// CMDSENTIE
1153 pub mod CMDSENTIE {
1154 /// Offset (7 bits)
1155 pub const offset: u32 = 7;
1156 /// Mask (1 bit: 1 << 7)
1157 pub const mask: u32 = 1 << offset;
1158 /// Read-only values (empty)
1159 pub mod R {}
1160 /// Write-only values (empty)
1161 pub mod W {}
1162 /// Read-write values (empty)
1163 pub mod RW {}
1164 }
1165
1166 /// DATAENDIE
1167 pub mod DATAENDIE {
1168 /// Offset (8 bits)
1169 pub const offset: u32 = 8;
1170 /// Mask (1 bit: 1 << 8)
1171 pub const mask: u32 = 1 << offset;
1172 /// Read-only values (empty)
1173 pub mod R {}
1174 /// Write-only values (empty)
1175 pub mod W {}
1176 /// Read-write values (empty)
1177 pub mod RW {}
1178 }
1179
1180 /// STBITERRIE
1181 pub mod STBITERRIE {
1182 /// Offset (9 bits)
1183 pub const offset: u32 = 9;
1184 /// Mask (1 bit: 1 << 9)
1185 pub const mask: u32 = 1 << offset;
1186 /// Read-only values (empty)
1187 pub mod R {}
1188 /// Write-only values (empty)
1189 pub mod W {}
1190 /// Read-write values (empty)
1191 pub mod RW {}
1192 }
1193
1194 /// DBACKENDIE
1195 pub mod DBACKENDIE {
1196 /// Offset (10 bits)
1197 pub const offset: u32 = 10;
1198 /// Mask (1 bit: 1 << 10)
1199 pub const mask: u32 = 1 << offset;
1200 /// Read-only values (empty)
1201 pub mod R {}
1202 /// Write-only values (empty)
1203 pub mod W {}
1204 /// Read-write values (empty)
1205 pub mod RW {}
1206 }
1207
1208 /// CMDACTIE
1209 pub mod CMDACTIE {
1210 /// Offset (11 bits)
1211 pub const offset: u32 = 11;
1212 /// Mask (1 bit: 1 << 11)
1213 pub const mask: u32 = 1 << offset;
1214 /// Read-only values (empty)
1215 pub mod R {}
1216 /// Write-only values (empty)
1217 pub mod W {}
1218 /// Read-write values (empty)
1219 pub mod RW {}
1220 }
1221
1222 /// TXACTIE
1223 pub mod TXACTIE {
1224 /// Offset (12 bits)
1225 pub const offset: u32 = 12;
1226 /// Mask (1 bit: 1 << 12)
1227 pub const mask: u32 = 1 << offset;
1228 /// Read-only values (empty)
1229 pub mod R {}
1230 /// Write-only values (empty)
1231 pub mod W {}
1232 /// Read-write values (empty)
1233 pub mod RW {}
1234 }
1235
1236 /// RXACTIE
1237 pub mod RXACTIE {
1238 /// Offset (13 bits)
1239 pub const offset: u32 = 13;
1240 /// Mask (1 bit: 1 << 13)
1241 pub const mask: u32 = 1 << offset;
1242 /// Read-only values (empty)
1243 pub mod R {}
1244 /// Write-only values (empty)
1245 pub mod W {}
1246 /// Read-write values (empty)
1247 pub mod RW {}
1248 }
1249
1250 /// TXFIFOHEIE
1251 pub mod TXFIFOHEIE {
1252 /// Offset (14 bits)
1253 pub const offset: u32 = 14;
1254 /// Mask (1 bit: 1 << 14)
1255 pub const mask: u32 = 1 << offset;
1256 /// Read-only values (empty)
1257 pub mod R {}
1258 /// Write-only values (empty)
1259 pub mod W {}
1260 /// Read-write values (empty)
1261 pub mod RW {}
1262 }
1263
1264 /// RXFIFOHFIE
1265 pub mod RXFIFOHFIE {
1266 /// Offset (15 bits)
1267 pub const offset: u32 = 15;
1268 /// Mask (1 bit: 1 << 15)
1269 pub const mask: u32 = 1 << offset;
1270 /// Read-only values (empty)
1271 pub mod R {}
1272 /// Write-only values (empty)
1273 pub mod W {}
1274 /// Read-write values (empty)
1275 pub mod RW {}
1276 }
1277
1278 /// TXFIFOFIE
1279 pub mod TXFIFOFIE {
1280 /// Offset (16 bits)
1281 pub const offset: u32 = 16;
1282 /// Mask (1 bit: 1 << 16)
1283 pub const mask: u32 = 1 << offset;
1284 /// Read-only values (empty)
1285 pub mod R {}
1286 /// Write-only values (empty)
1287 pub mod W {}
1288 /// Read-write values (empty)
1289 pub mod RW {}
1290 }
1291
1292 /// RXFIFOFIE
1293 pub mod RXFIFOFIE {
1294 /// Offset (17 bits)
1295 pub const offset: u32 = 17;
1296 /// Mask (1 bit: 1 << 17)
1297 pub const mask: u32 = 1 << offset;
1298 /// Read-only values (empty)
1299 pub mod R {}
1300 /// Write-only values (empty)
1301 pub mod W {}
1302 /// Read-write values (empty)
1303 pub mod RW {}
1304 }
1305
1306 /// TXFIFOEIE
1307 pub mod TXFIFOEIE {
1308 /// Offset (18 bits)
1309 pub const offset: u32 = 18;
1310 /// Mask (1 bit: 1 << 18)
1311 pub const mask: u32 = 1 << offset;
1312 /// Read-only values (empty)
1313 pub mod R {}
1314 /// Write-only values (empty)
1315 pub mod W {}
1316 /// Read-write values (empty)
1317 pub mod RW {}
1318 }
1319
1320 /// RXFIFOEIE
1321 pub mod RXFIFOEIE {
1322 /// Offset (19 bits)
1323 pub const offset: u32 = 19;
1324 /// Mask (1 bit: 1 << 19)
1325 pub const mask: u32 = 1 << offset;
1326 /// Read-only values (empty)
1327 pub mod R {}
1328 /// Write-only values (empty)
1329 pub mod W {}
1330 /// Read-write values (empty)
1331 pub mod RW {}
1332 }
1333
1334 /// TXDAVLIE
1335 pub mod TXDAVLIE {
1336 /// Offset (20 bits)
1337 pub const offset: u32 = 20;
1338 /// Mask (1 bit: 1 << 20)
1339 pub const mask: u32 = 1 << offset;
1340 /// Read-only values (empty)
1341 pub mod R {}
1342 /// Write-only values (empty)
1343 pub mod W {}
1344 /// Read-write values (empty)
1345 pub mod RW {}
1346 }
1347
1348 /// RXDAVLIE
1349 pub mod RXDAVLIE {
1350 /// Offset (21 bits)
1351 pub const offset: u32 = 21;
1352 /// Mask (1 bit: 1 << 21)
1353 pub const mask: u32 = 1 << offset;
1354 /// Read-only values (empty)
1355 pub mod R {}
1356 /// Write-only values (empty)
1357 pub mod W {}
1358 /// Read-write values (empty)
1359 pub mod RW {}
1360 }
1361
1362 /// SDIOITIE
1363 pub mod SDIOITIE {
1364 /// Offset (22 bits)
1365 pub const offset: u32 = 22;
1366 /// Mask (1 bit: 1 << 22)
1367 pub const mask: u32 = 1 << offset;
1368 /// Read-only values (empty)
1369 pub mod R {}
1370 /// Write-only values (empty)
1371 pub mod W {}
1372 /// Read-write values (empty)
1373 pub mod RW {}
1374 }
1375
1376 /// CEATENDIE
1377 pub mod CEATENDIE {
1378 /// Offset (23 bits)
1379 pub const offset: u32 = 23;
1380 /// Mask (1 bit: 1 << 23)
1381 pub const mask: u32 = 1 << offset;
1382 /// Read-only values (empty)
1383 pub mod R {}
1384 /// Write-only values (empty)
1385 pub mod W {}
1386 /// Read-write values (empty)
1387 pub mod RW {}
1388 }
1389}
1390
1391/// Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the FIFO
1392pub mod FIFOCNT {
1393
1394 /// FIF0COUNT
1395 pub mod FIF0COUNT {
1396 /// Offset (0 bits)
1397 pub const offset: u32 = 0;
1398 /// Mask (24 bits: 0xffffff << 0)
1399 pub const mask: u32 = 0xffffff << offset;
1400 /// Read-only values (empty)
1401 pub mod R {}
1402 /// Write-only values (empty)
1403 pub mod W {}
1404 /// Read-write values (empty)
1405 pub mod RW {}
1406 }
1407}
1408
1409/// bits 31:0 = FIFOData: Receive and transmit FIFO data
1410pub mod FIFO {
1411
1412 /// FIFOData
1413 pub mod FIFOData {
1414 /// Offset (0 bits)
1415 pub const offset: u32 = 0;
1416 /// Mask (32 bits: 0xffffffff << 0)
1417 pub const mask: u32 = 0xffffffff << offset;
1418 /// Read-only values (empty)
1419 pub mod R {}
1420 /// Write-only values (empty)
1421 pub mod W {}
1422 /// Read-write values (empty)
1423 pub mod RW {}
1424 }
1425}
1426#[repr(C)]
1427pub struct RegisterBlock {
1428 /// Bits 1:0 = PWRCTRL: Power supply control bits
1429 pub POWER: RWRegister<u32>,
1430
1431 /// SDI clock control register (SDIO_CLKCR)
1432 pub CLKCR: RWRegister<u32>,
1433
1434 /// Bits 31:0 = : Command argument
1435 pub ARG: RWRegister<u32>,
1436
1437 /// SDIO command register (SDIO_CMD)
1438 pub CMD: RWRegister<u32>,
1439
1440 /// SDIO command register
1441 pub RESPCMD: RORegister<u32>,
1442
1443 /// Bits 31:0 = CARDSTATUS1
1444 pub RESPI1: RORegister<u32>,
1445
1446 /// Bits 31:0 = CARDSTATUS2
1447 pub RESP2: RORegister<u32>,
1448
1449 /// Bits 31:0 = CARDSTATUS2
1450 pub RESP3: RORegister<u32>,
1451
1452 /// Bits 31:0 = CARDSTATUS2
1453 pub RESP4: RORegister<u32>,
1454
1455 /// Bits 31:0 = DATATIME: Data timeout period
1456 pub DTIMER: RWRegister<u32>,
1457
1458 /// Bits 24:0 = DATALENGTH: Data length value
1459 pub DLEN: RWRegister<u32>,
1460
1461 /// SDIO data control register (SDIO_DCTRL)
1462 pub DCTRL: RWRegister<u32>,
1463
1464 /// Bits 24:0 = DATACOUNT: Data count value
1465 pub DCOUNT: RORegister<u32>,
1466
1467 /// SDIO status register (SDIO_STA)
1468 pub STA: RORegister<u32>,
1469
1470 /// SDIO interrupt clear register (SDIO_ICR)
1471 pub ICR: RWRegister<u32>,
1472
1473 /// SDIO mask register (SDIO_MASK)
1474 pub MASK: RWRegister<u32>,
1475
1476 _reserved1: [u8; 8],
1477
1478 /// Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the FIFO
1479 pub FIFOCNT: RORegister<u32>,
1480
1481 _reserved2: [u8; 52],
1482
1483 /// bits 31:0 = FIFOData: Receive and transmit FIFO data
1484 pub FIFO: RWRegister<u32>,
1485}
1486pub struct ResetValues {
1487 pub POWER: u32,
1488 pub CLKCR: u32,
1489 pub ARG: u32,
1490 pub CMD: u32,
1491 pub RESPCMD: u32,
1492 pub RESPI1: u32,
1493 pub RESP2: u32,
1494 pub RESP3: u32,
1495 pub RESP4: u32,
1496 pub DTIMER: u32,
1497 pub DLEN: u32,
1498 pub DCTRL: u32,
1499 pub DCOUNT: u32,
1500 pub STA: u32,
1501 pub ICR: u32,
1502 pub MASK: u32,
1503 pub FIFOCNT: u32,
1504 pub FIFO: u32,
1505}
1506#[cfg(not(feature = "nosync"))]
1507pub struct Instance {
1508 pub(crate) addr: u32,
1509 pub(crate) _marker: PhantomData<*const RegisterBlock>,
1510}
1511#[cfg(not(feature = "nosync"))]
1512impl ::core::ops::Deref for Instance {
1513 type Target = RegisterBlock;
1514 #[inline(always)]
1515 fn deref(&self) -> &RegisterBlock {
1516 unsafe { &*(self.addr as *const _) }
1517 }
1518}
1519#[cfg(feature = "rtic")]
1520unsafe impl Send for Instance {}
1521
1522/// Access functions for the SDIO peripheral instance
1523pub mod SDIO {
1524 use super::ResetValues;
1525
1526 #[cfg(not(feature = "nosync"))]
1527 use super::Instance;
1528
1529 #[cfg(not(feature = "nosync"))]
1530 const INSTANCE: Instance = Instance {
1531 addr: 0x40018000,
1532 _marker: ::core::marker::PhantomData,
1533 };
1534
1535 /// Reset values for each field in SDIO
1536 pub const reset: ResetValues = ResetValues {
1537 POWER: 0x00000000,
1538 CLKCR: 0x00000000,
1539 ARG: 0x00000000,
1540 CMD: 0x00000000,
1541 RESPCMD: 0x00000000,
1542 RESPI1: 0x00000000,
1543 RESP2: 0x00000000,
1544 RESP3: 0x00000000,
1545 RESP4: 0x00000000,
1546 DTIMER: 0x00000000,
1547 DLEN: 0x00000000,
1548 DCTRL: 0x00000000,
1549 DCOUNT: 0x00000000,
1550 STA: 0x00000000,
1551 ICR: 0x00000000,
1552 MASK: 0x00000000,
1553 FIFOCNT: 0x00000000,
1554 FIFO: 0x00000000,
1555 };
1556
1557 #[cfg(not(feature = "nosync"))]
1558 #[allow(renamed_and_removed_lints)]
1559 #[allow(private_no_mangle_statics)]
1560 #[no_mangle]
1561 static mut SDIO_TAKEN: bool = false;
1562
1563 /// Safe access to SDIO
1564 ///
1565 /// This function returns `Some(Instance)` if this instance is not
1566 /// currently taken, and `None` if it is. This ensures that if you
1567 /// do get `Some(Instance)`, you are ensured unique access to
1568 /// the peripheral and there cannot be data races (unless other
1569 /// code uses `unsafe`, of course). You can then pass the
1570 /// `Instance` around to other functions as required. When you're
1571 /// done with it, you can call `release(instance)` to return it.
1572 ///
1573 /// `Instance` itself dereferences to a `RegisterBlock`, which
1574 /// provides access to the peripheral's registers.
1575 #[cfg(not(feature = "nosync"))]
1576 #[inline]
1577 pub fn take() -> Option<Instance> {
1578 external_cortex_m::interrupt::free(|_| unsafe {
1579 if SDIO_TAKEN {
1580 None
1581 } else {
1582 SDIO_TAKEN = true;
1583 Some(INSTANCE)
1584 }
1585 })
1586 }
1587
1588 /// Release exclusive access to SDIO
1589 ///
1590 /// This function allows you to return an `Instance` so that it
1591 /// is available to `take()` again. This function will panic if
1592 /// you return a different `Instance` or if this instance is not
1593 /// already taken.
1594 #[cfg(not(feature = "nosync"))]
1595 #[inline]
1596 pub fn release(inst: Instance) {
1597 external_cortex_m::interrupt::free(|_| unsafe {
1598 if SDIO_TAKEN && inst.addr == INSTANCE.addr {
1599 SDIO_TAKEN = false;
1600 } else {
1601 panic!("Released a peripheral which was not taken");
1602 }
1603 });
1604 }
1605
1606 /// Unsafely steal SDIO
1607 ///
1608 /// This function is similar to take() but forcibly takes the
1609 /// Instance, marking it as taken irregardless of its previous
1610 /// state.
1611 #[cfg(not(feature = "nosync"))]
1612 #[inline]
1613 pub unsafe fn steal() -> Instance {
1614 SDIO_TAKEN = true;
1615 INSTANCE
1616 }
1617}
1618
1619/// Raw pointer to SDIO
1620///
1621/// Dereferencing this is unsafe because you are not ensured unique
1622/// access to the peripheral, so you may encounter data races with
1623/// other users of this peripheral. It is up to you to ensure you
1624/// will not cause data races.
1625///
1626/// This constant is provided for ease of use in unsafe code: you can
1627/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
1628pub const SDIO: *const RegisterBlock = 0x40018000 as *const _;