stm32ral/stm32f1/stm32f103/dbgmcu.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Debug support
4
5use crate::{RORegister, RWRegister};
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// DBGMCU_IDCODE
10pub mod IDCODE {
11
12 /// DEV_ID
13 pub mod DEV_ID {
14 /// Offset (0 bits)
15 pub const offset: u32 = 0;
16 /// Mask (12 bits: 0xfff << 0)
17 pub const mask: u32 = 0xfff << offset;
18 /// Read-only values (empty)
19 pub mod R {}
20 /// Write-only values (empty)
21 pub mod W {}
22 /// Read-write values (empty)
23 pub mod RW {}
24 }
25
26 /// REV_ID
27 pub mod REV_ID {
28 /// Offset (16 bits)
29 pub const offset: u32 = 16;
30 /// Mask (16 bits: 0xffff << 16)
31 pub const mask: u32 = 0xffff << offset;
32 /// Read-only values (empty)
33 pub mod R {}
34 /// Write-only values (empty)
35 pub mod W {}
36 /// Read-write values (empty)
37 pub mod RW {}
38 }
39}
40
41/// DBGMCU_CR
42pub mod CR {
43
44 /// DBG_SLEEP
45 pub mod DBG_SLEEP {
46 /// Offset (0 bits)
47 pub const offset: u32 = 0;
48 /// Mask (1 bit: 1 << 0)
49 pub const mask: u32 = 1 << offset;
50 /// Read-only values (empty)
51 pub mod R {}
52 /// Write-only values (empty)
53 pub mod W {}
54 /// Read-write values (empty)
55 pub mod RW {}
56 }
57
58 /// DBG_STOP
59 pub mod DBG_STOP {
60 /// Offset (1 bits)
61 pub const offset: u32 = 1;
62 /// Mask (1 bit: 1 << 1)
63 pub const mask: u32 = 1 << offset;
64 /// Read-only values (empty)
65 pub mod R {}
66 /// Write-only values (empty)
67 pub mod W {}
68 /// Read-write values (empty)
69 pub mod RW {}
70 }
71
72 /// DBG_STANDBY
73 pub mod DBG_STANDBY {
74 /// Offset (2 bits)
75 pub const offset: u32 = 2;
76 /// Mask (1 bit: 1 << 2)
77 pub const mask: u32 = 1 << offset;
78 /// Read-only values (empty)
79 pub mod R {}
80 /// Write-only values (empty)
81 pub mod W {}
82 /// Read-write values (empty)
83 pub mod RW {}
84 }
85
86 /// TRACE_IOEN
87 pub mod TRACE_IOEN {
88 /// Offset (5 bits)
89 pub const offset: u32 = 5;
90 /// Mask (1 bit: 1 << 5)
91 pub const mask: u32 = 1 << offset;
92 /// Read-only values (empty)
93 pub mod R {}
94 /// Write-only values (empty)
95 pub mod W {}
96 /// Read-write values (empty)
97 pub mod RW {}
98 }
99
100 /// TRACE_MODE
101 pub mod TRACE_MODE {
102 /// Offset (6 bits)
103 pub const offset: u32 = 6;
104 /// Mask (2 bits: 0b11 << 6)
105 pub const mask: u32 = 0b11 << offset;
106 /// Read-only values (empty)
107 pub mod R {}
108 /// Write-only values (empty)
109 pub mod W {}
110 /// Read-write values (empty)
111 pub mod RW {}
112 }
113
114 /// DBG_IWDG_STOP
115 pub mod DBG_IWDG_STOP {
116 /// Offset (8 bits)
117 pub const offset: u32 = 8;
118 /// Mask (1 bit: 1 << 8)
119 pub const mask: u32 = 1 << offset;
120 /// Read-only values (empty)
121 pub mod R {}
122 /// Write-only values (empty)
123 pub mod W {}
124 /// Read-write values (empty)
125 pub mod RW {}
126 }
127
128 /// DBG_WWDG_STOP
129 pub mod DBG_WWDG_STOP {
130 /// Offset (9 bits)
131 pub const offset: u32 = 9;
132 /// Mask (1 bit: 1 << 9)
133 pub const mask: u32 = 1 << offset;
134 /// Read-only values (empty)
135 pub mod R {}
136 /// Write-only values (empty)
137 pub mod W {}
138 /// Read-write values (empty)
139 pub mod RW {}
140 }
141
142 /// DBG_TIM1_STOP
143 pub mod DBG_TIM1_STOP {
144 /// Offset (10 bits)
145 pub const offset: u32 = 10;
146 /// Mask (1 bit: 1 << 10)
147 pub const mask: u32 = 1 << offset;
148 /// Read-only values (empty)
149 pub mod R {}
150 /// Write-only values (empty)
151 pub mod W {}
152 /// Read-write values (empty)
153 pub mod RW {}
154 }
155
156 /// DBG_TIM2_STOP
157 pub mod DBG_TIM2_STOP {
158 /// Offset (11 bits)
159 pub const offset: u32 = 11;
160 /// Mask (1 bit: 1 << 11)
161 pub const mask: u32 = 1 << offset;
162 /// Read-only values (empty)
163 pub mod R {}
164 /// Write-only values (empty)
165 pub mod W {}
166 /// Read-write values (empty)
167 pub mod RW {}
168 }
169
170 /// DBG_TIM3_STOP
171 pub mod DBG_TIM3_STOP {
172 /// Offset (12 bits)
173 pub const offset: u32 = 12;
174 /// Mask (1 bit: 1 << 12)
175 pub const mask: u32 = 1 << offset;
176 /// Read-only values (empty)
177 pub mod R {}
178 /// Write-only values (empty)
179 pub mod W {}
180 /// Read-write values (empty)
181 pub mod RW {}
182 }
183
184 /// DBG_TIM4_STOP
185 pub mod DBG_TIM4_STOP {
186 /// Offset (13 bits)
187 pub const offset: u32 = 13;
188 /// Mask (1 bit: 1 << 13)
189 pub const mask: u32 = 1 << offset;
190 /// Read-only values (empty)
191 pub mod R {}
192 /// Write-only values (empty)
193 pub mod W {}
194 /// Read-write values (empty)
195 pub mod RW {}
196 }
197
198 /// DBG_CAN1_STOP
199 pub mod DBG_CAN1_STOP {
200 /// Offset (14 bits)
201 pub const offset: u32 = 14;
202 /// Mask (1 bit: 1 << 14)
203 pub const mask: u32 = 1 << offset;
204 /// Read-only values (empty)
205 pub mod R {}
206 /// Write-only values (empty)
207 pub mod W {}
208 /// Read-write values (empty)
209 pub mod RW {}
210 }
211
212 /// DBG_I2C1_SMBUS_TIMEOUT
213 pub mod DBG_I2C1_SMBUS_TIMEOUT {
214 /// Offset (15 bits)
215 pub const offset: u32 = 15;
216 /// Mask (1 bit: 1 << 15)
217 pub const mask: u32 = 1 << offset;
218 /// Read-only values (empty)
219 pub mod R {}
220 /// Write-only values (empty)
221 pub mod W {}
222 /// Read-write values (empty)
223 pub mod RW {}
224 }
225
226 /// DBG_I2C2_SMBUS_TIMEOUT
227 pub mod DBG_I2C2_SMBUS_TIMEOUT {
228 /// Offset (16 bits)
229 pub const offset: u32 = 16;
230 /// Mask (1 bit: 1 << 16)
231 pub const mask: u32 = 1 << offset;
232 /// Read-only values (empty)
233 pub mod R {}
234 /// Write-only values (empty)
235 pub mod W {}
236 /// Read-write values (empty)
237 pub mod RW {}
238 }
239
240 /// DBG_TIM8_STOP
241 pub mod DBG_TIM8_STOP {
242 /// Offset (17 bits)
243 pub const offset: u32 = 17;
244 /// Mask (1 bit: 1 << 17)
245 pub const mask: u32 = 1 << offset;
246 /// Read-only values (empty)
247 pub mod R {}
248 /// Write-only values (empty)
249 pub mod W {}
250 /// Read-write values (empty)
251 pub mod RW {}
252 }
253
254 /// DBG_TIM5_STOP
255 pub mod DBG_TIM5_STOP {
256 /// Offset (18 bits)
257 pub const offset: u32 = 18;
258 /// Mask (1 bit: 1 << 18)
259 pub const mask: u32 = 1 << offset;
260 /// Read-only values (empty)
261 pub mod R {}
262 /// Write-only values (empty)
263 pub mod W {}
264 /// Read-write values (empty)
265 pub mod RW {}
266 }
267
268 /// DBG_TIM6_STOP
269 pub mod DBG_TIM6_STOP {
270 /// Offset (19 bits)
271 pub const offset: u32 = 19;
272 /// Mask (1 bit: 1 << 19)
273 pub const mask: u32 = 1 << offset;
274 /// Read-only values (empty)
275 pub mod R {}
276 /// Write-only values (empty)
277 pub mod W {}
278 /// Read-write values (empty)
279 pub mod RW {}
280 }
281
282 /// DBG_TIM7_STOP
283 pub mod DBG_TIM7_STOP {
284 /// Offset (20 bits)
285 pub const offset: u32 = 20;
286 /// Mask (1 bit: 1 << 20)
287 pub const mask: u32 = 1 << offset;
288 /// Read-only values (empty)
289 pub mod R {}
290 /// Write-only values (empty)
291 pub mod W {}
292 /// Read-write values (empty)
293 pub mod RW {}
294 }
295
296 /// DBG_CAN2_STOP
297 pub mod DBG_CAN2_STOP {
298 /// Offset (21 bits)
299 pub const offset: u32 = 21;
300 /// Mask (1 bit: 1 << 21)
301 pub const mask: u32 = 1 << offset;
302 /// Read-only values (empty)
303 pub mod R {}
304 /// Write-only values (empty)
305 pub mod W {}
306 /// Read-write values (empty)
307 pub mod RW {}
308 }
309}
310#[repr(C)]
311pub struct RegisterBlock {
312 /// DBGMCU_IDCODE
313 pub IDCODE: RORegister<u32>,
314
315 /// DBGMCU_CR
316 pub CR: RWRegister<u32>,
317}
318pub struct ResetValues {
319 pub IDCODE: u32,
320 pub CR: u32,
321}
322#[cfg(not(feature = "nosync"))]
323pub struct Instance {
324 pub(crate) addr: u32,
325 pub(crate) _marker: PhantomData<*const RegisterBlock>,
326}
327#[cfg(not(feature = "nosync"))]
328impl ::core::ops::Deref for Instance {
329 type Target = RegisterBlock;
330 #[inline(always)]
331 fn deref(&self) -> &RegisterBlock {
332 unsafe { &*(self.addr as *const _) }
333 }
334}
335#[cfg(feature = "rtic")]
336unsafe impl Send for Instance {}
337
338/// Access functions for the DBGMCU peripheral instance
339pub mod DBGMCU {
340 use super::ResetValues;
341
342 #[cfg(not(feature = "nosync"))]
343 use super::Instance;
344
345 #[cfg(not(feature = "nosync"))]
346 const INSTANCE: Instance = Instance {
347 addr: 0xe0042000,
348 _marker: ::core::marker::PhantomData,
349 };
350
351 /// Reset values for each field in DBGMCU
352 pub const reset: ResetValues = ResetValues {
353 IDCODE: 0x00000000,
354 CR: 0x00000000,
355 };
356
357 #[cfg(not(feature = "nosync"))]
358 #[allow(renamed_and_removed_lints)]
359 #[allow(private_no_mangle_statics)]
360 #[no_mangle]
361 static mut DBGMCU_TAKEN: bool = false;
362
363 /// Safe access to DBGMCU
364 ///
365 /// This function returns `Some(Instance)` if this instance is not
366 /// currently taken, and `None` if it is. This ensures that if you
367 /// do get `Some(Instance)`, you are ensured unique access to
368 /// the peripheral and there cannot be data races (unless other
369 /// code uses `unsafe`, of course). You can then pass the
370 /// `Instance` around to other functions as required. When you're
371 /// done with it, you can call `release(instance)` to return it.
372 ///
373 /// `Instance` itself dereferences to a `RegisterBlock`, which
374 /// provides access to the peripheral's registers.
375 #[cfg(not(feature = "nosync"))]
376 #[inline]
377 pub fn take() -> Option<Instance> {
378 external_cortex_m::interrupt::free(|_| unsafe {
379 if DBGMCU_TAKEN {
380 None
381 } else {
382 DBGMCU_TAKEN = true;
383 Some(INSTANCE)
384 }
385 })
386 }
387
388 /// Release exclusive access to DBGMCU
389 ///
390 /// This function allows you to return an `Instance` so that it
391 /// is available to `take()` again. This function will panic if
392 /// you return a different `Instance` or if this instance is not
393 /// already taken.
394 #[cfg(not(feature = "nosync"))]
395 #[inline]
396 pub fn release(inst: Instance) {
397 external_cortex_m::interrupt::free(|_| unsafe {
398 if DBGMCU_TAKEN && inst.addr == INSTANCE.addr {
399 DBGMCU_TAKEN = false;
400 } else {
401 panic!("Released a peripheral which was not taken");
402 }
403 });
404 }
405
406 /// Unsafely steal DBGMCU
407 ///
408 /// This function is similar to take() but forcibly takes the
409 /// Instance, marking it as taken irregardless of its previous
410 /// state.
411 #[cfg(not(feature = "nosync"))]
412 #[inline]
413 pub unsafe fn steal() -> Instance {
414 DBGMCU_TAKEN = true;
415 INSTANCE
416 }
417}
418
419/// Raw pointer to DBGMCU
420///
421/// Dereferencing this is unsafe because you are not ensured unique
422/// access to the peripheral, so you may encounter data races with
423/// other users of this peripheral. It is up to you to ensure you
424/// will not cause data races.
425///
426/// This constant is provided for ease of use in unsafe code: you can
427/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
428pub const DBGMCU: *const RegisterBlock = 0xe0042000 as *const _;