stm32ral/stm32f1/stm32f101/rcc.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Reset and clock control
4
5use crate::RWRegister;
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// Clock control register
10pub mod CR {
11
12 /// Internal High Speed clock enable
13 pub mod HSION {
14 /// Offset (0 bits)
15 pub const offset: u32 = 0;
16 /// Mask (1 bit: 1 << 0)
17 pub const mask: u32 = 1 << offset;
18 /// Read-only values (empty)
19 pub mod R {}
20 /// Write-only values (empty)
21 pub mod W {}
22 /// Read-write values
23 pub mod RW {
24
25 /// 0b0: Clock Off
26 pub const Off: u32 = 0b0;
27
28 /// 0b1: Clock On
29 pub const On: u32 = 0b1;
30 }
31 }
32
33 /// Internal High Speed clock ready flag
34 pub mod HSIRDY {
35 /// Offset (1 bits)
36 pub const offset: u32 = 1;
37 /// Mask (1 bit: 1 << 1)
38 pub const mask: u32 = 1 << offset;
39 /// Read-only values
40 pub mod R {
41
42 /// 0b0: Clock not ready
43 pub const NotReady: u32 = 0b0;
44
45 /// 0b1: Clock ready
46 pub const Ready: u32 = 0b1;
47 }
48 /// Write-only values (empty)
49 pub mod W {}
50 /// Read-write values (empty)
51 pub mod RW {}
52 }
53
54 /// Internal High Speed clock trimming
55 pub mod HSITRIM {
56 /// Offset (3 bits)
57 pub const offset: u32 = 3;
58 /// Mask (5 bits: 0b11111 << 3)
59 pub const mask: u32 = 0b11111 << offset;
60 /// Read-only values (empty)
61 pub mod R {}
62 /// Write-only values (empty)
63 pub mod W {}
64 /// Read-write values (empty)
65 pub mod RW {}
66 }
67
68 /// Internal High Speed clock Calibration
69 pub mod HSICAL {
70 /// Offset (8 bits)
71 pub const offset: u32 = 8;
72 /// Mask (8 bits: 0xff << 8)
73 pub const mask: u32 = 0xff << offset;
74 /// Read-only values (empty)
75 pub mod R {}
76 /// Write-only values (empty)
77 pub mod W {}
78 /// Read-write values (empty)
79 pub mod RW {}
80 }
81
82 /// External High Speed clock enable
83 pub mod HSEON {
84 /// Offset (16 bits)
85 pub const offset: u32 = 16;
86 /// Mask (1 bit: 1 << 16)
87 pub const mask: u32 = 1 << offset;
88 /// Read-only values (empty)
89 pub mod R {}
90 /// Write-only values (empty)
91 pub mod W {}
92 pub use super::HSION::RW;
93 }
94
95 /// External High Speed clock ready flag
96 pub mod HSERDY {
97 /// Offset (17 bits)
98 pub const offset: u32 = 17;
99 /// Mask (1 bit: 1 << 17)
100 pub const mask: u32 = 1 << offset;
101 pub use super::HSIRDY::R;
102 /// Write-only values (empty)
103 pub mod W {}
104 /// Read-write values (empty)
105 pub mod RW {}
106 }
107
108 /// External High Speed clock Bypass
109 pub mod HSEBYP {
110 /// Offset (18 bits)
111 pub const offset: u32 = 18;
112 /// Mask (1 bit: 1 << 18)
113 pub const mask: u32 = 1 << offset;
114 /// Read-only values (empty)
115 pub mod R {}
116 /// Write-only values (empty)
117 pub mod W {}
118 /// Read-write values
119 pub mod RW {
120
121 /// 0b0: HSE crystal oscillator not bypassed
122 pub const NotBypassed: u32 = 0b0;
123
124 /// 0b1: HSE crystal oscillator bypassed with external clock
125 pub const Bypassed: u32 = 0b1;
126 }
127 }
128
129 /// Clock Security System enable
130 pub mod CSSON {
131 /// Offset (19 bits)
132 pub const offset: u32 = 19;
133 /// Mask (1 bit: 1 << 19)
134 pub const mask: u32 = 1 << offset;
135 /// Read-only values (empty)
136 pub mod R {}
137 /// Write-only values (empty)
138 pub mod W {}
139 /// Read-write values
140 pub mod RW {
141
142 /// 0b0: Clock security system disabled (clock detector OFF)
143 pub const Off: u32 = 0b0;
144
145 /// 0b1: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)
146 pub const On: u32 = 0b1;
147 }
148 }
149
150 /// PLL enable
151 pub mod PLLON {
152 /// Offset (24 bits)
153 pub const offset: u32 = 24;
154 /// Mask (1 bit: 1 << 24)
155 pub const mask: u32 = 1 << offset;
156 /// Read-only values (empty)
157 pub mod R {}
158 /// Write-only values (empty)
159 pub mod W {}
160 pub use super::HSION::RW;
161 }
162
163 /// PLL clock ready flag
164 pub mod PLLRDY {
165 /// Offset (25 bits)
166 pub const offset: u32 = 25;
167 /// Mask (1 bit: 1 << 25)
168 pub const mask: u32 = 1 << offset;
169 pub use super::HSIRDY::R;
170 /// Write-only values (empty)
171 pub mod W {}
172 /// Read-write values (empty)
173 pub mod RW {}
174 }
175}
176
177/// Clock configuration register (RCC_CFGR)
178pub mod CFGR {
179
180 /// System clock Switch
181 pub mod SW {
182 /// Offset (0 bits)
183 pub const offset: u32 = 0;
184 /// Mask (2 bits: 0b11 << 0)
185 pub const mask: u32 = 0b11 << offset;
186 /// Read-only values (empty)
187 pub mod R {}
188 /// Write-only values (empty)
189 pub mod W {}
190 /// Read-write values
191 pub mod RW {
192
193 /// 0b00: HSI selected as system clock
194 pub const HSI: u32 = 0b00;
195
196 /// 0b01: HSE selected as system clock
197 pub const HSE: u32 = 0b01;
198
199 /// 0b10: PLL selected as system clock
200 pub const PLL: u32 = 0b10;
201 }
202 }
203
204 /// System Clock Switch Status
205 pub mod SWS {
206 /// Offset (2 bits)
207 pub const offset: u32 = 2;
208 /// Mask (2 bits: 0b11 << 2)
209 pub const mask: u32 = 0b11 << offset;
210 /// Read-only values
211 pub mod R {
212
213 /// 0b00: HSI oscillator used as system clock
214 pub const HSI: u32 = 0b00;
215
216 /// 0b01: HSE oscillator used as system clock
217 pub const HSE: u32 = 0b01;
218
219 /// 0b10: PLL used as system clock
220 pub const PLL: u32 = 0b10;
221 }
222 /// Write-only values (empty)
223 pub mod W {}
224 /// Read-write values (empty)
225 pub mod RW {}
226 }
227
228 /// AHB prescaler
229 pub mod HPRE {
230 /// Offset (4 bits)
231 pub const offset: u32 = 4;
232 /// Mask (4 bits: 0b1111 << 4)
233 pub const mask: u32 = 0b1111 << offset;
234 /// Read-only values (empty)
235 pub mod R {}
236 /// Write-only values (empty)
237 pub mod W {}
238 /// Read-write values
239 pub mod RW {
240
241 /// 0b0000: SYSCLK not divided
242 pub const Div1: u32 = 0b0000;
243
244 /// 0b1000: SYSCLK divided by 2
245 pub const Div2: u32 = 0b1000;
246
247 /// 0b1001: SYSCLK divided by 4
248 pub const Div4: u32 = 0b1001;
249
250 /// 0b1010: SYSCLK divided by 8
251 pub const Div8: u32 = 0b1010;
252
253 /// 0b1011: SYSCLK divided by 16
254 pub const Div16: u32 = 0b1011;
255
256 /// 0b1100: SYSCLK divided by 64
257 pub const Div64: u32 = 0b1100;
258
259 /// 0b1101: SYSCLK divided by 128
260 pub const Div128: u32 = 0b1101;
261
262 /// 0b1110: SYSCLK divided by 256
263 pub const Div256: u32 = 0b1110;
264
265 /// 0b1111: SYSCLK divided by 512
266 pub const Div512: u32 = 0b1111;
267 }
268 }
269
270 /// APB Low speed prescaler (APB1)
271 pub mod PPRE1 {
272 /// Offset (8 bits)
273 pub const offset: u32 = 8;
274 /// Mask (3 bits: 0b111 << 8)
275 pub const mask: u32 = 0b111 << offset;
276 /// Read-only values (empty)
277 pub mod R {}
278 /// Write-only values (empty)
279 pub mod W {}
280 /// Read-write values
281 pub mod RW {
282
283 /// 0b000: HCLK not divided
284 pub const Div1: u32 = 0b000;
285
286 /// 0b100: HCLK divided by 2
287 pub const Div2: u32 = 0b100;
288
289 /// 0b101: HCLK divided by 4
290 pub const Div4: u32 = 0b101;
291
292 /// 0b110: HCLK divided by 8
293 pub const Div8: u32 = 0b110;
294
295 /// 0b111: HCLK divided by 16
296 pub const Div16: u32 = 0b111;
297 }
298 }
299
300 /// APB High speed prescaler (APB2)
301 pub mod PPRE2 {
302 /// Offset (11 bits)
303 pub const offset: u32 = 11;
304 /// Mask (3 bits: 0b111 << 11)
305 pub const mask: u32 = 0b111 << offset;
306 /// Read-only values (empty)
307 pub mod R {}
308 /// Write-only values (empty)
309 pub mod W {}
310 pub use super::PPRE1::RW;
311 }
312
313 /// ADC prescaler
314 pub mod ADCPRE {
315 /// Offset (14 bits)
316 pub const offset: u32 = 14;
317 /// Mask (2 bits: 0b11 << 14)
318 pub const mask: u32 = 0b11 << offset;
319 /// Read-only values (empty)
320 pub mod R {}
321 /// Write-only values (empty)
322 pub mod W {}
323 /// Read-write values
324 pub mod RW {
325
326 /// 0b00: PCLK2 divided by 2
327 pub const Div2: u32 = 0b00;
328
329 /// 0b01: PCLK2 divided by 4
330 pub const Div4: u32 = 0b01;
331
332 /// 0b10: PCLK2 divided by 8
333 pub const Div6: u32 = 0b10;
334
335 /// 0b11: PCLK2 divided by 16
336 pub const Div8: u32 = 0b11;
337 }
338 }
339
340 /// PLL entry clock source
341 pub mod PLLSRC {
342 /// Offset (16 bits)
343 pub const offset: u32 = 16;
344 /// Mask (1 bit: 1 << 16)
345 pub const mask: u32 = 1 << offset;
346 /// Read-only values (empty)
347 pub mod R {}
348 /// Write-only values (empty)
349 pub mod W {}
350 /// Read-write values
351 pub mod RW {
352
353 /// 0b0: HSI divided by 2 selected as PLL input clock
354 pub const HSI_Div2: u32 = 0b0;
355
356 /// 0b1: HSE divided by PREDIV selected as PLL input clock
357 pub const HSE_Div_PREDIV: u32 = 0b1;
358 }
359 }
360
361 /// HSE divider for PLL entry
362 pub mod PLLXTPRE {
363 /// Offset (17 bits)
364 pub const offset: u32 = 17;
365 /// Mask (1 bit: 1 << 17)
366 pub const mask: u32 = 1 << offset;
367 /// Read-only values (empty)
368 pub mod R {}
369 /// Write-only values (empty)
370 pub mod W {}
371 /// Read-write values
372 pub mod RW {
373
374 /// 0b0: HSE clock not divided
375 pub const Div1: u32 = 0b0;
376
377 /// 0b1: HSE clock divided by 2
378 pub const Div2: u32 = 0b1;
379 }
380 }
381
382 /// PLL Multiplication Factor
383 pub mod PLLMUL {
384 /// Offset (18 bits)
385 pub const offset: u32 = 18;
386 /// Mask (4 bits: 0b1111 << 18)
387 pub const mask: u32 = 0b1111 << offset;
388 /// Read-only values (empty)
389 pub mod R {}
390 /// Write-only values (empty)
391 pub mod W {}
392 /// Read-write values
393 pub mod RW {
394
395 /// 0b0000: PLL input clock x2
396 pub const Mul2: u32 = 0b0000;
397
398 /// 0b0001: PLL input clock x3
399 pub const Mul3: u32 = 0b0001;
400
401 /// 0b0010: PLL input clock x4
402 pub const Mul4: u32 = 0b0010;
403
404 /// 0b0011: PLL input clock x5
405 pub const Mul5: u32 = 0b0011;
406
407 /// 0b0100: PLL input clock x6
408 pub const Mul6: u32 = 0b0100;
409
410 /// 0b0101: PLL input clock x7
411 pub const Mul7: u32 = 0b0101;
412
413 /// 0b0110: PLL input clock x8
414 pub const Mul8: u32 = 0b0110;
415
416 /// 0b0111: PLL input clock x9
417 pub const Mul9: u32 = 0b0111;
418
419 /// 0b1000: PLL input clock x10
420 pub const Mul10: u32 = 0b1000;
421
422 /// 0b1001: PLL input clock x11
423 pub const Mul11: u32 = 0b1001;
424
425 /// 0b1010: PLL input clock x12
426 pub const Mul12: u32 = 0b1010;
427
428 /// 0b1011: PLL input clock x13
429 pub const Mul13: u32 = 0b1011;
430
431 /// 0b1100: PLL input clock x14
432 pub const Mul14: u32 = 0b1100;
433
434 /// 0b1101: PLL input clock x15
435 pub const Mul15: u32 = 0b1101;
436
437 /// 0b1110: PLL input clock x16
438 pub const Mul16: u32 = 0b1110;
439
440 /// 0b1111: PLL input clock x16
441 pub const Mul16x: u32 = 0b1111;
442 }
443 }
444
445 /// Microcontroller clock output
446 pub mod MCO {
447 /// Offset (24 bits)
448 pub const offset: u32 = 24;
449 /// Mask (3 bits: 0b111 << 24)
450 pub const mask: u32 = 0b111 << offset;
451 /// Read-only values (empty)
452 pub mod R {}
453 /// Write-only values (empty)
454 pub mod W {}
455 /// Read-write values
456 pub mod RW {
457
458 /// 0b000: MCO output disabled, no clock on MCO
459 pub const NoMCO: u32 = 0b000;
460
461 /// 0b100: System clock selected
462 pub const SYSCLK: u32 = 0b100;
463
464 /// 0b101: HSI oscillator clock selected
465 pub const HSI: u32 = 0b101;
466
467 /// 0b110: HSE oscillator clock selected
468 pub const HSE: u32 = 0b110;
469
470 /// 0b111: PLL clock selected (divided by 1 or 2, depending en PLLNODIV)
471 pub const PLL: u32 = 0b111;
472 }
473 }
474}
475
476/// Clock interrupt register (RCC_CIR)
477pub mod CIR {
478
479 /// LSI Ready Interrupt flag
480 pub mod LSIRDYF {
481 /// Offset (0 bits)
482 pub const offset: u32 = 0;
483 /// Mask (1 bit: 1 << 0)
484 pub const mask: u32 = 1 << offset;
485 /// Read-only values
486 pub mod R {
487
488 /// 0b0: No clock ready interrupt
489 pub const NotInterrupted: u32 = 0b0;
490
491 /// 0b1: Clock ready interrupt
492 pub const Interrupted: u32 = 0b1;
493 }
494 /// Write-only values (empty)
495 pub mod W {}
496 /// Read-write values (empty)
497 pub mod RW {}
498 }
499
500 /// LSE Ready Interrupt flag
501 pub mod LSERDYF {
502 /// Offset (1 bits)
503 pub const offset: u32 = 1;
504 /// Mask (1 bit: 1 << 1)
505 pub const mask: u32 = 1 << offset;
506 pub use super::LSIRDYF::R;
507 /// Write-only values (empty)
508 pub mod W {}
509 /// Read-write values (empty)
510 pub mod RW {}
511 }
512
513 /// HSI Ready Interrupt flag
514 pub mod HSIRDYF {
515 /// Offset (2 bits)
516 pub const offset: u32 = 2;
517 /// Mask (1 bit: 1 << 2)
518 pub const mask: u32 = 1 << offset;
519 pub use super::LSIRDYF::R;
520 /// Write-only values (empty)
521 pub mod W {}
522 /// Read-write values (empty)
523 pub mod RW {}
524 }
525
526 /// HSE Ready Interrupt flag
527 pub mod HSERDYF {
528 /// Offset (3 bits)
529 pub const offset: u32 = 3;
530 /// Mask (1 bit: 1 << 3)
531 pub const mask: u32 = 1 << offset;
532 pub use super::LSIRDYF::R;
533 /// Write-only values (empty)
534 pub mod W {}
535 /// Read-write values (empty)
536 pub mod RW {}
537 }
538
539 /// PLL Ready Interrupt flag
540 pub mod PLLRDYF {
541 /// Offset (4 bits)
542 pub const offset: u32 = 4;
543 /// Mask (1 bit: 1 << 4)
544 pub const mask: u32 = 1 << offset;
545 pub use super::LSIRDYF::R;
546 /// Write-only values (empty)
547 pub mod W {}
548 /// Read-write values (empty)
549 pub mod RW {}
550 }
551
552 /// Clock Security System Interrupt flag
553 pub mod CSSF {
554 /// Offset (7 bits)
555 pub const offset: u32 = 7;
556 /// Mask (1 bit: 1 << 7)
557 pub const mask: u32 = 1 << offset;
558 /// Read-only values
559 pub mod R {
560
561 /// 0b0: No clock security interrupt caused by HSE clock failure
562 pub const NotInterrupted: u32 = 0b0;
563
564 /// 0b1: Clock security interrupt caused by HSE clock failure
565 pub const Interrupted: u32 = 0b1;
566 }
567 /// Write-only values (empty)
568 pub mod W {}
569 /// Read-write values (empty)
570 pub mod RW {}
571 }
572
573 /// LSI Ready Interrupt Enable
574 pub mod LSIRDYIE {
575 /// Offset (8 bits)
576 pub const offset: u32 = 8;
577 /// Mask (1 bit: 1 << 8)
578 pub const mask: u32 = 1 << offset;
579 /// Read-only values (empty)
580 pub mod R {}
581 /// Write-only values (empty)
582 pub mod W {}
583 /// Read-write values
584 pub mod RW {
585
586 /// 0b0: Interrupt disabled
587 pub const Disabled: u32 = 0b0;
588
589 /// 0b1: Interrupt enabled
590 pub const Enabled: u32 = 0b1;
591 }
592 }
593
594 /// LSE Ready Interrupt Enable
595 pub mod LSERDYIE {
596 /// Offset (9 bits)
597 pub const offset: u32 = 9;
598 /// Mask (1 bit: 1 << 9)
599 pub const mask: u32 = 1 << offset;
600 /// Read-only values (empty)
601 pub mod R {}
602 /// Write-only values (empty)
603 pub mod W {}
604 pub use super::LSIRDYIE::RW;
605 }
606
607 /// HSI Ready Interrupt Enable
608 pub mod HSIRDYIE {
609 /// Offset (10 bits)
610 pub const offset: u32 = 10;
611 /// Mask (1 bit: 1 << 10)
612 pub const mask: u32 = 1 << offset;
613 /// Read-only values (empty)
614 pub mod R {}
615 /// Write-only values (empty)
616 pub mod W {}
617 pub use super::LSIRDYIE::RW;
618 }
619
620 /// HSE Ready Interrupt Enable
621 pub mod HSERDYIE {
622 /// Offset (11 bits)
623 pub const offset: u32 = 11;
624 /// Mask (1 bit: 1 << 11)
625 pub const mask: u32 = 1 << offset;
626 /// Read-only values (empty)
627 pub mod R {}
628 /// Write-only values (empty)
629 pub mod W {}
630 pub use super::LSIRDYIE::RW;
631 }
632
633 /// PLL Ready Interrupt Enable
634 pub mod PLLRDYIE {
635 /// Offset (12 bits)
636 pub const offset: u32 = 12;
637 /// Mask (1 bit: 1 << 12)
638 pub const mask: u32 = 1 << offset;
639 /// Read-only values (empty)
640 pub mod R {}
641 /// Write-only values (empty)
642 pub mod W {}
643 pub use super::LSIRDYIE::RW;
644 }
645
646 /// LSI Ready Interrupt Clear
647 pub mod LSIRDYC {
648 /// Offset (16 bits)
649 pub const offset: u32 = 16;
650 /// Mask (1 bit: 1 << 16)
651 pub const mask: u32 = 1 << offset;
652 /// Read-only values (empty)
653 pub mod R {}
654 /// Write-only values
655 pub mod W {
656
657 /// 0b1: Clear interrupt flag
658 pub const Clear: u32 = 0b1;
659 }
660 /// Read-write values (empty)
661 pub mod RW {}
662 }
663
664 /// LSE Ready Interrupt Clear
665 pub mod LSERDYC {
666 /// Offset (17 bits)
667 pub const offset: u32 = 17;
668 /// Mask (1 bit: 1 << 17)
669 pub const mask: u32 = 1 << offset;
670 /// Read-only values (empty)
671 pub mod R {}
672 pub use super::LSIRDYC::W;
673 /// Read-write values (empty)
674 pub mod RW {}
675 }
676
677 /// HSI Ready Interrupt Clear
678 pub mod HSIRDYC {
679 /// Offset (18 bits)
680 pub const offset: u32 = 18;
681 /// Mask (1 bit: 1 << 18)
682 pub const mask: u32 = 1 << offset;
683 /// Read-only values (empty)
684 pub mod R {}
685 pub use super::LSIRDYC::W;
686 /// Read-write values (empty)
687 pub mod RW {}
688 }
689
690 /// HSE Ready Interrupt Clear
691 pub mod HSERDYC {
692 /// Offset (19 bits)
693 pub const offset: u32 = 19;
694 /// Mask (1 bit: 1 << 19)
695 pub const mask: u32 = 1 << offset;
696 /// Read-only values (empty)
697 pub mod R {}
698 pub use super::LSIRDYC::W;
699 /// Read-write values (empty)
700 pub mod RW {}
701 }
702
703 /// PLL Ready Interrupt Clear
704 pub mod PLLRDYC {
705 /// Offset (20 bits)
706 pub const offset: u32 = 20;
707 /// Mask (1 bit: 1 << 20)
708 pub const mask: u32 = 1 << offset;
709 /// Read-only values (empty)
710 pub mod R {}
711 pub use super::LSIRDYC::W;
712 /// Read-write values (empty)
713 pub mod RW {}
714 }
715
716 /// Clock security system interrupt clear
717 pub mod CSSC {
718 /// Offset (23 bits)
719 pub const offset: u32 = 23;
720 /// Mask (1 bit: 1 << 23)
721 pub const mask: u32 = 1 << offset;
722 /// Read-only values (empty)
723 pub mod R {}
724 /// Write-only values
725 pub mod W {
726
727 /// 0b1: Clear CSSF flag
728 pub const Clear: u32 = 0b1;
729 }
730 /// Read-write values (empty)
731 pub mod RW {}
732 }
733}
734
735/// APB2 peripheral reset register (RCC_APB2RSTR)
736pub mod APB2RSTR {
737
738 /// Alternate function I/O reset
739 pub mod AFIORST {
740 /// Offset (0 bits)
741 pub const offset: u32 = 0;
742 /// Mask (1 bit: 1 << 0)
743 pub const mask: u32 = 1 << offset;
744 /// Read-only values (empty)
745 pub mod R {}
746 /// Write-only values (empty)
747 pub mod W {}
748 /// Read-write values
749 pub mod RW {
750
751 /// 0b1: Reset the selected module
752 pub const Reset: u32 = 0b1;
753 }
754 }
755
756 /// IO port A reset
757 pub mod IOPARST {
758 /// Offset (2 bits)
759 pub const offset: u32 = 2;
760 /// Mask (1 bit: 1 << 2)
761 pub const mask: u32 = 1 << offset;
762 /// Read-only values (empty)
763 pub mod R {}
764 /// Write-only values (empty)
765 pub mod W {}
766 pub use super::AFIORST::RW;
767 }
768
769 /// IO port B reset
770 pub mod IOPBRST {
771 /// Offset (3 bits)
772 pub const offset: u32 = 3;
773 /// Mask (1 bit: 1 << 3)
774 pub const mask: u32 = 1 << offset;
775 /// Read-only values (empty)
776 pub mod R {}
777 /// Write-only values (empty)
778 pub mod W {}
779 pub use super::AFIORST::RW;
780 }
781
782 /// IO port C reset
783 pub mod IOPCRST {
784 /// Offset (4 bits)
785 pub const offset: u32 = 4;
786 /// Mask (1 bit: 1 << 4)
787 pub const mask: u32 = 1 << offset;
788 /// Read-only values (empty)
789 pub mod R {}
790 /// Write-only values (empty)
791 pub mod W {}
792 pub use super::AFIORST::RW;
793 }
794
795 /// IO port D reset
796 pub mod IOPDRST {
797 /// Offset (5 bits)
798 pub const offset: u32 = 5;
799 /// Mask (1 bit: 1 << 5)
800 pub const mask: u32 = 1 << offset;
801 /// Read-only values (empty)
802 pub mod R {}
803 /// Write-only values (empty)
804 pub mod W {}
805 pub use super::AFIORST::RW;
806 }
807
808 /// IO port E reset
809 pub mod IOPERST {
810 /// Offset (6 bits)
811 pub const offset: u32 = 6;
812 /// Mask (1 bit: 1 << 6)
813 pub const mask: u32 = 1 << offset;
814 /// Read-only values (empty)
815 pub mod R {}
816 /// Write-only values (empty)
817 pub mod W {}
818 pub use super::AFIORST::RW;
819 }
820
821 /// ADC 1 interface reset
822 pub mod ADC1RST {
823 /// Offset (9 bits)
824 pub const offset: u32 = 9;
825 /// Mask (1 bit: 1 << 9)
826 pub const mask: u32 = 1 << offset;
827 /// Read-only values (empty)
828 pub mod R {}
829 /// Write-only values (empty)
830 pub mod W {}
831 pub use super::AFIORST::RW;
832 }
833
834 /// SPI 1 reset
835 pub mod SPI1RST {
836 /// Offset (12 bits)
837 pub const offset: u32 = 12;
838 /// Mask (1 bit: 1 << 12)
839 pub const mask: u32 = 1 << offset;
840 /// Read-only values (empty)
841 pub mod R {}
842 /// Write-only values (empty)
843 pub mod W {}
844 pub use super::AFIORST::RW;
845 }
846
847 /// USART1 reset
848 pub mod USART1RST {
849 /// Offset (14 bits)
850 pub const offset: u32 = 14;
851 /// Mask (1 bit: 1 << 14)
852 pub const mask: u32 = 1 << offset;
853 /// Read-only values (empty)
854 pub mod R {}
855 /// Write-only values (empty)
856 pub mod W {}
857 pub use super::AFIORST::RW;
858 }
859
860 /// TIM9 timer reset
861 pub mod TIM9RST {
862 /// Offset (19 bits)
863 pub const offset: u32 = 19;
864 /// Mask (1 bit: 1 << 19)
865 pub const mask: u32 = 1 << offset;
866 /// Read-only values (empty)
867 pub mod R {}
868 /// Write-only values (empty)
869 pub mod W {}
870 pub use super::AFIORST::RW;
871 }
872
873 /// TIM10 timer reset
874 pub mod TIM10RST {
875 /// Offset (20 bits)
876 pub const offset: u32 = 20;
877 /// Mask (1 bit: 1 << 20)
878 pub const mask: u32 = 1 << offset;
879 /// Read-only values (empty)
880 pub mod R {}
881 /// Write-only values (empty)
882 pub mod W {}
883 pub use super::AFIORST::RW;
884 }
885
886 /// TIM11 timer reset
887 pub mod TIM11RST {
888 /// Offset (21 bits)
889 pub const offset: u32 = 21;
890 /// Mask (1 bit: 1 << 21)
891 pub const mask: u32 = 1 << offset;
892 /// Read-only values (empty)
893 pub mod R {}
894 /// Write-only values (empty)
895 pub mod W {}
896 pub use super::AFIORST::RW;
897 }
898
899 /// IO port F reset
900 pub mod IOPFRST {
901 /// Offset (7 bits)
902 pub const offset: u32 = 7;
903 /// Mask (1 bit: 1 << 7)
904 pub const mask: u32 = 1 << offset;
905 /// Read-only values (empty)
906 pub mod R {}
907 /// Write-only values (empty)
908 pub mod W {}
909 pub use super::AFIORST::RW;
910 }
911
912 /// IO port G reset
913 pub mod IOPGRST {
914 /// Offset (8 bits)
915 pub const offset: u32 = 8;
916 /// Mask (1 bit: 1 << 8)
917 pub const mask: u32 = 1 << offset;
918 /// Read-only values (empty)
919 pub mod R {}
920 /// Write-only values (empty)
921 pub mod W {}
922 pub use super::AFIORST::RW;
923 }
924}
925
926/// APB1 peripheral reset register (RCC_APB1RSTR)
927pub mod APB1RSTR {
928
929 /// Timer 2 reset
930 pub mod TIM2RST {
931 /// Offset (0 bits)
932 pub const offset: u32 = 0;
933 /// Mask (1 bit: 1 << 0)
934 pub const mask: u32 = 1 << offset;
935 /// Read-only values (empty)
936 pub mod R {}
937 /// Write-only values (empty)
938 pub mod W {}
939 /// Read-write values
940 pub mod RW {
941
942 /// 0b1: Reset the selected module
943 pub const Reset: u32 = 0b1;
944 }
945 }
946
947 /// Timer 3 reset
948 pub mod TIM3RST {
949 /// Offset (1 bits)
950 pub const offset: u32 = 1;
951 /// Mask (1 bit: 1 << 1)
952 pub const mask: u32 = 1 << offset;
953 /// Read-only values (empty)
954 pub mod R {}
955 /// Write-only values (empty)
956 pub mod W {}
957 pub use super::TIM2RST::RW;
958 }
959
960 /// Timer 4 reset
961 pub mod TIM4RST {
962 /// Offset (2 bits)
963 pub const offset: u32 = 2;
964 /// Mask (1 bit: 1 << 2)
965 pub const mask: u32 = 1 << offset;
966 /// Read-only values (empty)
967 pub mod R {}
968 /// Write-only values (empty)
969 pub mod W {}
970 pub use super::TIM2RST::RW;
971 }
972
973 /// Timer 5 reset
974 pub mod TIM5RST {
975 /// Offset (3 bits)
976 pub const offset: u32 = 3;
977 /// Mask (1 bit: 1 << 3)
978 pub const mask: u32 = 1 << offset;
979 /// Read-only values (empty)
980 pub mod R {}
981 /// Write-only values (empty)
982 pub mod W {}
983 pub use super::TIM2RST::RW;
984 }
985
986 /// Timer 6 reset
987 pub mod TIM6RST {
988 /// Offset (4 bits)
989 pub const offset: u32 = 4;
990 /// Mask (1 bit: 1 << 4)
991 pub const mask: u32 = 1 << offset;
992 /// Read-only values (empty)
993 pub mod R {}
994 /// Write-only values (empty)
995 pub mod W {}
996 pub use super::TIM2RST::RW;
997 }
998
999 /// Timer 7 reset
1000 pub mod TIM7RST {
1001 /// Offset (5 bits)
1002 pub const offset: u32 = 5;
1003 /// Mask (1 bit: 1 << 5)
1004 pub const mask: u32 = 1 << offset;
1005 /// Read-only values (empty)
1006 pub mod R {}
1007 /// Write-only values (empty)
1008 pub mod W {}
1009 pub use super::TIM2RST::RW;
1010 }
1011
1012 /// Timer 12 reset
1013 pub mod TIM12RST {
1014 /// Offset (6 bits)
1015 pub const offset: u32 = 6;
1016 /// Mask (1 bit: 1 << 6)
1017 pub const mask: u32 = 1 << offset;
1018 /// Read-only values (empty)
1019 pub mod R {}
1020 /// Write-only values (empty)
1021 pub mod W {}
1022 pub use super::TIM2RST::RW;
1023 }
1024
1025 /// Timer 13 reset
1026 pub mod TIM13RST {
1027 /// Offset (7 bits)
1028 pub const offset: u32 = 7;
1029 /// Mask (1 bit: 1 << 7)
1030 pub const mask: u32 = 1 << offset;
1031 /// Read-only values (empty)
1032 pub mod R {}
1033 /// Write-only values (empty)
1034 pub mod W {}
1035 pub use super::TIM2RST::RW;
1036 }
1037
1038 /// Timer 14 reset
1039 pub mod TIM14RST {
1040 /// Offset (8 bits)
1041 pub const offset: u32 = 8;
1042 /// Mask (1 bit: 1 << 8)
1043 pub const mask: u32 = 1 << offset;
1044 /// Read-only values (empty)
1045 pub mod R {}
1046 /// Write-only values (empty)
1047 pub mod W {}
1048 pub use super::TIM2RST::RW;
1049 }
1050
1051 /// Window watchdog reset
1052 pub mod WWDGRST {
1053 /// Offset (11 bits)
1054 pub const offset: u32 = 11;
1055 /// Mask (1 bit: 1 << 11)
1056 pub const mask: u32 = 1 << offset;
1057 /// Read-only values (empty)
1058 pub mod R {}
1059 /// Write-only values (empty)
1060 pub mod W {}
1061 pub use super::TIM2RST::RW;
1062 }
1063
1064 /// SPI2 reset
1065 pub mod SPI2RST {
1066 /// Offset (14 bits)
1067 pub const offset: u32 = 14;
1068 /// Mask (1 bit: 1 << 14)
1069 pub const mask: u32 = 1 << offset;
1070 /// Read-only values (empty)
1071 pub mod R {}
1072 /// Write-only values (empty)
1073 pub mod W {}
1074 pub use super::TIM2RST::RW;
1075 }
1076
1077 /// SPI3 reset
1078 pub mod SPI3RST {
1079 /// Offset (15 bits)
1080 pub const offset: u32 = 15;
1081 /// Mask (1 bit: 1 << 15)
1082 pub const mask: u32 = 1 << offset;
1083 /// Read-only values (empty)
1084 pub mod R {}
1085 /// Write-only values (empty)
1086 pub mod W {}
1087 pub use super::TIM2RST::RW;
1088 }
1089
1090 /// USART 2 reset
1091 pub mod USART2RST {
1092 /// Offset (17 bits)
1093 pub const offset: u32 = 17;
1094 /// Mask (1 bit: 1 << 17)
1095 pub const mask: u32 = 1 << offset;
1096 /// Read-only values (empty)
1097 pub mod R {}
1098 /// Write-only values (empty)
1099 pub mod W {}
1100 pub use super::TIM2RST::RW;
1101 }
1102
1103 /// USART 3 reset
1104 pub mod USART3RST {
1105 /// Offset (18 bits)
1106 pub const offset: u32 = 18;
1107 /// Mask (1 bit: 1 << 18)
1108 pub const mask: u32 = 1 << offset;
1109 /// Read-only values (empty)
1110 pub mod R {}
1111 /// Write-only values (empty)
1112 pub mod W {}
1113 pub use super::TIM2RST::RW;
1114 }
1115
1116 /// UART 4 reset
1117 pub mod UART4RST {
1118 /// Offset (19 bits)
1119 pub const offset: u32 = 19;
1120 /// Mask (1 bit: 1 << 19)
1121 pub const mask: u32 = 1 << offset;
1122 /// Read-only values (empty)
1123 pub mod R {}
1124 /// Write-only values (empty)
1125 pub mod W {}
1126 pub use super::TIM2RST::RW;
1127 }
1128
1129 /// UART 5 reset
1130 pub mod UART5RST {
1131 /// Offset (20 bits)
1132 pub const offset: u32 = 20;
1133 /// Mask (1 bit: 1 << 20)
1134 pub const mask: u32 = 1 << offset;
1135 /// Read-only values (empty)
1136 pub mod R {}
1137 /// Write-only values (empty)
1138 pub mod W {}
1139 pub use super::TIM2RST::RW;
1140 }
1141
1142 /// I2C1 reset
1143 pub mod I2C1RST {
1144 /// Offset (21 bits)
1145 pub const offset: u32 = 21;
1146 /// Mask (1 bit: 1 << 21)
1147 pub const mask: u32 = 1 << offset;
1148 /// Read-only values (empty)
1149 pub mod R {}
1150 /// Write-only values (empty)
1151 pub mod W {}
1152 pub use super::TIM2RST::RW;
1153 }
1154
1155 /// I2C2 reset
1156 pub mod I2C2RST {
1157 /// Offset (22 bits)
1158 pub const offset: u32 = 22;
1159 /// Mask (1 bit: 1 << 22)
1160 pub const mask: u32 = 1 << offset;
1161 /// Read-only values (empty)
1162 pub mod R {}
1163 /// Write-only values (empty)
1164 pub mod W {}
1165 pub use super::TIM2RST::RW;
1166 }
1167
1168 /// Backup interface reset
1169 pub mod BKPRST {
1170 /// Offset (27 bits)
1171 pub const offset: u32 = 27;
1172 /// Mask (1 bit: 1 << 27)
1173 pub const mask: u32 = 1 << offset;
1174 /// Read-only values (empty)
1175 pub mod R {}
1176 /// Write-only values (empty)
1177 pub mod W {}
1178 pub use super::TIM2RST::RW;
1179 }
1180
1181 /// Power interface reset
1182 pub mod PWRRST {
1183 /// Offset (28 bits)
1184 pub const offset: u32 = 28;
1185 /// Mask (1 bit: 1 << 28)
1186 pub const mask: u32 = 1 << offset;
1187 /// Read-only values (empty)
1188 pub mod R {}
1189 /// Write-only values (empty)
1190 pub mod W {}
1191 pub use super::TIM2RST::RW;
1192 }
1193
1194 /// DAC interface reset
1195 pub mod DACRST {
1196 /// Offset (29 bits)
1197 pub const offset: u32 = 29;
1198 /// Mask (1 bit: 1 << 29)
1199 pub const mask: u32 = 1 << offset;
1200 /// Read-only values (empty)
1201 pub mod R {}
1202 /// Write-only values (empty)
1203 pub mod W {}
1204 pub use super::TIM2RST::RW;
1205 }
1206}
1207
1208/// AHB Peripheral Clock enable register (RCC_AHBENR)
1209pub mod AHBENR {
1210
1211 /// DMA1 clock enable
1212 pub mod DMA1EN {
1213 /// Offset (0 bits)
1214 pub const offset: u32 = 0;
1215 /// Mask (1 bit: 1 << 0)
1216 pub const mask: u32 = 1 << offset;
1217 /// Read-only values (empty)
1218 pub mod R {}
1219 /// Write-only values (empty)
1220 pub mod W {}
1221 /// Read-write values
1222 pub mod RW {
1223
1224 /// 0b0: The selected clock is disabled
1225 pub const Disabled: u32 = 0b0;
1226
1227 /// 0b1: The selected clock is enabled
1228 pub const Enabled: u32 = 0b1;
1229 }
1230 }
1231
1232 /// DMA2 clock enable
1233 pub mod DMA2EN {
1234 /// Offset (1 bits)
1235 pub const offset: u32 = 1;
1236 /// Mask (1 bit: 1 << 1)
1237 pub const mask: u32 = 1 << offset;
1238 /// Read-only values (empty)
1239 pub mod R {}
1240 /// Write-only values (empty)
1241 pub mod W {}
1242 pub use super::DMA1EN::RW;
1243 }
1244
1245 /// SRAM interface clock enable
1246 pub mod SRAMEN {
1247 /// Offset (2 bits)
1248 pub const offset: u32 = 2;
1249 /// Mask (1 bit: 1 << 2)
1250 pub const mask: u32 = 1 << offset;
1251 /// Read-only values (empty)
1252 pub mod R {}
1253 /// Write-only values (empty)
1254 pub mod W {}
1255 pub use super::DMA1EN::RW;
1256 }
1257
1258 /// FLITF clock enable
1259 pub mod FLITFEN {
1260 /// Offset (4 bits)
1261 pub const offset: u32 = 4;
1262 /// Mask (1 bit: 1 << 4)
1263 pub const mask: u32 = 1 << offset;
1264 /// Read-only values (empty)
1265 pub mod R {}
1266 /// Write-only values (empty)
1267 pub mod W {}
1268 pub use super::DMA1EN::RW;
1269 }
1270
1271 /// CRC clock enable
1272 pub mod CRCEN {
1273 /// Offset (6 bits)
1274 pub const offset: u32 = 6;
1275 /// Mask (1 bit: 1 << 6)
1276 pub const mask: u32 = 1 << offset;
1277 /// Read-only values (empty)
1278 pub mod R {}
1279 /// Write-only values (empty)
1280 pub mod W {}
1281 pub use super::DMA1EN::RW;
1282 }
1283
1284 /// FSMC clock enable
1285 pub mod FSMCEN {
1286 /// Offset (8 bits)
1287 pub const offset: u32 = 8;
1288 /// Mask (1 bit: 1 << 8)
1289 pub const mask: u32 = 1 << offset;
1290 /// Read-only values (empty)
1291 pub mod R {}
1292 /// Write-only values (empty)
1293 pub mod W {}
1294 pub use super::DMA1EN::RW;
1295 }
1296}
1297
1298/// APB2 peripheral clock enable register (RCC_APB2ENR)
1299pub mod APB2ENR {
1300
1301 /// Alternate function I/O clock enable
1302 pub mod AFIOEN {
1303 /// Offset (0 bits)
1304 pub const offset: u32 = 0;
1305 /// Mask (1 bit: 1 << 0)
1306 pub const mask: u32 = 1 << offset;
1307 /// Read-only values (empty)
1308 pub mod R {}
1309 /// Write-only values (empty)
1310 pub mod W {}
1311 /// Read-write values
1312 pub mod RW {
1313
1314 /// 0b0: The selected clock is disabled
1315 pub const Disabled: u32 = 0b0;
1316
1317 /// 0b1: The selected clock is enabled
1318 pub const Enabled: u32 = 0b1;
1319 }
1320 }
1321
1322 /// I/O port A clock enable
1323 pub mod IOPAEN {
1324 /// Offset (2 bits)
1325 pub const offset: u32 = 2;
1326 /// Mask (1 bit: 1 << 2)
1327 pub const mask: u32 = 1 << offset;
1328 /// Read-only values (empty)
1329 pub mod R {}
1330 /// Write-only values (empty)
1331 pub mod W {}
1332 pub use super::AFIOEN::RW;
1333 }
1334
1335 /// I/O port B clock enable
1336 pub mod IOPBEN {
1337 /// Offset (3 bits)
1338 pub const offset: u32 = 3;
1339 /// Mask (1 bit: 1 << 3)
1340 pub const mask: u32 = 1 << offset;
1341 /// Read-only values (empty)
1342 pub mod R {}
1343 /// Write-only values (empty)
1344 pub mod W {}
1345 pub use super::AFIOEN::RW;
1346 }
1347
1348 /// I/O port C clock enable
1349 pub mod IOPCEN {
1350 /// Offset (4 bits)
1351 pub const offset: u32 = 4;
1352 /// Mask (1 bit: 1 << 4)
1353 pub const mask: u32 = 1 << offset;
1354 /// Read-only values (empty)
1355 pub mod R {}
1356 /// Write-only values (empty)
1357 pub mod W {}
1358 pub use super::AFIOEN::RW;
1359 }
1360
1361 /// I/O port D clock enable
1362 pub mod IOPDEN {
1363 /// Offset (5 bits)
1364 pub const offset: u32 = 5;
1365 /// Mask (1 bit: 1 << 5)
1366 pub const mask: u32 = 1 << offset;
1367 /// Read-only values (empty)
1368 pub mod R {}
1369 /// Write-only values (empty)
1370 pub mod W {}
1371 pub use super::AFIOEN::RW;
1372 }
1373
1374 /// I/O port E clock enable
1375 pub mod IOPEEN {
1376 /// Offset (6 bits)
1377 pub const offset: u32 = 6;
1378 /// Mask (1 bit: 1 << 6)
1379 pub const mask: u32 = 1 << offset;
1380 /// Read-only values (empty)
1381 pub mod R {}
1382 /// Write-only values (empty)
1383 pub mod W {}
1384 pub use super::AFIOEN::RW;
1385 }
1386
1387 /// I/O port F clock enable
1388 pub mod IOPFEN {
1389 /// Offset (7 bits)
1390 pub const offset: u32 = 7;
1391 /// Mask (1 bit: 1 << 7)
1392 pub const mask: u32 = 1 << offset;
1393 /// Read-only values (empty)
1394 pub mod R {}
1395 /// Write-only values (empty)
1396 pub mod W {}
1397 pub use super::AFIOEN::RW;
1398 }
1399
1400 /// I/O port G clock enable
1401 pub mod IOPGEN {
1402 /// Offset (8 bits)
1403 pub const offset: u32 = 8;
1404 /// Mask (1 bit: 1 << 8)
1405 pub const mask: u32 = 1 << offset;
1406 /// Read-only values (empty)
1407 pub mod R {}
1408 /// Write-only values (empty)
1409 pub mod W {}
1410 pub use super::AFIOEN::RW;
1411 }
1412
1413 /// ADC 1 interface clock enable
1414 pub mod ADC1EN {
1415 /// Offset (9 bits)
1416 pub const offset: u32 = 9;
1417 /// Mask (1 bit: 1 << 9)
1418 pub const mask: u32 = 1 << offset;
1419 /// Read-only values (empty)
1420 pub mod R {}
1421 /// Write-only values (empty)
1422 pub mod W {}
1423 pub use super::AFIOEN::RW;
1424 }
1425
1426 /// SPI 1 clock enable
1427 pub mod SPI1EN {
1428 /// Offset (12 bits)
1429 pub const offset: u32 = 12;
1430 /// Mask (1 bit: 1 << 12)
1431 pub const mask: u32 = 1 << offset;
1432 /// Read-only values (empty)
1433 pub mod R {}
1434 /// Write-only values (empty)
1435 pub mod W {}
1436 pub use super::AFIOEN::RW;
1437 }
1438
1439 /// USART1 clock enable
1440 pub mod USART1EN {
1441 /// Offset (14 bits)
1442 pub const offset: u32 = 14;
1443 /// Mask (1 bit: 1 << 14)
1444 pub const mask: u32 = 1 << offset;
1445 /// Read-only values (empty)
1446 pub mod R {}
1447 /// Write-only values (empty)
1448 pub mod W {}
1449 pub use super::AFIOEN::RW;
1450 }
1451
1452 /// TIM9 Timer clock enable
1453 pub mod TIM9EN {
1454 /// Offset (19 bits)
1455 pub const offset: u32 = 19;
1456 /// Mask (1 bit: 1 << 19)
1457 pub const mask: u32 = 1 << offset;
1458 /// Read-only values (empty)
1459 pub mod R {}
1460 /// Write-only values (empty)
1461 pub mod W {}
1462 pub use super::AFIOEN::RW;
1463 }
1464
1465 /// TIM10 Timer clock enable
1466 pub mod TIM10EN {
1467 /// Offset (20 bits)
1468 pub const offset: u32 = 20;
1469 /// Mask (1 bit: 1 << 20)
1470 pub const mask: u32 = 1 << offset;
1471 /// Read-only values (empty)
1472 pub mod R {}
1473 /// Write-only values (empty)
1474 pub mod W {}
1475 pub use super::AFIOEN::RW;
1476 }
1477
1478 /// TIM11 Timer clock enable
1479 pub mod TIM11EN {
1480 /// Offset (21 bits)
1481 pub const offset: u32 = 21;
1482 /// Mask (1 bit: 1 << 21)
1483 pub const mask: u32 = 1 << offset;
1484 /// Read-only values (empty)
1485 pub mod R {}
1486 /// Write-only values (empty)
1487 pub mod W {}
1488 pub use super::AFIOEN::RW;
1489 }
1490}
1491
1492/// APB1 peripheral clock enable register (RCC_APB1ENR)
1493pub mod APB1ENR {
1494
1495 /// Timer 2 clock enable
1496 pub mod TIM2EN {
1497 /// Offset (0 bits)
1498 pub const offset: u32 = 0;
1499 /// Mask (1 bit: 1 << 0)
1500 pub const mask: u32 = 1 << offset;
1501 /// Read-only values (empty)
1502 pub mod R {}
1503 /// Write-only values (empty)
1504 pub mod W {}
1505 /// Read-write values
1506 pub mod RW {
1507
1508 /// 0b0: The selected clock is disabled
1509 pub const Disabled: u32 = 0b0;
1510
1511 /// 0b1: The selected clock is enabled
1512 pub const Enabled: u32 = 0b1;
1513 }
1514 }
1515
1516 /// Timer 3 clock enable
1517 pub mod TIM3EN {
1518 /// Offset (1 bits)
1519 pub const offset: u32 = 1;
1520 /// Mask (1 bit: 1 << 1)
1521 pub const mask: u32 = 1 << offset;
1522 /// Read-only values (empty)
1523 pub mod R {}
1524 /// Write-only values (empty)
1525 pub mod W {}
1526 pub use super::TIM2EN::RW;
1527 }
1528
1529 /// Timer 4 clock enable
1530 pub mod TIM4EN {
1531 /// Offset (2 bits)
1532 pub const offset: u32 = 2;
1533 /// Mask (1 bit: 1 << 2)
1534 pub const mask: u32 = 1 << offset;
1535 /// Read-only values (empty)
1536 pub mod R {}
1537 /// Write-only values (empty)
1538 pub mod W {}
1539 pub use super::TIM2EN::RW;
1540 }
1541
1542 /// Timer 5 clock enable
1543 pub mod TIM5EN {
1544 /// Offset (3 bits)
1545 pub const offset: u32 = 3;
1546 /// Mask (1 bit: 1 << 3)
1547 pub const mask: u32 = 1 << offset;
1548 /// Read-only values (empty)
1549 pub mod R {}
1550 /// Write-only values (empty)
1551 pub mod W {}
1552 pub use super::TIM2EN::RW;
1553 }
1554
1555 /// Timer 6 clock enable
1556 pub mod TIM6EN {
1557 /// Offset (4 bits)
1558 pub const offset: u32 = 4;
1559 /// Mask (1 bit: 1 << 4)
1560 pub const mask: u32 = 1 << offset;
1561 /// Read-only values (empty)
1562 pub mod R {}
1563 /// Write-only values (empty)
1564 pub mod W {}
1565 pub use super::TIM2EN::RW;
1566 }
1567
1568 /// Timer 7 clock enable
1569 pub mod TIM7EN {
1570 /// Offset (5 bits)
1571 pub const offset: u32 = 5;
1572 /// Mask (1 bit: 1 << 5)
1573 pub const mask: u32 = 1 << offset;
1574 /// Read-only values (empty)
1575 pub mod R {}
1576 /// Write-only values (empty)
1577 pub mod W {}
1578 pub use super::TIM2EN::RW;
1579 }
1580
1581 /// Timer 12 clock enable
1582 pub mod TIM12EN {
1583 /// Offset (6 bits)
1584 pub const offset: u32 = 6;
1585 /// Mask (1 bit: 1 << 6)
1586 pub const mask: u32 = 1 << offset;
1587 /// Read-only values (empty)
1588 pub mod R {}
1589 /// Write-only values (empty)
1590 pub mod W {}
1591 pub use super::TIM2EN::RW;
1592 }
1593
1594 /// Timer 13 clock enable
1595 pub mod TIM13EN {
1596 /// Offset (7 bits)
1597 pub const offset: u32 = 7;
1598 /// Mask (1 bit: 1 << 7)
1599 pub const mask: u32 = 1 << offset;
1600 /// Read-only values (empty)
1601 pub mod R {}
1602 /// Write-only values (empty)
1603 pub mod W {}
1604 pub use super::TIM2EN::RW;
1605 }
1606
1607 /// Timer 14 clock enable
1608 pub mod TIM14EN {
1609 /// Offset (8 bits)
1610 pub const offset: u32 = 8;
1611 /// Mask (1 bit: 1 << 8)
1612 pub const mask: u32 = 1 << offset;
1613 /// Read-only values (empty)
1614 pub mod R {}
1615 /// Write-only values (empty)
1616 pub mod W {}
1617 pub use super::TIM2EN::RW;
1618 }
1619
1620 /// Window watchdog clock enable
1621 pub mod WWDGEN {
1622 /// Offset (11 bits)
1623 pub const offset: u32 = 11;
1624 /// Mask (1 bit: 1 << 11)
1625 pub const mask: u32 = 1 << offset;
1626 /// Read-only values (empty)
1627 pub mod R {}
1628 /// Write-only values (empty)
1629 pub mod W {}
1630 pub use super::TIM2EN::RW;
1631 }
1632
1633 /// SPI 2 clock enable
1634 pub mod SPI2EN {
1635 /// Offset (14 bits)
1636 pub const offset: u32 = 14;
1637 /// Mask (1 bit: 1 << 14)
1638 pub const mask: u32 = 1 << offset;
1639 /// Read-only values (empty)
1640 pub mod R {}
1641 /// Write-only values (empty)
1642 pub mod W {}
1643 pub use super::TIM2EN::RW;
1644 }
1645
1646 /// SPI 3 clock enable
1647 pub mod SPI3EN {
1648 /// Offset (15 bits)
1649 pub const offset: u32 = 15;
1650 /// Mask (1 bit: 1 << 15)
1651 pub const mask: u32 = 1 << offset;
1652 /// Read-only values (empty)
1653 pub mod R {}
1654 /// Write-only values (empty)
1655 pub mod W {}
1656 pub use super::TIM2EN::RW;
1657 }
1658
1659 /// USART 2 clock enable
1660 pub mod USART2EN {
1661 /// Offset (17 bits)
1662 pub const offset: u32 = 17;
1663 /// Mask (1 bit: 1 << 17)
1664 pub const mask: u32 = 1 << offset;
1665 /// Read-only values (empty)
1666 pub mod R {}
1667 /// Write-only values (empty)
1668 pub mod W {}
1669 pub use super::TIM2EN::RW;
1670 }
1671
1672 /// USART 3 clock enable
1673 pub mod USART3EN {
1674 /// Offset (18 bits)
1675 pub const offset: u32 = 18;
1676 /// Mask (1 bit: 1 << 18)
1677 pub const mask: u32 = 1 << offset;
1678 /// Read-only values (empty)
1679 pub mod R {}
1680 /// Write-only values (empty)
1681 pub mod W {}
1682 pub use super::TIM2EN::RW;
1683 }
1684
1685 /// UART 4 clock enable
1686 pub mod UART4EN {
1687 /// Offset (19 bits)
1688 pub const offset: u32 = 19;
1689 /// Mask (1 bit: 1 << 19)
1690 pub const mask: u32 = 1 << offset;
1691 /// Read-only values (empty)
1692 pub mod R {}
1693 /// Write-only values (empty)
1694 pub mod W {}
1695 pub use super::TIM2EN::RW;
1696 }
1697
1698 /// UART 5 clock enable
1699 pub mod UART5EN {
1700 /// Offset (20 bits)
1701 pub const offset: u32 = 20;
1702 /// Mask (1 bit: 1 << 20)
1703 pub const mask: u32 = 1 << offset;
1704 /// Read-only values (empty)
1705 pub mod R {}
1706 /// Write-only values (empty)
1707 pub mod W {}
1708 pub use super::TIM2EN::RW;
1709 }
1710
1711 /// I2C 1 clock enable
1712 pub mod I2C1EN {
1713 /// Offset (21 bits)
1714 pub const offset: u32 = 21;
1715 /// Mask (1 bit: 1 << 21)
1716 pub const mask: u32 = 1 << offset;
1717 /// Read-only values (empty)
1718 pub mod R {}
1719 /// Write-only values (empty)
1720 pub mod W {}
1721 pub use super::TIM2EN::RW;
1722 }
1723
1724 /// I2C 2 clock enable
1725 pub mod I2C2EN {
1726 /// Offset (22 bits)
1727 pub const offset: u32 = 22;
1728 /// Mask (1 bit: 1 << 22)
1729 pub const mask: u32 = 1 << offset;
1730 /// Read-only values (empty)
1731 pub mod R {}
1732 /// Write-only values (empty)
1733 pub mod W {}
1734 pub use super::TIM2EN::RW;
1735 }
1736
1737 /// Backup interface clock enable
1738 pub mod BKPEN {
1739 /// Offset (27 bits)
1740 pub const offset: u32 = 27;
1741 /// Mask (1 bit: 1 << 27)
1742 pub const mask: u32 = 1 << offset;
1743 /// Read-only values (empty)
1744 pub mod R {}
1745 /// Write-only values (empty)
1746 pub mod W {}
1747 pub use super::TIM2EN::RW;
1748 }
1749
1750 /// Power interface clock enable
1751 pub mod PWREN {
1752 /// Offset (28 bits)
1753 pub const offset: u32 = 28;
1754 /// Mask (1 bit: 1 << 28)
1755 pub const mask: u32 = 1 << offset;
1756 /// Read-only values (empty)
1757 pub mod R {}
1758 /// Write-only values (empty)
1759 pub mod W {}
1760 pub use super::TIM2EN::RW;
1761 }
1762
1763 /// DAC interface clock enable
1764 pub mod DACEN {
1765 /// Offset (29 bits)
1766 pub const offset: u32 = 29;
1767 /// Mask (1 bit: 1 << 29)
1768 pub const mask: u32 = 1 << offset;
1769 /// Read-only values (empty)
1770 pub mod R {}
1771 /// Write-only values (empty)
1772 pub mod W {}
1773 pub use super::TIM2EN::RW;
1774 }
1775}
1776
1777/// Backup domain control register (RCC_BDCR)
1778pub mod BDCR {
1779
1780 /// External Low Speed oscillator enable
1781 pub mod LSEON {
1782 /// Offset (0 bits)
1783 pub const offset: u32 = 0;
1784 /// Mask (1 bit: 1 << 0)
1785 pub const mask: u32 = 1 << offset;
1786 /// Read-only values (empty)
1787 pub mod R {}
1788 /// Write-only values (empty)
1789 pub mod W {}
1790 /// Read-write values
1791 pub mod RW {
1792
1793 /// 0b0: LSE oscillator Off
1794 pub const Off: u32 = 0b0;
1795
1796 /// 0b1: LSE oscillator On
1797 pub const On: u32 = 0b1;
1798 }
1799 }
1800
1801 /// External Low Speed oscillator ready
1802 pub mod LSERDY {
1803 /// Offset (1 bits)
1804 pub const offset: u32 = 1;
1805 /// Mask (1 bit: 1 << 1)
1806 pub const mask: u32 = 1 << offset;
1807 /// Read-only values
1808 pub mod R {
1809
1810 /// 0b0: LSE oscillator not ready
1811 pub const NotReady: u32 = 0b0;
1812
1813 /// 0b1: LSE oscillator ready
1814 pub const Ready: u32 = 0b1;
1815 }
1816 /// Write-only values (empty)
1817 pub mod W {}
1818 /// Read-write values (empty)
1819 pub mod RW {}
1820 }
1821
1822 /// External Low Speed oscillator bypass
1823 pub mod LSEBYP {
1824 /// Offset (2 bits)
1825 pub const offset: u32 = 2;
1826 /// Mask (1 bit: 1 << 2)
1827 pub const mask: u32 = 1 << offset;
1828 /// Read-only values (empty)
1829 pub mod R {}
1830 /// Write-only values (empty)
1831 pub mod W {}
1832 /// Read-write values
1833 pub mod RW {
1834
1835 /// 0b0: LSE crystal oscillator not bypassed
1836 pub const NotBypassed: u32 = 0b0;
1837
1838 /// 0b1: LSE crystal oscillator bypassed with external clock
1839 pub const Bypassed: u32 = 0b1;
1840 }
1841 }
1842
1843 /// RTC clock source selection
1844 pub mod RTCSEL {
1845 /// Offset (8 bits)
1846 pub const offset: u32 = 8;
1847 /// Mask (2 bits: 0b11 << 8)
1848 pub const mask: u32 = 0b11 << offset;
1849 /// Read-only values (empty)
1850 pub mod R {}
1851 /// Write-only values (empty)
1852 pub mod W {}
1853 /// Read-write values
1854 pub mod RW {
1855
1856 /// 0b00: No clock
1857 pub const NoClock: u32 = 0b00;
1858
1859 /// 0b01: LSE oscillator clock used as RTC clock
1860 pub const LSE: u32 = 0b01;
1861
1862 /// 0b10: LSI oscillator clock used as RTC clock
1863 pub const LSI: u32 = 0b10;
1864
1865 /// 0b11: HSE oscillator clock divided by a prescaler used as RTC clock
1866 pub const HSE: u32 = 0b11;
1867 }
1868 }
1869
1870 /// RTC clock enable
1871 pub mod RTCEN {
1872 /// Offset (15 bits)
1873 pub const offset: u32 = 15;
1874 /// Mask (1 bit: 1 << 15)
1875 pub const mask: u32 = 1 << offset;
1876 /// Read-only values (empty)
1877 pub mod R {}
1878 /// Write-only values (empty)
1879 pub mod W {}
1880 /// Read-write values
1881 pub mod RW {
1882
1883 /// 0b0: RTC clock disabled
1884 pub const Disabled: u32 = 0b0;
1885
1886 /// 0b1: RTC clock enabled
1887 pub const Enabled: u32 = 0b1;
1888 }
1889 }
1890
1891 /// Backup domain software reset
1892 pub mod BDRST {
1893 /// Offset (16 bits)
1894 pub const offset: u32 = 16;
1895 /// Mask (1 bit: 1 << 16)
1896 pub const mask: u32 = 1 << offset;
1897 /// Read-only values (empty)
1898 pub mod R {}
1899 /// Write-only values (empty)
1900 pub mod W {}
1901 /// Read-write values
1902 pub mod RW {
1903
1904 /// 0b0: Reset not activated
1905 pub const Disabled: u32 = 0b0;
1906
1907 /// 0b1: Reset the entire RTC domain
1908 pub const Enabled: u32 = 0b1;
1909 }
1910 }
1911}
1912
1913/// Control/status register (RCC_CSR)
1914pub mod CSR {
1915
1916 /// Internal low speed oscillator enable
1917 pub mod LSION {
1918 /// Offset (0 bits)
1919 pub const offset: u32 = 0;
1920 /// Mask (1 bit: 1 << 0)
1921 pub const mask: u32 = 1 << offset;
1922 /// Read-only values (empty)
1923 pub mod R {}
1924 /// Write-only values (empty)
1925 pub mod W {}
1926 /// Read-write values
1927 pub mod RW {
1928
1929 /// 0b0: LSI oscillator Off
1930 pub const Off: u32 = 0b0;
1931
1932 /// 0b1: LSI oscillator On
1933 pub const On: u32 = 0b1;
1934 }
1935 }
1936
1937 /// Internal low speed oscillator ready
1938 pub mod LSIRDY {
1939 /// Offset (1 bits)
1940 pub const offset: u32 = 1;
1941 /// Mask (1 bit: 1 << 1)
1942 pub const mask: u32 = 1 << offset;
1943 /// Read-only values
1944 pub mod R {
1945
1946 /// 0b0: LSI oscillator not ready
1947 pub const NotReady: u32 = 0b0;
1948
1949 /// 0b1: LSI oscillator ready
1950 pub const Ready: u32 = 0b1;
1951 }
1952 /// Write-only values (empty)
1953 pub mod W {}
1954 /// Read-write values (empty)
1955 pub mod RW {}
1956 }
1957
1958 /// Remove reset flag
1959 pub mod RMVF {
1960 /// Offset (24 bits)
1961 pub const offset: u32 = 24;
1962 /// Mask (1 bit: 1 << 24)
1963 pub const mask: u32 = 1 << offset;
1964 /// Read-only values (empty)
1965 pub mod R {}
1966 /// Write-only values
1967 pub mod W {
1968
1969 /// 0b1: Clears the reset flag
1970 pub const Clear: u32 = 0b1;
1971 }
1972 /// Read-write values (empty)
1973 pub mod RW {}
1974 }
1975
1976 /// PIN reset flag
1977 pub mod PINRSTF {
1978 /// Offset (26 bits)
1979 pub const offset: u32 = 26;
1980 /// Mask (1 bit: 1 << 26)
1981 pub const mask: u32 = 1 << offset;
1982 /// Read-only values
1983 pub mod R {
1984
1985 /// 0b0: No reset has occured
1986 pub const NoReset: u32 = 0b0;
1987
1988 /// 0b1: A reset has occured
1989 pub const Reset: u32 = 0b1;
1990 }
1991 /// Write-only values (empty)
1992 pub mod W {}
1993 /// Read-write values (empty)
1994 pub mod RW {}
1995 }
1996
1997 /// POR/PDR reset flag
1998 pub mod PORRSTF {
1999 /// Offset (27 bits)
2000 pub const offset: u32 = 27;
2001 /// Mask (1 bit: 1 << 27)
2002 pub const mask: u32 = 1 << offset;
2003 pub use super::PINRSTF::R;
2004 /// Write-only values (empty)
2005 pub mod W {}
2006 /// Read-write values (empty)
2007 pub mod RW {}
2008 }
2009
2010 /// Software reset flag
2011 pub mod SFTRSTF {
2012 /// Offset (28 bits)
2013 pub const offset: u32 = 28;
2014 /// Mask (1 bit: 1 << 28)
2015 pub const mask: u32 = 1 << offset;
2016 pub use super::PINRSTF::R;
2017 /// Write-only values (empty)
2018 pub mod W {}
2019 /// Read-write values (empty)
2020 pub mod RW {}
2021 }
2022
2023 /// Independent watchdog reset flag
2024 pub mod IWDGRSTF {
2025 /// Offset (29 bits)
2026 pub const offset: u32 = 29;
2027 /// Mask (1 bit: 1 << 29)
2028 pub const mask: u32 = 1 << offset;
2029 pub use super::PINRSTF::R;
2030 /// Write-only values (empty)
2031 pub mod W {}
2032 /// Read-write values (empty)
2033 pub mod RW {}
2034 }
2035
2036 /// Window watchdog reset flag
2037 pub mod WWDGRSTF {
2038 /// Offset (30 bits)
2039 pub const offset: u32 = 30;
2040 /// Mask (1 bit: 1 << 30)
2041 pub const mask: u32 = 1 << offset;
2042 pub use super::PINRSTF::R;
2043 /// Write-only values (empty)
2044 pub mod W {}
2045 /// Read-write values (empty)
2046 pub mod RW {}
2047 }
2048
2049 /// Low-power reset flag
2050 pub mod LPWRRSTF {
2051 /// Offset (31 bits)
2052 pub const offset: u32 = 31;
2053 /// Mask (1 bit: 1 << 31)
2054 pub const mask: u32 = 1 << offset;
2055 pub use super::PINRSTF::R;
2056 /// Write-only values (empty)
2057 pub mod W {}
2058 /// Read-write values (empty)
2059 pub mod RW {}
2060 }
2061}
2062#[repr(C)]
2063pub struct RegisterBlock {
2064 /// Clock control register
2065 pub CR: RWRegister<u32>,
2066
2067 /// Clock configuration register (RCC_CFGR)
2068 pub CFGR: RWRegister<u32>,
2069
2070 /// Clock interrupt register (RCC_CIR)
2071 pub CIR: RWRegister<u32>,
2072
2073 /// APB2 peripheral reset register (RCC_APB2RSTR)
2074 pub APB2RSTR: RWRegister<u32>,
2075
2076 /// APB1 peripheral reset register (RCC_APB1RSTR)
2077 pub APB1RSTR: RWRegister<u32>,
2078
2079 /// AHB Peripheral Clock enable register (RCC_AHBENR)
2080 pub AHBENR: RWRegister<u32>,
2081
2082 /// APB2 peripheral clock enable register (RCC_APB2ENR)
2083 pub APB2ENR: RWRegister<u32>,
2084
2085 /// APB1 peripheral clock enable register (RCC_APB1ENR)
2086 pub APB1ENR: RWRegister<u32>,
2087
2088 /// Backup domain control register (RCC_BDCR)
2089 pub BDCR: RWRegister<u32>,
2090
2091 /// Control/status register (RCC_CSR)
2092 pub CSR: RWRegister<u32>,
2093}
2094pub struct ResetValues {
2095 pub CR: u32,
2096 pub CFGR: u32,
2097 pub CIR: u32,
2098 pub APB2RSTR: u32,
2099 pub APB1RSTR: u32,
2100 pub AHBENR: u32,
2101 pub APB2ENR: u32,
2102 pub APB1ENR: u32,
2103 pub BDCR: u32,
2104 pub CSR: u32,
2105}
2106#[cfg(not(feature = "nosync"))]
2107pub struct Instance {
2108 pub(crate) addr: u32,
2109 pub(crate) _marker: PhantomData<*const RegisterBlock>,
2110}
2111#[cfg(not(feature = "nosync"))]
2112impl ::core::ops::Deref for Instance {
2113 type Target = RegisterBlock;
2114 #[inline(always)]
2115 fn deref(&self) -> &RegisterBlock {
2116 unsafe { &*(self.addr as *const _) }
2117 }
2118}
2119#[cfg(feature = "rtic")]
2120unsafe impl Send for Instance {}
2121
2122/// Access functions for the RCC peripheral instance
2123pub mod RCC {
2124 use super::ResetValues;
2125
2126 #[cfg(not(feature = "nosync"))]
2127 use super::Instance;
2128
2129 #[cfg(not(feature = "nosync"))]
2130 const INSTANCE: Instance = Instance {
2131 addr: 0x40021000,
2132 _marker: ::core::marker::PhantomData,
2133 };
2134
2135 /// Reset values for each field in RCC
2136 pub const reset: ResetValues = ResetValues {
2137 CR: 0x00000083,
2138 CFGR: 0x00000000,
2139 CIR: 0x00000000,
2140 APB2RSTR: 0x00000000,
2141 APB1RSTR: 0x00000000,
2142 AHBENR: 0x00000014,
2143 APB2ENR: 0x00000000,
2144 APB1ENR: 0x00000000,
2145 BDCR: 0x00000000,
2146 CSR: 0x0C000000,
2147 };
2148
2149 #[cfg(not(feature = "nosync"))]
2150 #[allow(renamed_and_removed_lints)]
2151 #[allow(private_no_mangle_statics)]
2152 #[no_mangle]
2153 static mut RCC_TAKEN: bool = false;
2154
2155 /// Safe access to RCC
2156 ///
2157 /// This function returns `Some(Instance)` if this instance is not
2158 /// currently taken, and `None` if it is. This ensures that if you
2159 /// do get `Some(Instance)`, you are ensured unique access to
2160 /// the peripheral and there cannot be data races (unless other
2161 /// code uses `unsafe`, of course). You can then pass the
2162 /// `Instance` around to other functions as required. When you're
2163 /// done with it, you can call `release(instance)` to return it.
2164 ///
2165 /// `Instance` itself dereferences to a `RegisterBlock`, which
2166 /// provides access to the peripheral's registers.
2167 #[cfg(not(feature = "nosync"))]
2168 #[inline]
2169 pub fn take() -> Option<Instance> {
2170 external_cortex_m::interrupt::free(|_| unsafe {
2171 if RCC_TAKEN {
2172 None
2173 } else {
2174 RCC_TAKEN = true;
2175 Some(INSTANCE)
2176 }
2177 })
2178 }
2179
2180 /// Release exclusive access to RCC
2181 ///
2182 /// This function allows you to return an `Instance` so that it
2183 /// is available to `take()` again. This function will panic if
2184 /// you return a different `Instance` or if this instance is not
2185 /// already taken.
2186 #[cfg(not(feature = "nosync"))]
2187 #[inline]
2188 pub fn release(inst: Instance) {
2189 external_cortex_m::interrupt::free(|_| unsafe {
2190 if RCC_TAKEN && inst.addr == INSTANCE.addr {
2191 RCC_TAKEN = false;
2192 } else {
2193 panic!("Released a peripheral which was not taken");
2194 }
2195 });
2196 }
2197
2198 /// Unsafely steal RCC
2199 ///
2200 /// This function is similar to take() but forcibly takes the
2201 /// Instance, marking it as taken irregardless of its previous
2202 /// state.
2203 #[cfg(not(feature = "nosync"))]
2204 #[inline]
2205 pub unsafe fn steal() -> Instance {
2206 RCC_TAKEN = true;
2207 INSTANCE
2208 }
2209}
2210
2211/// Raw pointer to RCC
2212///
2213/// Dereferencing this is unsafe because you are not ensured unique
2214/// access to the peripheral, so you may encounter data races with
2215/// other users of this peripheral. It is up to you to ensure you
2216/// will not cause data races.
2217///
2218/// This constant is provided for ease of use in unsafe code: you can
2219/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
2220pub const RCC: *const RegisterBlock = 0x40021000 as *const _;