stm32ral/stm32f1/stm32f100/
tim17.rs

1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! General-purpose-timers
4
5#[cfg(not(feature = "nosync"))]
6pub use crate::stm32f1::peripherals::tim16::Instance;
7pub use crate::stm32f1::peripherals::tim16::{RegisterBlock, ResetValues};
8pub use crate::stm32f1::peripherals::tim16::{
9    ARR, BDTR, CCER, CCMR1, CCR1, CNT, CR1, CR2, DCR, DIER, DMAR, EGR, PSC, RCR, SR,
10};
11
12/// Access functions for the TIM17 peripheral instance
13pub mod TIM17 {
14    use super::ResetValues;
15
16    #[cfg(not(feature = "nosync"))]
17    use super::Instance;
18
19    #[cfg(not(feature = "nosync"))]
20    const INSTANCE: Instance = Instance {
21        addr: 0x40014800,
22        _marker: ::core::marker::PhantomData,
23    };
24
25    /// Reset values for each field in TIM17
26    pub const reset: ResetValues = ResetValues {
27        CR1: 0x00000000,
28        CR2: 0x00000000,
29        DIER: 0x00000000,
30        SR: 0x00000000,
31        EGR: 0x00000000,
32        CCMR1: 0x00000000,
33        CCER: 0x00000000,
34        CNT: 0x00000000,
35        PSC: 0x00000000,
36        ARR: 0x00000000,
37        RCR: 0x00000000,
38        CCR1: 0x00000000,
39        BDTR: 0x00000000,
40        DCR: 0x00000000,
41        DMAR: 0x00000000,
42    };
43
44    #[cfg(not(feature = "nosync"))]
45    #[allow(renamed_and_removed_lints)]
46    #[allow(private_no_mangle_statics)]
47    #[no_mangle]
48    static mut TIM17_TAKEN: bool = false;
49
50    /// Safe access to TIM17
51    ///
52    /// This function returns `Some(Instance)` if this instance is not
53    /// currently taken, and `None` if it is. This ensures that if you
54    /// do get `Some(Instance)`, you are ensured unique access to
55    /// the peripheral and there cannot be data races (unless other
56    /// code uses `unsafe`, of course). You can then pass the
57    /// `Instance` around to other functions as required. When you're
58    /// done with it, you can call `release(instance)` to return it.
59    ///
60    /// `Instance` itself dereferences to a `RegisterBlock`, which
61    /// provides access to the peripheral's registers.
62    #[cfg(not(feature = "nosync"))]
63    #[inline]
64    pub fn take() -> Option<Instance> {
65        external_cortex_m::interrupt::free(|_| unsafe {
66            if TIM17_TAKEN {
67                None
68            } else {
69                TIM17_TAKEN = true;
70                Some(INSTANCE)
71            }
72        })
73    }
74
75    /// Release exclusive access to TIM17
76    ///
77    /// This function allows you to return an `Instance` so that it
78    /// is available to `take()` again. This function will panic if
79    /// you return a different `Instance` or if this instance is not
80    /// already taken.
81    #[cfg(not(feature = "nosync"))]
82    #[inline]
83    pub fn release(inst: Instance) {
84        external_cortex_m::interrupt::free(|_| unsafe {
85            if TIM17_TAKEN && inst.addr == INSTANCE.addr {
86                TIM17_TAKEN = false;
87            } else {
88                panic!("Released a peripheral which was not taken");
89            }
90        });
91    }
92
93    /// Unsafely steal TIM17
94    ///
95    /// This function is similar to take() but forcibly takes the
96    /// Instance, marking it as taken irregardless of its previous
97    /// state.
98    #[cfg(not(feature = "nosync"))]
99    #[inline]
100    pub unsafe fn steal() -> Instance {
101        TIM17_TAKEN = true;
102        INSTANCE
103    }
104}
105
106/// Raw pointer to TIM17
107///
108/// Dereferencing this is unsafe because you are not ensured unique
109/// access to the peripheral, so you may encounter data races with
110/// other users of this peripheral. It is up to you to ensure you
111/// will not cause data races.
112///
113/// This constant is provided for ease of use in unsafe code: you can
114/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
115pub const TIM17: *const RegisterBlock = 0x40014800 as *const _;
stm32ral/stm32f1/stm32f100/tim17.rs

stm32ral/stm32f1/stm32f100/
tim17.rs
