stm32ral/stm32f1/peripherals/tim1_v2.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Advanced timer
4//!
5//! Used by: stm32f103, stm32f107
6
7use crate::{RWRegister, WORegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// control register 1
12pub mod CR1 {
13
14 /// Clock division
15 pub mod CKD {
16 /// Offset (8 bits)
17 pub const offset: u32 = 8;
18 /// Mask (2 bits: 0b11 << 8)
19 pub const mask: u32 = 0b11 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values
25 pub mod RW {
26
27 /// 0b00: t_DTS = t_CK_INT
28 pub const Div1: u32 = 0b00;
29
30 /// 0b01: t_DTS = 2 × t_CK_INT
31 pub const Div2: u32 = 0b01;
32
33 /// 0b10: t_DTS = 4 × t_CK_INT
34 pub const Div4: u32 = 0b10;
35 }
36 }
37
38 /// Auto-reload preload enable
39 pub mod ARPE {
40 /// Offset (7 bits)
41 pub const offset: u32 = 7;
42 /// Mask (1 bit: 1 << 7)
43 pub const mask: u32 = 1 << offset;
44 /// Read-only values (empty)
45 pub mod R {}
46 /// Write-only values (empty)
47 pub mod W {}
48 /// Read-write values
49 pub mod RW {
50
51 /// 0b0: TIMx_APRR register is not buffered
52 pub const Disabled: u32 = 0b0;
53
54 /// 0b1: TIMx_APRR register is buffered
55 pub const Enabled: u32 = 0b1;
56 }
57 }
58
59 /// Center-aligned mode selection
60 pub mod CMS {
61 /// Offset (5 bits)
62 pub const offset: u32 = 5;
63 /// Mask (2 bits: 0b11 << 5)
64 pub const mask: u32 = 0b11 << offset;
65 /// Read-only values (empty)
66 pub mod R {}
67 /// Write-only values (empty)
68 pub mod W {}
69 /// Read-write values
70 pub mod RW {
71
72 /// 0b00: The counter counts up or down depending on the direction bit
73 pub const EdgeAligned: u32 = 0b00;
74
75 /// 0b01: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
76 pub const CenterAligned1: u32 = 0b01;
77
78 /// 0b10: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
79 pub const CenterAligned2: u32 = 0b10;
80
81 /// 0b11: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
82 pub const CenterAligned3: u32 = 0b11;
83 }
84 }
85
86 /// Direction
87 pub mod DIR {
88 /// Offset (4 bits)
89 pub const offset: u32 = 4;
90 /// Mask (1 bit: 1 << 4)
91 pub const mask: u32 = 1 << offset;
92 /// Read-only values (empty)
93 pub mod R {}
94 /// Write-only values (empty)
95 pub mod W {}
96 /// Read-write values
97 pub mod RW {
98
99 /// 0b0: Counter used as upcounter
100 pub const Up: u32 = 0b0;
101
102 /// 0b1: Counter used as downcounter
103 pub const Down: u32 = 0b1;
104 }
105 }
106
107 /// One-pulse mode
108 pub mod OPM {
109 /// Offset (3 bits)
110 pub const offset: u32 = 3;
111 /// Mask (1 bit: 1 << 3)
112 pub const mask: u32 = 1 << offset;
113 /// Read-only values (empty)
114 pub mod R {}
115 /// Write-only values (empty)
116 pub mod W {}
117 /// Read-write values
118 pub mod RW {
119
120 /// 0b0: Counter is not stopped at update event
121 pub const Disabled: u32 = 0b0;
122
123 /// 0b1: Counter stops counting at the next update event (clearing the CEN bit)
124 pub const Enabled: u32 = 0b1;
125 }
126 }
127
128 /// Update request source
129 pub mod URS {
130 /// Offset (2 bits)
131 pub const offset: u32 = 2;
132 /// Mask (1 bit: 1 << 2)
133 pub const mask: u32 = 1 << offset;
134 /// Read-only values (empty)
135 pub mod R {}
136 /// Write-only values (empty)
137 pub mod W {}
138 /// Read-write values
139 pub mod RW {
140
141 /// 0b0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
142 pub const AnyEvent: u32 = 0b0;
143
144 /// 0b1: Only counter overflow/underflow generates an update interrupt or DMA request
145 pub const CounterOnly: u32 = 0b1;
146 }
147 }
148
149 /// Update disable
150 pub mod UDIS {
151 /// Offset (1 bits)
152 pub const offset: u32 = 1;
153 /// Mask (1 bit: 1 << 1)
154 pub const mask: u32 = 1 << offset;
155 /// Read-only values (empty)
156 pub mod R {}
157 /// Write-only values (empty)
158 pub mod W {}
159 /// Read-write values
160 pub mod RW {
161
162 /// 0b0: Update event enabled
163 pub const Enabled: u32 = 0b0;
164
165 /// 0b1: Update event disabled
166 pub const Disabled: u32 = 0b1;
167 }
168 }
169
170 /// Counter enable
171 pub mod CEN {
172 /// Offset (0 bits)
173 pub const offset: u32 = 0;
174 /// Mask (1 bit: 1 << 0)
175 pub const mask: u32 = 1 << offset;
176 /// Read-only values (empty)
177 pub mod R {}
178 /// Write-only values (empty)
179 pub mod W {}
180 /// Read-write values
181 pub mod RW {
182
183 /// 0b0: Counter disabled
184 pub const Disabled: u32 = 0b0;
185
186 /// 0b1: Counter enabled
187 pub const Enabled: u32 = 0b1;
188 }
189 }
190}
191
192/// control register 2
193pub mod CR2 {
194
195 /// Output Idle state 4
196 pub mod OIS4 {
197 /// Offset (14 bits)
198 pub const offset: u32 = 14;
199 /// Mask (1 bit: 1 << 14)
200 pub const mask: u32 = 1 << offset;
201 /// Read-only values (empty)
202 pub mod R {}
203 /// Write-only values (empty)
204 pub mod W {}
205 /// Read-write values (empty)
206 pub mod RW {}
207 }
208
209 /// Output Idle state 3
210 pub mod OIS3N {
211 /// Offset (13 bits)
212 pub const offset: u32 = 13;
213 /// Mask (1 bit: 1 << 13)
214 pub const mask: u32 = 1 << offset;
215 /// Read-only values (empty)
216 pub mod R {}
217 /// Write-only values (empty)
218 pub mod W {}
219 /// Read-write values (empty)
220 pub mod RW {}
221 }
222
223 /// Output Idle state 3
224 pub mod OIS3 {
225 /// Offset (12 bits)
226 pub const offset: u32 = 12;
227 /// Mask (1 bit: 1 << 12)
228 pub const mask: u32 = 1 << offset;
229 /// Read-only values (empty)
230 pub mod R {}
231 /// Write-only values (empty)
232 pub mod W {}
233 /// Read-write values (empty)
234 pub mod RW {}
235 }
236
237 /// Output Idle state 2
238 pub mod OIS2N {
239 /// Offset (11 bits)
240 pub const offset: u32 = 11;
241 /// Mask (1 bit: 1 << 11)
242 pub const mask: u32 = 1 << offset;
243 /// Read-only values (empty)
244 pub mod R {}
245 /// Write-only values (empty)
246 pub mod W {}
247 /// Read-write values (empty)
248 pub mod RW {}
249 }
250
251 /// Output Idle state 2
252 pub mod OIS2 {
253 /// Offset (10 bits)
254 pub const offset: u32 = 10;
255 /// Mask (1 bit: 1 << 10)
256 pub const mask: u32 = 1 << offset;
257 /// Read-only values (empty)
258 pub mod R {}
259 /// Write-only values (empty)
260 pub mod W {}
261 /// Read-write values (empty)
262 pub mod RW {}
263 }
264
265 /// Output Idle state 1
266 pub mod OIS1N {
267 /// Offset (9 bits)
268 pub const offset: u32 = 9;
269 /// Mask (1 bit: 1 << 9)
270 pub const mask: u32 = 1 << offset;
271 /// Read-only values (empty)
272 pub mod R {}
273 /// Write-only values (empty)
274 pub mod W {}
275 /// Read-write values (empty)
276 pub mod RW {}
277 }
278
279 /// Output Idle state 1
280 pub mod OIS1 {
281 /// Offset (8 bits)
282 pub const offset: u32 = 8;
283 /// Mask (1 bit: 1 << 8)
284 pub const mask: u32 = 1 << offset;
285 /// Read-only values (empty)
286 pub mod R {}
287 /// Write-only values (empty)
288 pub mod W {}
289 /// Read-write values (empty)
290 pub mod RW {}
291 }
292
293 /// TI1 selection
294 pub mod TI1S {
295 /// Offset (7 bits)
296 pub const offset: u32 = 7;
297 /// Mask (1 bit: 1 << 7)
298 pub const mask: u32 = 1 << offset;
299 /// Read-only values (empty)
300 pub mod R {}
301 /// Write-only values (empty)
302 pub mod W {}
303 /// Read-write values
304 pub mod RW {
305
306 /// 0b0: The TIMx_CH1 pin is connected to TI1 input
307 pub const Normal: u32 = 0b0;
308
309 /// 0b1: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
310 pub const XOR: u32 = 0b1;
311 }
312 }
313
314 /// Master mode selection
315 pub mod MMS {
316 /// Offset (4 bits)
317 pub const offset: u32 = 4;
318 /// Mask (3 bits: 0b111 << 4)
319 pub const mask: u32 = 0b111 << offset;
320 /// Read-only values (empty)
321 pub mod R {}
322 /// Write-only values (empty)
323 pub mod W {}
324 /// Read-write values
325 pub mod RW {
326
327 /// 0b000: The UG bit from the TIMx_EGR register is used as trigger output
328 pub const Reset: u32 = 0b000;
329
330 /// 0b001: The counter enable signal, CNT_EN, is used as trigger output
331 pub const Enable: u32 = 0b001;
332
333 /// 0b010: The update event is selected as trigger output
334 pub const Update: u32 = 0b010;
335
336 /// 0b011: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
337 pub const ComparePulse: u32 = 0b011;
338
339 /// 0b100: OC1REF signal is used as trigger output
340 pub const CompareOC1: u32 = 0b100;
341
342 /// 0b101: OC2REF signal is used as trigger output
343 pub const CompareOC2: u32 = 0b101;
344
345 /// 0b110: OC3REF signal is used as trigger output
346 pub const CompareOC3: u32 = 0b110;
347
348 /// 0b111: OC4REF signal is used as trigger output
349 pub const CompareOC4: u32 = 0b111;
350 }
351 }
352
353 /// Capture/compare DMA selection
354 pub mod CCDS {
355 /// Offset (3 bits)
356 pub const offset: u32 = 3;
357 /// Mask (1 bit: 1 << 3)
358 pub const mask: u32 = 1 << offset;
359 /// Read-only values (empty)
360 pub mod R {}
361 /// Write-only values (empty)
362 pub mod W {}
363 /// Read-write values
364 pub mod RW {
365
366 /// 0b0: CCx DMA request sent when CCx event occurs
367 pub const OnCompare: u32 = 0b0;
368
369 /// 0b1: CCx DMA request sent when update event occurs
370 pub const OnUpdate: u32 = 0b1;
371 }
372 }
373
374 /// Capture/compare control update selection
375 pub mod CCUS {
376 /// Offset (2 bits)
377 pub const offset: u32 = 2;
378 /// Mask (1 bit: 1 << 2)
379 pub const mask: u32 = 1 << offset;
380 /// Read-only values (empty)
381 pub mod R {}
382 /// Write-only values (empty)
383 pub mod W {}
384 /// Read-write values (empty)
385 pub mod RW {}
386 }
387
388 /// Capture/compare preloaded control
389 pub mod CCPC {
390 /// Offset (0 bits)
391 pub const offset: u32 = 0;
392 /// Mask (1 bit: 1 << 0)
393 pub const mask: u32 = 1 << offset;
394 /// Read-only values (empty)
395 pub mod R {}
396 /// Write-only values (empty)
397 pub mod W {}
398 /// Read-write values (empty)
399 pub mod RW {}
400 }
401}
402
403/// slave mode control register
404pub mod SMCR {
405
406 /// External trigger polarity
407 pub mod ETP {
408 /// Offset (15 bits)
409 pub const offset: u32 = 15;
410 /// Mask (1 bit: 1 << 15)
411 pub const mask: u32 = 1 << offset;
412 /// Read-only values (empty)
413 pub mod R {}
414 /// Write-only values (empty)
415 pub mod W {}
416 /// Read-write values
417 pub mod RW {
418
419 /// 0b0: ETR is noninverted, active at high level or rising edge
420 pub const NotInverted: u32 = 0b0;
421
422 /// 0b1: ETR is inverted, active at low level or falling edge
423 pub const Inverted: u32 = 0b1;
424 }
425 }
426
427 /// External clock enable
428 pub mod ECE {
429 /// Offset (14 bits)
430 pub const offset: u32 = 14;
431 /// Mask (1 bit: 1 << 14)
432 pub const mask: u32 = 1 << offset;
433 /// Read-only values (empty)
434 pub mod R {}
435 /// Write-only values (empty)
436 pub mod W {}
437 /// Read-write values
438 pub mod RW {
439
440 /// 0b0: External clock mode 2 disabled
441 pub const Disabled: u32 = 0b0;
442
443 /// 0b1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
444 pub const Enabled: u32 = 0b1;
445 }
446 }
447
448 /// External trigger prescaler
449 pub mod ETPS {
450 /// Offset (12 bits)
451 pub const offset: u32 = 12;
452 /// Mask (2 bits: 0b11 << 12)
453 pub const mask: u32 = 0b11 << offset;
454 /// Read-only values (empty)
455 pub mod R {}
456 /// Write-only values (empty)
457 pub mod W {}
458 /// Read-write values
459 pub mod RW {
460
461 /// 0b00: Prescaler OFF
462 pub const Div1: u32 = 0b00;
463
464 /// 0b01: ETRP frequency divided by 2
465 pub const Div2: u32 = 0b01;
466
467 /// 0b10: ETRP frequency divided by 4
468 pub const Div4: u32 = 0b10;
469
470 /// 0b11: ETRP frequency divided by 8
471 pub const Div8: u32 = 0b11;
472 }
473 }
474
475 /// External trigger filter
476 pub mod ETF {
477 /// Offset (8 bits)
478 pub const offset: u32 = 8;
479 /// Mask (4 bits: 0b1111 << 8)
480 pub const mask: u32 = 0b1111 << offset;
481 /// Read-only values (empty)
482 pub mod R {}
483 /// Write-only values (empty)
484 pub mod W {}
485 /// Read-write values
486 pub mod RW {
487
488 /// 0b0000: No filter, sampling is done at fDTS
489 pub const NoFilter: u32 = 0b0000;
490
491 /// 0b0001: fSAMPLING=fCK_INT, N=2
492 pub const FCK_INT_N2: u32 = 0b0001;
493
494 /// 0b0010: fSAMPLING=fCK_INT, N=4
495 pub const FCK_INT_N4: u32 = 0b0010;
496
497 /// 0b0011: fSAMPLING=fCK_INT, N=8
498 pub const FCK_INT_N8: u32 = 0b0011;
499
500 /// 0b0100: fSAMPLING=fDTS/2, N=6
501 pub const FDTS_Div2_N6: u32 = 0b0100;
502
503 /// 0b0101: fSAMPLING=fDTS/2, N=8
504 pub const FDTS_Div2_N8: u32 = 0b0101;
505
506 /// 0b0110: fSAMPLING=fDTS/4, N=6
507 pub const FDTS_Div4_N6: u32 = 0b0110;
508
509 /// 0b0111: fSAMPLING=fDTS/4, N=8
510 pub const FDTS_Div4_N8: u32 = 0b0111;
511
512 /// 0b1000: fSAMPLING=fDTS/8, N=6
513 pub const FDTS_Div8_N6: u32 = 0b1000;
514
515 /// 0b1001: fSAMPLING=fDTS/8, N=8
516 pub const FDTS_Div8_N8: u32 = 0b1001;
517
518 /// 0b1010: fSAMPLING=fDTS/16, N=5
519 pub const FDTS_Div16_N5: u32 = 0b1010;
520
521 /// 0b1011: fSAMPLING=fDTS/16, N=6
522 pub const FDTS_Div16_N6: u32 = 0b1011;
523
524 /// 0b1100: fSAMPLING=fDTS/16, N=8
525 pub const FDTS_Div16_N8: u32 = 0b1100;
526
527 /// 0b1101: fSAMPLING=fDTS/32, N=5
528 pub const FDTS_Div32_N5: u32 = 0b1101;
529
530 /// 0b1110: fSAMPLING=fDTS/32, N=6
531 pub const FDTS_Div32_N6: u32 = 0b1110;
532
533 /// 0b1111: fSAMPLING=fDTS/32, N=8
534 pub const FDTS_Div32_N8: u32 = 0b1111;
535 }
536 }
537
538 /// Master/Slave mode
539 pub mod MSM {
540 /// Offset (7 bits)
541 pub const offset: u32 = 7;
542 /// Mask (1 bit: 1 << 7)
543 pub const mask: u32 = 1 << offset;
544 /// Read-only values (empty)
545 pub mod R {}
546 /// Write-only values (empty)
547 pub mod W {}
548 /// Read-write values
549 pub mod RW {
550
551 /// 0b0: No action
552 pub const NoSync: u32 = 0b0;
553
554 /// 0b1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
555 pub const Sync: u32 = 0b1;
556 }
557 }
558
559 /// Trigger selection
560 pub mod TS {
561 /// Offset (4 bits)
562 pub const offset: u32 = 4;
563 /// Mask (3 bits: 0b111 << 4)
564 pub const mask: u32 = 0b111 << offset;
565 /// Read-only values (empty)
566 pub mod R {}
567 /// Write-only values (empty)
568 pub mod W {}
569 /// Read-write values
570 pub mod RW {
571
572 /// 0b000: Internal Trigger 0 (ITR0)
573 pub const ITR0: u32 = 0b000;
574
575 /// 0b001: Internal Trigger 1 (ITR1)
576 pub const ITR1: u32 = 0b001;
577
578 /// 0b010: Internal Trigger 2 (ITR2)
579 pub const ITR2: u32 = 0b010;
580
581 /// 0b100: TI1 Edge Detector (TI1F_ED)
582 pub const TI1F_ED: u32 = 0b100;
583
584 /// 0b101: Filtered Timer Input 1 (TI1FP1)
585 pub const TI1FP1: u32 = 0b101;
586
587 /// 0b110: Filtered Timer Input 2 (TI2FP2)
588 pub const TI2FP2: u32 = 0b110;
589
590 /// 0b111: External Trigger input (ETRF)
591 pub const ETRF: u32 = 0b111;
592 }
593 }
594
595 /// Slave mode selection
596 pub mod SMS {
597 /// Offset (0 bits)
598 pub const offset: u32 = 0;
599 /// Mask (3 bits: 0b111 << 0)
600 pub const mask: u32 = 0b111 << offset;
601 /// Read-only values (empty)
602 pub mod R {}
603 /// Write-only values (empty)
604 pub mod W {}
605 /// Read-write values
606 pub mod RW {
607
608 /// 0b000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
609 pub const Disabled: u32 = 0b000;
610
611 /// 0b001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
612 pub const Encoder_Mode_1: u32 = 0b001;
613
614 /// 0b010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
615 pub const Encoder_Mode_2: u32 = 0b010;
616
617 /// 0b011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
618 pub const Encoder_Mode_3: u32 = 0b011;
619
620 /// 0b100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
621 pub const Reset_Mode: u32 = 0b100;
622
623 /// 0b101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
624 pub const Gated_Mode: u32 = 0b101;
625
626 /// 0b110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
627 pub const Trigger_Mode: u32 = 0b110;
628
629 /// 0b111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
630 pub const Ext_Clock_Mode: u32 = 0b111;
631 }
632 }
633}
634
635/// DMA/Interrupt enable register
636pub mod DIER {
637
638 /// Trigger DMA request enable
639 pub mod TDE {
640 /// Offset (14 bits)
641 pub const offset: u32 = 14;
642 /// Mask (1 bit: 1 << 14)
643 pub const mask: u32 = 1 << offset;
644 /// Read-only values (empty)
645 pub mod R {}
646 /// Write-only values (empty)
647 pub mod W {}
648 /// Read-write values
649 pub mod RW {
650
651 /// 0b0: Trigger DMA request disabled
652 pub const Disabled: u32 = 0b0;
653
654 /// 0b1: Trigger DMA request enabled
655 pub const Enabled: u32 = 0b1;
656 }
657 }
658
659 /// COM DMA request enable
660 pub mod COMDE {
661 /// Offset (13 bits)
662 pub const offset: u32 = 13;
663 /// Mask (1 bit: 1 << 13)
664 pub const mask: u32 = 1 << offset;
665 /// Read-only values (empty)
666 pub mod R {}
667 /// Write-only values (empty)
668 pub mod W {}
669 /// Read-write values (empty)
670 pub mod RW {}
671 }
672
673 /// Capture/Compare 4 DMA request enable
674 pub mod CC4DE {
675 /// Offset (12 bits)
676 pub const offset: u32 = 12;
677 /// Mask (1 bit: 1 << 12)
678 pub const mask: u32 = 1 << offset;
679 /// Read-only values (empty)
680 pub mod R {}
681 /// Write-only values (empty)
682 pub mod W {}
683 /// Read-write values
684 pub mod RW {
685
686 /// 0b0: CCx DMA request disabled
687 pub const Disabled: u32 = 0b0;
688
689 /// 0b1: CCx DMA request enabled
690 pub const Enabled: u32 = 0b1;
691 }
692 }
693
694 /// Capture/Compare 3 DMA request enable
695 pub mod CC3DE {
696 /// Offset (11 bits)
697 pub const offset: u32 = 11;
698 /// Mask (1 bit: 1 << 11)
699 pub const mask: u32 = 1 << offset;
700 /// Read-only values (empty)
701 pub mod R {}
702 /// Write-only values (empty)
703 pub mod W {}
704 pub use super::CC4DE::RW;
705 }
706
707 /// Capture/Compare 2 DMA request enable
708 pub mod CC2DE {
709 /// Offset (10 bits)
710 pub const offset: u32 = 10;
711 /// Mask (1 bit: 1 << 10)
712 pub const mask: u32 = 1 << offset;
713 /// Read-only values (empty)
714 pub mod R {}
715 /// Write-only values (empty)
716 pub mod W {}
717 pub use super::CC4DE::RW;
718 }
719
720 /// Capture/Compare 1 DMA request enable
721 pub mod CC1DE {
722 /// Offset (9 bits)
723 pub const offset: u32 = 9;
724 /// Mask (1 bit: 1 << 9)
725 pub const mask: u32 = 1 << offset;
726 /// Read-only values (empty)
727 pub mod R {}
728 /// Write-only values (empty)
729 pub mod W {}
730 pub use super::CC4DE::RW;
731 }
732
733 /// Update DMA request enable
734 pub mod UDE {
735 /// Offset (8 bits)
736 pub const offset: u32 = 8;
737 /// Mask (1 bit: 1 << 8)
738 pub const mask: u32 = 1 << offset;
739 /// Read-only values (empty)
740 pub mod R {}
741 /// Write-only values (empty)
742 pub mod W {}
743 /// Read-write values
744 pub mod RW {
745
746 /// 0b0: Update DMA request disabled
747 pub const Disabled: u32 = 0b0;
748
749 /// 0b1: Update DMA request enabled
750 pub const Enabled: u32 = 0b1;
751 }
752 }
753
754 /// Trigger interrupt enable
755 pub mod TIE {
756 /// Offset (6 bits)
757 pub const offset: u32 = 6;
758 /// Mask (1 bit: 1 << 6)
759 pub const mask: u32 = 1 << offset;
760 /// Read-only values (empty)
761 pub mod R {}
762 /// Write-only values (empty)
763 pub mod W {}
764 /// Read-write values
765 pub mod RW {
766
767 /// 0b0: Trigger interrupt disabled
768 pub const Disabled: u32 = 0b0;
769
770 /// 0b1: Trigger interrupt enabled
771 pub const Enabled: u32 = 0b1;
772 }
773 }
774
775 /// Capture/Compare 4 interrupt enable
776 pub mod CC4IE {
777 /// Offset (4 bits)
778 pub const offset: u32 = 4;
779 /// Mask (1 bit: 1 << 4)
780 pub const mask: u32 = 1 << offset;
781 /// Read-only values (empty)
782 pub mod R {}
783 /// Write-only values (empty)
784 pub mod W {}
785 /// Read-write values
786 pub mod RW {
787
788 /// 0b0: CCx interrupt disabled
789 pub const Disabled: u32 = 0b0;
790
791 /// 0b1: CCx interrupt enabled
792 pub const Enabled: u32 = 0b1;
793 }
794 }
795
796 /// Capture/Compare 3 interrupt enable
797 pub mod CC3IE {
798 /// Offset (3 bits)
799 pub const offset: u32 = 3;
800 /// Mask (1 bit: 1 << 3)
801 pub const mask: u32 = 1 << offset;
802 /// Read-only values (empty)
803 pub mod R {}
804 /// Write-only values (empty)
805 pub mod W {}
806 pub use super::CC4IE::RW;
807 }
808
809 /// Capture/Compare 2 interrupt enable
810 pub mod CC2IE {
811 /// Offset (2 bits)
812 pub const offset: u32 = 2;
813 /// Mask (1 bit: 1 << 2)
814 pub const mask: u32 = 1 << offset;
815 /// Read-only values (empty)
816 pub mod R {}
817 /// Write-only values (empty)
818 pub mod W {}
819 pub use super::CC4IE::RW;
820 }
821
822 /// Capture/Compare 1 interrupt enable
823 pub mod CC1IE {
824 /// Offset (1 bits)
825 pub const offset: u32 = 1;
826 /// Mask (1 bit: 1 << 1)
827 pub const mask: u32 = 1 << offset;
828 /// Read-only values (empty)
829 pub mod R {}
830 /// Write-only values (empty)
831 pub mod W {}
832 pub use super::CC4IE::RW;
833 }
834
835 /// Update interrupt enable
836 pub mod UIE {
837 /// Offset (0 bits)
838 pub const offset: u32 = 0;
839 /// Mask (1 bit: 1 << 0)
840 pub const mask: u32 = 1 << offset;
841 /// Read-only values (empty)
842 pub mod R {}
843 /// Write-only values (empty)
844 pub mod W {}
845 /// Read-write values
846 pub mod RW {
847
848 /// 0b0: Update interrupt disabled
849 pub const Disabled: u32 = 0b0;
850
851 /// 0b1: Update interrupt enabled
852 pub const Enabled: u32 = 0b1;
853 }
854 }
855
856 /// Break interrupt enable
857 pub mod BIE {
858 /// Offset (7 bits)
859 pub const offset: u32 = 7;
860 /// Mask (1 bit: 1 << 7)
861 pub const mask: u32 = 1 << offset;
862 /// Read-only values (empty)
863 pub mod R {}
864 /// Write-only values (empty)
865 pub mod W {}
866 /// Read-write values (empty)
867 pub mod RW {}
868 }
869
870 /// COM interrupt enable
871 pub mod COMIE {
872 /// Offset (5 bits)
873 pub const offset: u32 = 5;
874 /// Mask (1 bit: 1 << 5)
875 pub const mask: u32 = 1 << offset;
876 /// Read-only values (empty)
877 pub mod R {}
878 /// Write-only values (empty)
879 pub mod W {}
880 /// Read-write values (empty)
881 pub mod RW {}
882 }
883}
884
885/// status register
886pub mod SR {
887
888 /// Capture/Compare 4 overcapture flag
889 pub mod CC4OF {
890 /// Offset (12 bits)
891 pub const offset: u32 = 12;
892 /// Mask (1 bit: 1 << 12)
893 pub const mask: u32 = 1 << offset;
894 /// Read-only values
895 pub mod R {
896
897 /// 0b1: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
898 pub const Overcapture: u32 = 0b1;
899 }
900 /// Write-only values
901 pub mod W {
902
903 /// 0b0: Clear flag
904 pub const Clear: u32 = 0b0;
905 }
906 /// Read-write values (empty)
907 pub mod RW {}
908 }
909
910 /// Capture/Compare 3 overcapture flag
911 pub mod CC3OF {
912 /// Offset (11 bits)
913 pub const offset: u32 = 11;
914 /// Mask (1 bit: 1 << 11)
915 pub const mask: u32 = 1 << offset;
916 pub use super::CC4OF::R;
917 pub use super::CC4OF::W;
918 /// Read-write values (empty)
919 pub mod RW {}
920 }
921
922 /// Capture/compare 2 overcapture flag
923 pub mod CC2OF {
924 /// Offset (10 bits)
925 pub const offset: u32 = 10;
926 /// Mask (1 bit: 1 << 10)
927 pub const mask: u32 = 1 << offset;
928 pub use super::CC4OF::R;
929 pub use super::CC4OF::W;
930 /// Read-write values (empty)
931 pub mod RW {}
932 }
933
934 /// Capture/Compare 1 overcapture flag
935 pub mod CC1OF {
936 /// Offset (9 bits)
937 pub const offset: u32 = 9;
938 /// Mask (1 bit: 1 << 9)
939 pub const mask: u32 = 1 << offset;
940 pub use super::CC4OF::R;
941 pub use super::CC4OF::W;
942 /// Read-write values (empty)
943 pub mod RW {}
944 }
945
946 /// Break interrupt flag
947 pub mod BIF {
948 /// Offset (7 bits)
949 pub const offset: u32 = 7;
950 /// Mask (1 bit: 1 << 7)
951 pub const mask: u32 = 1 << offset;
952 /// Read-only values (empty)
953 pub mod R {}
954 /// Write-only values (empty)
955 pub mod W {}
956 /// Read-write values (empty)
957 pub mod RW {}
958 }
959
960 /// Trigger interrupt flag
961 pub mod TIF {
962 /// Offset (6 bits)
963 pub const offset: u32 = 6;
964 /// Mask (1 bit: 1 << 6)
965 pub const mask: u32 = 1 << offset;
966 /// Read-only values
967 pub mod R {
968
969 /// 0b0: No trigger event occurred
970 pub const NoTrigger: u32 = 0b0;
971
972 /// 0b1: Trigger interrupt pending
973 pub const Trigger: u32 = 0b1;
974 }
975 pub use super::CC4OF::W;
976 /// Read-write values (empty)
977 pub mod RW {}
978 }
979
980 /// COM interrupt flag
981 pub mod COMIF {
982 /// Offset (5 bits)
983 pub const offset: u32 = 5;
984 /// Mask (1 bit: 1 << 5)
985 pub const mask: u32 = 1 << offset;
986 /// Read-only values (empty)
987 pub mod R {}
988 /// Write-only values (empty)
989 pub mod W {}
990 /// Read-write values (empty)
991 pub mod RW {}
992 }
993
994 /// Capture/Compare 4 interrupt flag
995 pub mod CC4IF {
996 /// Offset (4 bits)
997 pub const offset: u32 = 4;
998 /// Mask (1 bit: 1 << 4)
999 pub const mask: u32 = 1 << offset;
1000 /// Read-only values
1001 pub mod R {
1002
1003 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
1004 pub const Match: u32 = 0b1;
1005 }
1006 pub use super::CC4OF::W;
1007 /// Read-write values (empty)
1008 pub mod RW {}
1009 }
1010
1011 /// Capture/Compare 3 interrupt flag
1012 pub mod CC3IF {
1013 /// Offset (3 bits)
1014 pub const offset: u32 = 3;
1015 /// Mask (1 bit: 1 << 3)
1016 pub const mask: u32 = 1 << offset;
1017 /// Read-only values
1018 pub mod R {
1019
1020 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
1021 pub const Match: u32 = 0b1;
1022 }
1023 pub use super::CC4OF::W;
1024 /// Read-write values (empty)
1025 pub mod RW {}
1026 }
1027
1028 /// Capture/Compare 2 interrupt flag
1029 pub mod CC2IF {
1030 /// Offset (2 bits)
1031 pub const offset: u32 = 2;
1032 /// Mask (1 bit: 1 << 2)
1033 pub const mask: u32 = 1 << offset;
1034 /// Read-only values
1035 pub mod R {
1036
1037 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
1038 pub const Match: u32 = 0b1;
1039 }
1040 pub use super::CC4OF::W;
1041 /// Read-write values (empty)
1042 pub mod RW {}
1043 }
1044
1045 /// Capture/compare 1 interrupt flag
1046 pub mod CC1IF {
1047 /// Offset (1 bits)
1048 pub const offset: u32 = 1;
1049 /// Mask (1 bit: 1 << 1)
1050 pub const mask: u32 = 1 << offset;
1051 /// Read-only values
1052 pub mod R {
1053
1054 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
1055 pub const Match: u32 = 0b1;
1056 }
1057 pub use super::CC4OF::W;
1058 /// Read-write values (empty)
1059 pub mod RW {}
1060 }
1061
1062 /// Update interrupt flag
1063 pub mod UIF {
1064 /// Offset (0 bits)
1065 pub const offset: u32 = 0;
1066 /// Mask (1 bit: 1 << 0)
1067 pub const mask: u32 = 1 << offset;
1068 /// Read-only values (empty)
1069 pub mod R {}
1070 /// Write-only values (empty)
1071 pub mod W {}
1072 /// Read-write values
1073 pub mod RW {
1074
1075 /// 0b0: No update occurred
1076 pub const Clear: u32 = 0b0;
1077
1078 /// 0b1: Update interrupt pending.
1079 pub const UpdatePending: u32 = 0b1;
1080 }
1081 }
1082}
1083
1084/// event generation register
1085pub mod EGR {
1086
1087 /// Break generation
1088 pub mod BG {
1089 /// Offset (7 bits)
1090 pub const offset: u32 = 7;
1091 /// Mask (1 bit: 1 << 7)
1092 pub const mask: u32 = 1 << offset;
1093 /// Read-only values (empty)
1094 pub mod R {}
1095 /// Write-only values (empty)
1096 pub mod W {}
1097 /// Read-write values (empty)
1098 pub mod RW {}
1099 }
1100
1101 /// Trigger generation
1102 pub mod TG {
1103 /// Offset (6 bits)
1104 pub const offset: u32 = 6;
1105 /// Mask (1 bit: 1 << 6)
1106 pub const mask: u32 = 1 << offset;
1107 /// Read-only values (empty)
1108 pub mod R {}
1109 /// Write-only values
1110 pub mod W {
1111
1112 /// 0b1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
1113 pub const Trigger: u32 = 0b1;
1114 }
1115 /// Read-write values (empty)
1116 pub mod RW {}
1117 }
1118
1119 /// Capture/Compare control update generation
1120 pub mod COMG {
1121 /// Offset (5 bits)
1122 pub const offset: u32 = 5;
1123 /// Mask (1 bit: 1 << 5)
1124 pub const mask: u32 = 1 << offset;
1125 /// Read-only values (empty)
1126 pub mod R {}
1127 /// Write-only values (empty)
1128 pub mod W {}
1129 /// Read-write values (empty)
1130 pub mod RW {}
1131 }
1132
1133 /// Capture/compare 4 generation
1134 pub mod CC4G {
1135 /// Offset (4 bits)
1136 pub const offset: u32 = 4;
1137 /// Mask (1 bit: 1 << 4)
1138 pub const mask: u32 = 1 << offset;
1139 /// Read-only values (empty)
1140 pub mod R {}
1141 /// Write-only values
1142 pub mod W {
1143
1144 /// 0b1: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
1145 pub const Trigger: u32 = 0b1;
1146 }
1147 /// Read-write values (empty)
1148 pub mod RW {}
1149 }
1150
1151 /// Capture/compare 3 generation
1152 pub mod CC3G {
1153 /// Offset (3 bits)
1154 pub const offset: u32 = 3;
1155 /// Mask (1 bit: 1 << 3)
1156 pub const mask: u32 = 1 << offset;
1157 /// Read-only values (empty)
1158 pub mod R {}
1159 pub use super::CC4G::W;
1160 /// Read-write values (empty)
1161 pub mod RW {}
1162 }
1163
1164 /// Capture/compare 2 generation
1165 pub mod CC2G {
1166 /// Offset (2 bits)
1167 pub const offset: u32 = 2;
1168 /// Mask (1 bit: 1 << 2)
1169 pub const mask: u32 = 1 << offset;
1170 /// Read-only values (empty)
1171 pub mod R {}
1172 pub use super::CC4G::W;
1173 /// Read-write values (empty)
1174 pub mod RW {}
1175 }
1176
1177 /// Capture/compare 1 generation
1178 pub mod CC1G {
1179 /// Offset (1 bits)
1180 pub const offset: u32 = 1;
1181 /// Mask (1 bit: 1 << 1)
1182 pub const mask: u32 = 1 << offset;
1183 /// Read-only values (empty)
1184 pub mod R {}
1185 pub use super::CC4G::W;
1186 /// Read-write values (empty)
1187 pub mod RW {}
1188 }
1189
1190 /// Update generation
1191 pub mod UG {
1192 /// Offset (0 bits)
1193 pub const offset: u32 = 0;
1194 /// Mask (1 bit: 1 << 0)
1195 pub const mask: u32 = 1 << offset;
1196 /// Read-only values (empty)
1197 pub mod R {}
1198 /// Write-only values
1199 pub mod W {
1200
1201 /// 0b1: Re-initializes the timer counter and generates an update of the registers.
1202 pub const Update: u32 = 0b1;
1203 }
1204 /// Read-write values (empty)
1205 pub mod RW {}
1206 }
1207}
1208
1209/// CCMR1_Output and CCMR1_Input
1210/// CCMR1_Output: capture/compare mode register (output mode)
1211/// CCMR1_Input: capture/compare mode register 1 (input mode)
1212pub mod CCMR1 {
1213
1214 /// Output Compare 2 clear enable
1215 pub mod OC2CE {
1216 /// Offset (15 bits)
1217 pub const offset: u32 = 15;
1218 /// Mask (1 bit: 1 << 15)
1219 pub const mask: u32 = 1 << offset;
1220 /// Read-only values (empty)
1221 pub mod R {}
1222 /// Write-only values (empty)
1223 pub mod W {}
1224 /// Read-write values (empty)
1225 pub mod RW {}
1226 }
1227
1228 /// Output Compare 2 mode
1229 pub mod OC2M {
1230 /// Offset (12 bits)
1231 pub const offset: u32 = 12;
1232 /// Mask (3 bits: 0b111 << 12)
1233 pub const mask: u32 = 0b111 << offset;
1234 /// Read-only values (empty)
1235 pub mod R {}
1236 /// Write-only values (empty)
1237 pub mod W {}
1238 /// Read-write values
1239 pub mod RW {
1240
1241 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1242 pub const Frozen: u32 = 0b000;
1243
1244 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1245 pub const ActiveOnMatch: u32 = 0b001;
1246
1247 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
1248 pub const InactiveOnMatch: u32 = 0b010;
1249
1250 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy
1251 pub const Toggle: u32 = 0b011;
1252
1253 /// 0b100: OCyREF is forced low
1254 pub const ForceInactive: u32 = 0b100;
1255
1256 /// 0b101: OCyREF is forced high
1257 pub const ForceActive: u32 = 0b101;
1258
1259 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
1260 pub const PwmMode1: u32 = 0b110;
1261
1262 /// 0b111: Inversely to PwmMode1
1263 pub const PwmMode2: u32 = 0b111;
1264 }
1265 }
1266
1267 /// Output Compare 2 preload enable
1268 pub mod OC2PE {
1269 /// Offset (11 bits)
1270 pub const offset: u32 = 11;
1271 /// Mask (1 bit: 1 << 11)
1272 pub const mask: u32 = 1 << offset;
1273 /// Read-only values (empty)
1274 pub mod R {}
1275 /// Write-only values (empty)
1276 pub mod W {}
1277 /// Read-write values
1278 pub mod RW {
1279
1280 /// 0b0: Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately
1281 pub const Disabled: u32 = 0b0;
1282
1283 /// 0b1: Preload register on CCR2 enabled. Preload value is loaded into active register on each update event
1284 pub const Enabled: u32 = 0b1;
1285 }
1286 }
1287
1288 /// Output Compare 2 fast enable
1289 pub mod OC2FE {
1290 /// Offset (10 bits)
1291 pub const offset: u32 = 10;
1292 /// Mask (1 bit: 1 << 10)
1293 pub const mask: u32 = 1 << offset;
1294 /// Read-only values (empty)
1295 pub mod R {}
1296 /// Write-only values (empty)
1297 pub mod W {}
1298 /// Read-write values (empty)
1299 pub mod RW {}
1300 }
1301
1302 /// Capture/Compare 2 selection
1303 pub mod CC2S {
1304 /// Offset (8 bits)
1305 pub const offset: u32 = 8;
1306 /// Mask (2 bits: 0b11 << 8)
1307 pub const mask: u32 = 0b11 << offset;
1308 /// Read-only values (empty)
1309 pub mod R {}
1310 /// Write-only values (empty)
1311 pub mod W {}
1312 /// Read-write values
1313 pub mod RW {
1314
1315 /// 0b00: CC2 channel is configured as output
1316 pub const Output: u32 = 0b00;
1317 }
1318 }
1319
1320 /// Output Compare 1 clear enable
1321 pub mod OC1CE {
1322 /// Offset (7 bits)
1323 pub const offset: u32 = 7;
1324 /// Mask (1 bit: 1 << 7)
1325 pub const mask: u32 = 1 << offset;
1326 /// Read-only values (empty)
1327 pub mod R {}
1328 /// Write-only values (empty)
1329 pub mod W {}
1330 /// Read-write values (empty)
1331 pub mod RW {}
1332 }
1333
1334 /// Output Compare 1 mode
1335 pub mod OC1M {
1336 /// Offset (4 bits)
1337 pub const offset: u32 = 4;
1338 /// Mask (3 bits: 0b111 << 4)
1339 pub const mask: u32 = 0b111 << offset;
1340 /// Read-only values (empty)
1341 pub mod R {}
1342 /// Write-only values (empty)
1343 pub mod W {}
1344 pub use super::OC2M::RW;
1345 }
1346
1347 /// Output Compare 1 preload enable
1348 pub mod OC1PE {
1349 /// Offset (3 bits)
1350 pub const offset: u32 = 3;
1351 /// Mask (1 bit: 1 << 3)
1352 pub const mask: u32 = 1 << offset;
1353 /// Read-only values (empty)
1354 pub mod R {}
1355 /// Write-only values (empty)
1356 pub mod W {}
1357 /// Read-write values
1358 pub mod RW {
1359
1360 /// 0b0: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1361 pub const Disabled: u32 = 0b0;
1362
1363 /// 0b1: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
1364 pub const Enabled: u32 = 0b1;
1365 }
1366 }
1367
1368 /// Output Compare 1 fast enable
1369 pub mod OC1FE {
1370 /// Offset (2 bits)
1371 pub const offset: u32 = 2;
1372 /// Mask (1 bit: 1 << 2)
1373 pub const mask: u32 = 1 << offset;
1374 /// Read-only values (empty)
1375 pub mod R {}
1376 /// Write-only values (empty)
1377 pub mod W {}
1378 /// Read-write values (empty)
1379 pub mod RW {}
1380 }
1381
1382 /// Capture/Compare 1 selection
1383 pub mod CC1S {
1384 /// Offset (0 bits)
1385 pub const offset: u32 = 0;
1386 /// Mask (2 bits: 0b11 << 0)
1387 pub const mask: u32 = 0b11 << offset;
1388 /// Read-only values (empty)
1389 pub mod R {}
1390 /// Write-only values (empty)
1391 pub mod W {}
1392 /// Read-write values
1393 pub mod RW {
1394
1395 /// 0b00: CC1 channel is configured as output
1396 pub const Output: u32 = 0b00;
1397 }
1398 }
1399
1400 /// Input capture 2 filter
1401 pub mod IC2F {
1402 /// Offset (12 bits)
1403 pub const offset: u32 = 12;
1404 /// Mask (4 bits: 0b1111 << 12)
1405 pub const mask: u32 = 0b1111 << offset;
1406 /// Read-only values (empty)
1407 pub mod R {}
1408 /// Write-only values (empty)
1409 pub mod W {}
1410 /// Read-write values (empty)
1411 pub mod RW {}
1412 }
1413
1414 /// Input capture 2 prescaler
1415 pub mod IC2PSC {
1416 /// Offset (10 bits)
1417 pub const offset: u32 = 10;
1418 /// Mask (2 bits: 0b11 << 10)
1419 pub const mask: u32 = 0b11 << offset;
1420 /// Read-only values (empty)
1421 pub mod R {}
1422 /// Write-only values (empty)
1423 pub mod W {}
1424 /// Read-write values (empty)
1425 pub mod RW {}
1426 }
1427
1428 /// Input capture 1 filter
1429 pub mod IC1F {
1430 /// Offset (4 bits)
1431 pub const offset: u32 = 4;
1432 /// Mask (4 bits: 0b1111 << 4)
1433 pub const mask: u32 = 0b1111 << offset;
1434 /// Read-only values (empty)
1435 pub mod R {}
1436 /// Write-only values (empty)
1437 pub mod W {}
1438 /// Read-write values
1439 pub mod RW {
1440
1441 /// 0b0000: No filter, sampling is done at fDTS
1442 pub const NoFilter: u32 = 0b0000;
1443
1444 /// 0b0001: fSAMPLING=fCK_INT, N=2
1445 pub const FCK_INT_N2: u32 = 0b0001;
1446
1447 /// 0b0010: fSAMPLING=fCK_INT, N=4
1448 pub const FCK_INT_N4: u32 = 0b0010;
1449
1450 /// 0b0011: fSAMPLING=fCK_INT, N=8
1451 pub const FCK_INT_N8: u32 = 0b0011;
1452
1453 /// 0b0100: fSAMPLING=fDTS/2, N=6
1454 pub const FDTS_Div2_N6: u32 = 0b0100;
1455
1456 /// 0b0101: fSAMPLING=fDTS/2, N=8
1457 pub const FDTS_Div2_N8: u32 = 0b0101;
1458
1459 /// 0b0110: fSAMPLING=fDTS/4, N=6
1460 pub const FDTS_Div4_N6: u32 = 0b0110;
1461
1462 /// 0b0111: fSAMPLING=fDTS/4, N=8
1463 pub const FDTS_Div4_N8: u32 = 0b0111;
1464
1465 /// 0b1000: fSAMPLING=fDTS/8, N=6
1466 pub const FDTS_Div8_N6: u32 = 0b1000;
1467
1468 /// 0b1001: fSAMPLING=fDTS/8, N=8
1469 pub const FDTS_Div8_N8: u32 = 0b1001;
1470
1471 /// 0b1010: fSAMPLING=fDTS/16, N=5
1472 pub const FDTS_Div16_N5: u32 = 0b1010;
1473
1474 /// 0b1011: fSAMPLING=fDTS/16, N=6
1475 pub const FDTS_Div16_N6: u32 = 0b1011;
1476
1477 /// 0b1100: fSAMPLING=fDTS/16, N=8
1478 pub const FDTS_Div16_N8: u32 = 0b1100;
1479
1480 /// 0b1101: fSAMPLING=fDTS/32, N=5
1481 pub const FDTS_Div32_N5: u32 = 0b1101;
1482
1483 /// 0b1110: fSAMPLING=fDTS/32, N=6
1484 pub const FDTS_Div32_N6: u32 = 0b1110;
1485
1486 /// 0b1111: fSAMPLING=fDTS/32, N=8
1487 pub const FDTS_Div32_N8: u32 = 0b1111;
1488 }
1489 }
1490
1491 /// Input capture 1 prescaler
1492 pub mod IC1PSC {
1493 /// Offset (2 bits)
1494 pub const offset: u32 = 2;
1495 /// Mask (2 bits: 0b11 << 2)
1496 pub const mask: u32 = 0b11 << offset;
1497 /// Read-only values (empty)
1498 pub mod R {}
1499 /// Write-only values (empty)
1500 pub mod W {}
1501 /// Read-write values (empty)
1502 pub mod RW {}
1503 }
1504}
1505
1506/// CCMR2_Output and CCMR2_Input
1507/// CCMR2_Output: capture/compare mode register (output mode)
1508/// CCMR2_Input: capture/compare mode register 2 (input mode)
1509pub mod CCMR2 {
1510
1511 /// Output compare 4 clear enable
1512 pub mod OC4CE {
1513 /// Offset (15 bits)
1514 pub const offset: u32 = 15;
1515 /// Mask (1 bit: 1 << 15)
1516 pub const mask: u32 = 1 << offset;
1517 /// Read-only values (empty)
1518 pub mod R {}
1519 /// Write-only values (empty)
1520 pub mod W {}
1521 /// Read-write values (empty)
1522 pub mod RW {}
1523 }
1524
1525 /// Output compare 4 mode
1526 pub mod OC4M {
1527 /// Offset (12 bits)
1528 pub const offset: u32 = 12;
1529 /// Mask (3 bits: 0b111 << 12)
1530 pub const mask: u32 = 0b111 << offset;
1531 /// Read-only values (empty)
1532 pub mod R {}
1533 /// Write-only values (empty)
1534 pub mod W {}
1535 /// Read-write values
1536 pub mod RW {
1537
1538 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1539 pub const Frozen: u32 = 0b000;
1540
1541 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1542 pub const ActiveOnMatch: u32 = 0b001;
1543
1544 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
1545 pub const InactiveOnMatch: u32 = 0b010;
1546
1547 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy
1548 pub const Toggle: u32 = 0b011;
1549
1550 /// 0b100: OCyREF is forced low
1551 pub const ForceInactive: u32 = 0b100;
1552
1553 /// 0b101: OCyREF is forced high
1554 pub const ForceActive: u32 = 0b101;
1555
1556 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
1557 pub const PwmMode1: u32 = 0b110;
1558
1559 /// 0b111: Inversely to PwmMode1
1560 pub const PwmMode2: u32 = 0b111;
1561 }
1562 }
1563
1564 /// Output compare 4 preload enable
1565 pub mod OC4PE {
1566 /// Offset (11 bits)
1567 pub const offset: u32 = 11;
1568 /// Mask (1 bit: 1 << 11)
1569 pub const mask: u32 = 1 << offset;
1570 /// Read-only values (empty)
1571 pub mod R {}
1572 /// Write-only values (empty)
1573 pub mod W {}
1574 /// Read-write values
1575 pub mod RW {
1576
1577 /// 0b0: Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately
1578 pub const Disabled: u32 = 0b0;
1579
1580 /// 0b1: Preload register on CCR4 enabled. Preload value is loaded into active register on each update event
1581 pub const Enabled: u32 = 0b1;
1582 }
1583 }
1584
1585 /// Output compare 4 fast enable
1586 pub mod OC4FE {
1587 /// Offset (10 bits)
1588 pub const offset: u32 = 10;
1589 /// Mask (1 bit: 1 << 10)
1590 pub const mask: u32 = 1 << offset;
1591 /// Read-only values (empty)
1592 pub mod R {}
1593 /// Write-only values (empty)
1594 pub mod W {}
1595 /// Read-write values (empty)
1596 pub mod RW {}
1597 }
1598
1599 /// Capture/Compare 4 selection
1600 pub mod CC4S {
1601 /// Offset (8 bits)
1602 pub const offset: u32 = 8;
1603 /// Mask (2 bits: 0b11 << 8)
1604 pub const mask: u32 = 0b11 << offset;
1605 /// Read-only values (empty)
1606 pub mod R {}
1607 /// Write-only values (empty)
1608 pub mod W {}
1609 /// Read-write values
1610 pub mod RW {
1611
1612 /// 0b00: CC4 channel is configured as output
1613 pub const Output: u32 = 0b00;
1614 }
1615 }
1616
1617 /// Output compare 3 clear enable
1618 pub mod OC3CE {
1619 /// Offset (7 bits)
1620 pub const offset: u32 = 7;
1621 /// Mask (1 bit: 1 << 7)
1622 pub const mask: u32 = 1 << offset;
1623 /// Read-only values (empty)
1624 pub mod R {}
1625 /// Write-only values (empty)
1626 pub mod W {}
1627 /// Read-write values (empty)
1628 pub mod RW {}
1629 }
1630
1631 /// Output compare 3 mode
1632 pub mod OC3M {
1633 /// Offset (4 bits)
1634 pub const offset: u32 = 4;
1635 /// Mask (3 bits: 0b111 << 4)
1636 pub const mask: u32 = 0b111 << offset;
1637 /// Read-only values (empty)
1638 pub mod R {}
1639 /// Write-only values (empty)
1640 pub mod W {}
1641 pub use super::OC4M::RW;
1642 }
1643
1644 /// Output compare 3 preload enable
1645 pub mod OC3PE {
1646 /// Offset (3 bits)
1647 pub const offset: u32 = 3;
1648 /// Mask (1 bit: 1 << 3)
1649 pub const mask: u32 = 1 << offset;
1650 /// Read-only values (empty)
1651 pub mod R {}
1652 /// Write-only values (empty)
1653 pub mod W {}
1654 /// Read-write values
1655 pub mod RW {
1656
1657 /// 0b0: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1658 pub const Disabled: u32 = 0b0;
1659
1660 /// 0b1: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
1661 pub const Enabled: u32 = 0b1;
1662 }
1663 }
1664
1665 /// Output compare 3 fast enable
1666 pub mod OC3FE {
1667 /// Offset (2 bits)
1668 pub const offset: u32 = 2;
1669 /// Mask (1 bit: 1 << 2)
1670 pub const mask: u32 = 1 << offset;
1671 /// Read-only values (empty)
1672 pub mod R {}
1673 /// Write-only values (empty)
1674 pub mod W {}
1675 /// Read-write values (empty)
1676 pub mod RW {}
1677 }
1678
1679 /// Capture/Compare 3 selection
1680 pub mod CC3S {
1681 /// Offset (0 bits)
1682 pub const offset: u32 = 0;
1683 /// Mask (2 bits: 0b11 << 0)
1684 pub const mask: u32 = 0b11 << offset;
1685 /// Read-only values (empty)
1686 pub mod R {}
1687 /// Write-only values (empty)
1688 pub mod W {}
1689 /// Read-write values
1690 pub mod RW {
1691
1692 /// 0b00: CC3 channel is configured as output
1693 pub const Output: u32 = 0b00;
1694 }
1695 }
1696
1697 /// Input capture 4 filter
1698 pub mod IC4F {
1699 /// Offset (12 bits)
1700 pub const offset: u32 = 12;
1701 /// Mask (4 bits: 0b1111 << 12)
1702 pub const mask: u32 = 0b1111 << offset;
1703 /// Read-only values (empty)
1704 pub mod R {}
1705 /// Write-only values (empty)
1706 pub mod W {}
1707 /// Read-write values (empty)
1708 pub mod RW {}
1709 }
1710
1711 /// Input capture 4 prescaler
1712 pub mod IC4PSC {
1713 /// Offset (10 bits)
1714 pub const offset: u32 = 10;
1715 /// Mask (2 bits: 0b11 << 10)
1716 pub const mask: u32 = 0b11 << offset;
1717 /// Read-only values (empty)
1718 pub mod R {}
1719 /// Write-only values (empty)
1720 pub mod W {}
1721 /// Read-write values (empty)
1722 pub mod RW {}
1723 }
1724
1725 /// Input capture 3 filter
1726 pub mod IC3F {
1727 /// Offset (4 bits)
1728 pub const offset: u32 = 4;
1729 /// Mask (4 bits: 0b1111 << 4)
1730 pub const mask: u32 = 0b1111 << offset;
1731 /// Read-only values (empty)
1732 pub mod R {}
1733 /// Write-only values (empty)
1734 pub mod W {}
1735 /// Read-write values (empty)
1736 pub mod RW {}
1737 }
1738
1739 /// Input capture 3 prescaler
1740 pub mod IC3PSC {
1741 /// Offset (2 bits)
1742 pub const offset: u32 = 2;
1743 /// Mask (2 bits: 0b11 << 2)
1744 pub const mask: u32 = 0b11 << offset;
1745 /// Read-only values (empty)
1746 pub mod R {}
1747 /// Write-only values (empty)
1748 pub mod W {}
1749 /// Read-write values (empty)
1750 pub mod RW {}
1751 }
1752}
1753
1754/// capture/compare enable register
1755pub mod CCER {
1756
1757 /// Capture/Compare 3 output Polarity
1758 pub mod CC4P {
1759 /// Offset (13 bits)
1760 pub const offset: u32 = 13;
1761 /// Mask (1 bit: 1 << 13)
1762 pub const mask: u32 = 1 << offset;
1763 /// Read-only values (empty)
1764 pub mod R {}
1765 /// Write-only values (empty)
1766 pub mod W {}
1767 /// Read-write values (empty)
1768 pub mod RW {}
1769 }
1770
1771 /// Capture/Compare 4 output enable
1772 pub mod CC4E {
1773 /// Offset (12 bits)
1774 pub const offset: u32 = 12;
1775 /// Mask (1 bit: 1 << 12)
1776 pub const mask: u32 = 1 << offset;
1777 /// Read-only values (empty)
1778 pub mod R {}
1779 /// Write-only values (empty)
1780 pub mod W {}
1781 /// Read-write values (empty)
1782 pub mod RW {}
1783 }
1784
1785 /// Capture/Compare 3 output Polarity
1786 pub mod CC3NP {
1787 /// Offset (11 bits)
1788 pub const offset: u32 = 11;
1789 /// Mask (1 bit: 1 << 11)
1790 pub const mask: u32 = 1 << offset;
1791 /// Read-only values (empty)
1792 pub mod R {}
1793 /// Write-only values (empty)
1794 pub mod W {}
1795 /// Read-write values (empty)
1796 pub mod RW {}
1797 }
1798
1799 /// Capture/Compare 3 complementary output enable
1800 pub mod CC3NE {
1801 /// Offset (10 bits)
1802 pub const offset: u32 = 10;
1803 /// Mask (1 bit: 1 << 10)
1804 pub const mask: u32 = 1 << offset;
1805 /// Read-only values (empty)
1806 pub mod R {}
1807 /// Write-only values (empty)
1808 pub mod W {}
1809 /// Read-write values (empty)
1810 pub mod RW {}
1811 }
1812
1813 /// Capture/Compare 3 output Polarity
1814 pub mod CC3P {
1815 /// Offset (9 bits)
1816 pub const offset: u32 = 9;
1817 /// Mask (1 bit: 1 << 9)
1818 pub const mask: u32 = 1 << offset;
1819 /// Read-only values (empty)
1820 pub mod R {}
1821 /// Write-only values (empty)
1822 pub mod W {}
1823 /// Read-write values (empty)
1824 pub mod RW {}
1825 }
1826
1827 /// Capture/Compare 3 output enable
1828 pub mod CC3E {
1829 /// Offset (8 bits)
1830 pub const offset: u32 = 8;
1831 /// Mask (1 bit: 1 << 8)
1832 pub const mask: u32 = 1 << offset;
1833 /// Read-only values (empty)
1834 pub mod R {}
1835 /// Write-only values (empty)
1836 pub mod W {}
1837 /// Read-write values (empty)
1838 pub mod RW {}
1839 }
1840
1841 /// Capture/Compare 2 output Polarity
1842 pub mod CC2NP {
1843 /// Offset (7 bits)
1844 pub const offset: u32 = 7;
1845 /// Mask (1 bit: 1 << 7)
1846 pub const mask: u32 = 1 << offset;
1847 /// Read-only values (empty)
1848 pub mod R {}
1849 /// Write-only values (empty)
1850 pub mod W {}
1851 /// Read-write values (empty)
1852 pub mod RW {}
1853 }
1854
1855 /// Capture/Compare 2 complementary output enable
1856 pub mod CC2NE {
1857 /// Offset (6 bits)
1858 pub const offset: u32 = 6;
1859 /// Mask (1 bit: 1 << 6)
1860 pub const mask: u32 = 1 << offset;
1861 /// Read-only values (empty)
1862 pub mod R {}
1863 /// Write-only values (empty)
1864 pub mod W {}
1865 /// Read-write values (empty)
1866 pub mod RW {}
1867 }
1868
1869 /// Capture/Compare 2 output Polarity
1870 pub mod CC2P {
1871 /// Offset (5 bits)
1872 pub const offset: u32 = 5;
1873 /// Mask (1 bit: 1 << 5)
1874 pub const mask: u32 = 1 << offset;
1875 /// Read-only values (empty)
1876 pub mod R {}
1877 /// Write-only values (empty)
1878 pub mod W {}
1879 /// Read-write values (empty)
1880 pub mod RW {}
1881 }
1882
1883 /// Capture/Compare 2 output enable
1884 pub mod CC2E {
1885 /// Offset (4 bits)
1886 pub const offset: u32 = 4;
1887 /// Mask (1 bit: 1 << 4)
1888 pub const mask: u32 = 1 << offset;
1889 /// Read-only values (empty)
1890 pub mod R {}
1891 /// Write-only values (empty)
1892 pub mod W {}
1893 /// Read-write values (empty)
1894 pub mod RW {}
1895 }
1896
1897 /// Capture/Compare 1 output Polarity
1898 pub mod CC1NP {
1899 /// Offset (3 bits)
1900 pub const offset: u32 = 3;
1901 /// Mask (1 bit: 1 << 3)
1902 pub const mask: u32 = 1 << offset;
1903 /// Read-only values (empty)
1904 pub mod R {}
1905 /// Write-only values (empty)
1906 pub mod W {}
1907 /// Read-write values (empty)
1908 pub mod RW {}
1909 }
1910
1911 /// Capture/Compare 1 complementary output enable
1912 pub mod CC1NE {
1913 /// Offset (2 bits)
1914 pub const offset: u32 = 2;
1915 /// Mask (1 bit: 1 << 2)
1916 pub const mask: u32 = 1 << offset;
1917 /// Read-only values (empty)
1918 pub mod R {}
1919 /// Write-only values (empty)
1920 pub mod W {}
1921 /// Read-write values (empty)
1922 pub mod RW {}
1923 }
1924
1925 /// Capture/Compare 1 output Polarity
1926 pub mod CC1P {
1927 /// Offset (1 bits)
1928 pub const offset: u32 = 1;
1929 /// Mask (1 bit: 1 << 1)
1930 pub const mask: u32 = 1 << offset;
1931 /// Read-only values (empty)
1932 pub mod R {}
1933 /// Write-only values (empty)
1934 pub mod W {}
1935 /// Read-write values (empty)
1936 pub mod RW {}
1937 }
1938
1939 /// Capture/Compare 1 output enable
1940 pub mod CC1E {
1941 /// Offset (0 bits)
1942 pub const offset: u32 = 0;
1943 /// Mask (1 bit: 1 << 0)
1944 pub const mask: u32 = 1 << offset;
1945 /// Read-only values (empty)
1946 pub mod R {}
1947 /// Write-only values (empty)
1948 pub mod W {}
1949 /// Read-write values (empty)
1950 pub mod RW {}
1951 }
1952}
1953
1954/// counter
1955pub mod CNT {
1956
1957 /// counter value
1958 pub mod CNT {
1959 /// Offset (0 bits)
1960 pub const offset: u32 = 0;
1961 /// Mask (16 bits: 0xffff << 0)
1962 pub const mask: u32 = 0xffff << offset;
1963 /// Read-only values (empty)
1964 pub mod R {}
1965 /// Write-only values (empty)
1966 pub mod W {}
1967 /// Read-write values (empty)
1968 pub mod RW {}
1969 }
1970}
1971
1972/// prescaler
1973pub mod PSC {
1974
1975 /// Prescaler value
1976 pub mod PSC {
1977 /// Offset (0 bits)
1978 pub const offset: u32 = 0;
1979 /// Mask (16 bits: 0xffff << 0)
1980 pub const mask: u32 = 0xffff << offset;
1981 /// Read-only values (empty)
1982 pub mod R {}
1983 /// Write-only values (empty)
1984 pub mod W {}
1985 /// Read-write values (empty)
1986 pub mod RW {}
1987 }
1988}
1989
1990/// auto-reload register
1991pub mod ARR {
1992
1993 /// Auto-reload value
1994 pub mod ARR {
1995 /// Offset (0 bits)
1996 pub const offset: u32 = 0;
1997 /// Mask (16 bits: 0xffff << 0)
1998 pub const mask: u32 = 0xffff << offset;
1999 /// Read-only values (empty)
2000 pub mod R {}
2001 /// Write-only values (empty)
2002 pub mod W {}
2003 /// Read-write values (empty)
2004 pub mod RW {}
2005 }
2006}
2007
2008/// capture/compare register
2009pub mod CCR1 {
2010
2011 /// Capture/Compare value
2012 pub mod CCR {
2013 /// Offset (0 bits)
2014 pub const offset: u32 = 0;
2015 /// Mask (16 bits: 0xffff << 0)
2016 pub const mask: u32 = 0xffff << offset;
2017 /// Read-only values (empty)
2018 pub mod R {}
2019 /// Write-only values (empty)
2020 pub mod W {}
2021 /// Read-write values (empty)
2022 pub mod RW {}
2023 }
2024}
2025
2026/// capture/compare register
2027pub mod CCR2 {
2028 pub use super::CCR1::CCR;
2029}
2030
2031/// capture/compare register
2032pub mod CCR3 {
2033 pub use super::CCR1::CCR;
2034}
2035
2036/// capture/compare register
2037pub mod CCR4 {
2038 pub use super::CCR1::CCR;
2039}
2040
2041/// DMA control register
2042pub mod DCR {
2043
2044 /// DMA burst length
2045 pub mod DBL {
2046 /// Offset (8 bits)
2047 pub const offset: u32 = 8;
2048 /// Mask (5 bits: 0b11111 << 8)
2049 pub const mask: u32 = 0b11111 << offset;
2050 /// Read-only values (empty)
2051 pub mod R {}
2052 /// Write-only values (empty)
2053 pub mod W {}
2054 /// Read-write values (empty)
2055 pub mod RW {}
2056 }
2057
2058 /// DMA base address
2059 pub mod DBA {
2060 /// Offset (0 bits)
2061 pub const offset: u32 = 0;
2062 /// Mask (5 bits: 0b11111 << 0)
2063 pub const mask: u32 = 0b11111 << offset;
2064 /// Read-only values (empty)
2065 pub mod R {}
2066 /// Write-only values (empty)
2067 pub mod W {}
2068 /// Read-write values (empty)
2069 pub mod RW {}
2070 }
2071}
2072
2073/// DMA address for full transfer
2074pub mod DMAR {
2075
2076 /// DMA register for burst accesses
2077 pub mod DMAB {
2078 /// Offset (0 bits)
2079 pub const offset: u32 = 0;
2080 /// Mask (16 bits: 0xffff << 0)
2081 pub const mask: u32 = 0xffff << offset;
2082 /// Read-only values (empty)
2083 pub mod R {}
2084 /// Write-only values (empty)
2085 pub mod W {}
2086 /// Read-write values (empty)
2087 pub mod RW {}
2088 }
2089}
2090
2091/// repetition counter register
2092pub mod RCR {
2093
2094 /// Repetition counter value
2095 pub mod REP {
2096 /// Offset (0 bits)
2097 pub const offset: u32 = 0;
2098 /// Mask (8 bits: 0xff << 0)
2099 pub const mask: u32 = 0xff << offset;
2100 /// Read-only values (empty)
2101 pub mod R {}
2102 /// Write-only values (empty)
2103 pub mod W {}
2104 /// Read-write values (empty)
2105 pub mod RW {}
2106 }
2107}
2108
2109/// break and dead-time register
2110pub mod BDTR {
2111
2112 /// Main output enable
2113 pub mod MOE {
2114 /// Offset (15 bits)
2115 pub const offset: u32 = 15;
2116 /// Mask (1 bit: 1 << 15)
2117 pub const mask: u32 = 1 << offset;
2118 /// Read-only values (empty)
2119 pub mod R {}
2120 /// Write-only values (empty)
2121 pub mod W {}
2122 /// Read-write values
2123 pub mod RW {
2124
2125 /// 0b0: OC/OCN are disabled or forced idle depending on OSSI
2126 pub const DisabledIdle: u32 = 0b0;
2127
2128 /// 0b1: OC/OCN are enabled if CCxE/CCxNE are set
2129 pub const Enabled: u32 = 0b1;
2130 }
2131 }
2132
2133 /// Automatic output enable
2134 pub mod AOE {
2135 /// Offset (14 bits)
2136 pub const offset: u32 = 14;
2137 /// Mask (1 bit: 1 << 14)
2138 pub const mask: u32 = 1 << offset;
2139 /// Read-only values (empty)
2140 pub mod R {}
2141 /// Write-only values (empty)
2142 pub mod W {}
2143 /// Read-write values (empty)
2144 pub mod RW {}
2145 }
2146
2147 /// Break polarity
2148 pub mod BKP {
2149 /// Offset (13 bits)
2150 pub const offset: u32 = 13;
2151 /// Mask (1 bit: 1 << 13)
2152 pub const mask: u32 = 1 << offset;
2153 /// Read-only values (empty)
2154 pub mod R {}
2155 /// Write-only values (empty)
2156 pub mod W {}
2157 /// Read-write values (empty)
2158 pub mod RW {}
2159 }
2160
2161 /// Break enable
2162 pub mod BKE {
2163 /// Offset (12 bits)
2164 pub const offset: u32 = 12;
2165 /// Mask (1 bit: 1 << 12)
2166 pub const mask: u32 = 1 << offset;
2167 /// Read-only values (empty)
2168 pub mod R {}
2169 /// Write-only values (empty)
2170 pub mod W {}
2171 /// Read-write values (empty)
2172 pub mod RW {}
2173 }
2174
2175 /// Off-state selection for Run mode
2176 pub mod OSSR {
2177 /// Offset (11 bits)
2178 pub const offset: u32 = 11;
2179 /// Mask (1 bit: 1 << 11)
2180 pub const mask: u32 = 1 << offset;
2181 /// Read-only values (empty)
2182 pub mod R {}
2183 /// Write-only values (empty)
2184 pub mod W {}
2185 /// Read-write values
2186 pub mod RW {
2187
2188 /// 0b0: When inactive, OC/OCN outputs are disabled
2189 pub const Disabled: u32 = 0b0;
2190
2191 /// 0b1: When inactive, OC/OCN outputs are enabled with their inactive level
2192 pub const IdleLevel: u32 = 0b1;
2193 }
2194 }
2195
2196 /// Off-state selection for Idle mode
2197 pub mod OSSI {
2198 /// Offset (10 bits)
2199 pub const offset: u32 = 10;
2200 /// Mask (1 bit: 1 << 10)
2201 pub const mask: u32 = 1 << offset;
2202 /// Read-only values (empty)
2203 pub mod R {}
2204 /// Write-only values (empty)
2205 pub mod W {}
2206 /// Read-write values
2207 pub mod RW {
2208
2209 /// 0b0: When inactive, OC/OCN outputs are disabled
2210 pub const Disabled: u32 = 0b0;
2211
2212 /// 0b1: When inactive, OC/OCN outputs are forced to idle level
2213 pub const IdleLevel: u32 = 0b1;
2214 }
2215 }
2216
2217 /// Lock configuration
2218 pub mod LOCK {
2219 /// Offset (8 bits)
2220 pub const offset: u32 = 8;
2221 /// Mask (2 bits: 0b11 << 8)
2222 pub const mask: u32 = 0b11 << offset;
2223 /// Read-only values (empty)
2224 pub mod R {}
2225 /// Write-only values (empty)
2226 pub mod W {}
2227 /// Read-write values (empty)
2228 pub mod RW {}
2229 }
2230
2231 /// Dead-time generator setup
2232 pub mod DTG {
2233 /// Offset (0 bits)
2234 pub const offset: u32 = 0;
2235 /// Mask (8 bits: 0xff << 0)
2236 pub const mask: u32 = 0xff << offset;
2237 /// Read-only values (empty)
2238 pub mod R {}
2239 /// Write-only values (empty)
2240 pub mod W {}
2241 /// Read-write values (empty)
2242 pub mod RW {}
2243 }
2244}
2245#[repr(C)]
2246pub struct RegisterBlock {
2247 /// control register 1
2248 pub CR1: RWRegister<u32>,
2249
2250 /// control register 2
2251 pub CR2: RWRegister<u32>,
2252
2253 /// slave mode control register
2254 pub SMCR: RWRegister<u32>,
2255
2256 /// DMA/Interrupt enable register
2257 pub DIER: RWRegister<u32>,
2258
2259 /// status register
2260 pub SR: RWRegister<u32>,
2261
2262 /// event generation register
2263 pub EGR: WORegister<u32>,
2264
2265 /// CCMR1_Output and CCMR1_Input
2266 /// CCMR1_Output: capture/compare mode register (output mode)
2267 /// CCMR1_Input: capture/compare mode register 1 (input mode)
2268 pub CCMR1: RWRegister<u32>,
2269
2270 /// CCMR2_Output and CCMR2_Input
2271 /// CCMR2_Output: capture/compare mode register (output mode)
2272 /// CCMR2_Input: capture/compare mode register 2 (input mode)
2273 pub CCMR2: RWRegister<u32>,
2274
2275 /// capture/compare enable register
2276 pub CCER: RWRegister<u32>,
2277
2278 /// counter
2279 pub CNT: RWRegister<u32>,
2280
2281 /// prescaler
2282 pub PSC: RWRegister<u32>,
2283
2284 /// auto-reload register
2285 pub ARR: RWRegister<u32>,
2286
2287 /// repetition counter register
2288 pub RCR: RWRegister<u32>,
2289
2290 /// capture/compare register
2291 pub CCR1: RWRegister<u32>,
2292
2293 /// capture/compare register
2294 pub CCR2: RWRegister<u32>,
2295
2296 /// capture/compare register
2297 pub CCR3: RWRegister<u32>,
2298
2299 /// capture/compare register
2300 pub CCR4: RWRegister<u32>,
2301
2302 /// break and dead-time register
2303 pub BDTR: RWRegister<u32>,
2304
2305 /// DMA control register
2306 pub DCR: RWRegister<u32>,
2307
2308 /// DMA address for full transfer
2309 pub DMAR: RWRegister<u32>,
2310}
2311pub struct ResetValues {
2312 pub CR1: u32,
2313 pub CR2: u32,
2314 pub SMCR: u32,
2315 pub DIER: u32,
2316 pub SR: u32,
2317 pub EGR: u32,
2318 pub CCMR1: u32,
2319 pub CCMR2: u32,
2320 pub CCER: u32,
2321 pub CNT: u32,
2322 pub PSC: u32,
2323 pub ARR: u32,
2324 pub RCR: u32,
2325 pub CCR1: u32,
2326 pub CCR2: u32,
2327 pub CCR3: u32,
2328 pub CCR4: u32,
2329 pub BDTR: u32,
2330 pub DCR: u32,
2331 pub DMAR: u32,
2332}
2333#[cfg(not(feature = "nosync"))]
2334pub struct Instance {
2335 pub(crate) addr: u32,
2336 pub(crate) _marker: PhantomData<*const RegisterBlock>,
2337}
2338#[cfg(not(feature = "nosync"))]
2339impl ::core::ops::Deref for Instance {
2340 type Target = RegisterBlock;
2341 #[inline(always)]
2342 fn deref(&self) -> &RegisterBlock {
2343 unsafe { &*(self.addr as *const _) }
2344 }
2345}
2346#[cfg(feature = "rtic")]
2347unsafe impl Send for Instance {}