stm32ral/stm32f1/peripherals/tim13.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! General purpose timer
4//!
5//! Used by: stm32f100, stm32f102, stm32f107
6
7use crate::{RWRegister, WORegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// control register 1
12pub mod CR1 {
13
14 /// Clock division
15 pub mod CKD {
16 /// Offset (8 bits)
17 pub const offset: u32 = 8;
18 /// Mask (2 bits: 0b11 << 8)
19 pub const mask: u32 = 0b11 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values
25 pub mod RW {
26
27 /// 0b00: t_DTS = t_CK_INT
28 pub const Div1: u32 = 0b00;
29
30 /// 0b01: t_DTS = 2 × t_CK_INT
31 pub const Div2: u32 = 0b01;
32
33 /// 0b10: t_DTS = 4 × t_CK_INT
34 pub const Div4: u32 = 0b10;
35 }
36 }
37
38 /// Auto-reload preload enable
39 pub mod ARPE {
40 /// Offset (7 bits)
41 pub const offset: u32 = 7;
42 /// Mask (1 bit: 1 << 7)
43 pub const mask: u32 = 1 << offset;
44 /// Read-only values (empty)
45 pub mod R {}
46 /// Write-only values (empty)
47 pub mod W {}
48 /// Read-write values
49 pub mod RW {
50
51 /// 0b0: TIMx_APRR register is not buffered
52 pub const Disabled: u32 = 0b0;
53
54 /// 0b1: TIMx_APRR register is buffered
55 pub const Enabled: u32 = 0b1;
56 }
57 }
58
59 /// Update request source
60 pub mod URS {
61 /// Offset (2 bits)
62 pub const offset: u32 = 2;
63 /// Mask (1 bit: 1 << 2)
64 pub const mask: u32 = 1 << offset;
65 /// Read-only values (empty)
66 pub mod R {}
67 /// Write-only values (empty)
68 pub mod W {}
69 /// Read-write values
70 pub mod RW {
71
72 /// 0b0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
73 pub const AnyEvent: u32 = 0b0;
74
75 /// 0b1: Only counter overflow/underflow generates an update interrupt or DMA request
76 pub const CounterOnly: u32 = 0b1;
77 }
78 }
79
80 /// Update disable
81 pub mod UDIS {
82 /// Offset (1 bits)
83 pub const offset: u32 = 1;
84 /// Mask (1 bit: 1 << 1)
85 pub const mask: u32 = 1 << offset;
86 /// Read-only values (empty)
87 pub mod R {}
88 /// Write-only values (empty)
89 pub mod W {}
90 /// Read-write values
91 pub mod RW {
92
93 /// 0b0: Update event enabled
94 pub const Enabled: u32 = 0b0;
95
96 /// 0b1: Update event disabled
97 pub const Disabled: u32 = 0b1;
98 }
99 }
100
101 /// Counter enable
102 pub mod CEN {
103 /// Offset (0 bits)
104 pub const offset: u32 = 0;
105 /// Mask (1 bit: 1 << 0)
106 pub const mask: u32 = 1 << offset;
107 /// Read-only values (empty)
108 pub mod R {}
109 /// Write-only values (empty)
110 pub mod W {}
111 /// Read-write values
112 pub mod RW {
113
114 /// 0b0: Counter disabled
115 pub const Disabled: u32 = 0b0;
116
117 /// 0b1: Counter enabled
118 pub const Enabled: u32 = 0b1;
119 }
120 }
121
122 /// One-pulse mode
123 pub mod OPM {
124 /// Offset (3 bits)
125 pub const offset: u32 = 3;
126 /// Mask (1 bit: 1 << 3)
127 pub const mask: u32 = 1 << offset;
128 /// Read-only values (empty)
129 pub mod R {}
130 /// Write-only values (empty)
131 pub mod W {}
132 /// Read-write values
133 pub mod RW {
134
135 /// 0b0: Counter is not stopped at update event
136 pub const Disabled: u32 = 0b0;
137
138 /// 0b1: Counter stops counting at the next update event (clearing the CEN bit)
139 pub const Enabled: u32 = 0b1;
140 }
141 }
142}
143
144/// DMA/Interrupt enable register
145pub mod DIER {
146
147 /// Capture/Compare 1 interrupt enable
148 pub mod CC1IE {
149 /// Offset (1 bits)
150 pub const offset: u32 = 1;
151 /// Mask (1 bit: 1 << 1)
152 pub const mask: u32 = 1 << offset;
153 /// Read-only values (empty)
154 pub mod R {}
155 /// Write-only values (empty)
156 pub mod W {}
157 /// Read-write values (empty)
158 pub mod RW {}
159 }
160
161 /// Update interrupt enable
162 pub mod UIE {
163 /// Offset (0 bits)
164 pub const offset: u32 = 0;
165 /// Mask (1 bit: 1 << 0)
166 pub const mask: u32 = 1 << offset;
167 /// Read-only values (empty)
168 pub mod R {}
169 /// Write-only values (empty)
170 pub mod W {}
171 /// Read-write values
172 pub mod RW {
173
174 /// 0b0: Update interrupt disabled
175 pub const Disabled: u32 = 0b0;
176
177 /// 0b1: Update interrupt enabled
178 pub const Enabled: u32 = 0b1;
179 }
180 }
181}
182
183/// status register
184pub mod SR {
185
186 /// Capture/Compare 1 overcapture flag
187 pub mod CC1OF {
188 /// Offset (9 bits)
189 pub const offset: u32 = 9;
190 /// Mask (1 bit: 1 << 9)
191 pub const mask: u32 = 1 << offset;
192 /// Read-only values (empty)
193 pub mod R {}
194 /// Write-only values (empty)
195 pub mod W {}
196 /// Read-write values (empty)
197 pub mod RW {}
198 }
199
200 /// Capture/compare 1 interrupt flag
201 pub mod CC1IF {
202 /// Offset (1 bits)
203 pub const offset: u32 = 1;
204 /// Mask (1 bit: 1 << 1)
205 pub const mask: u32 = 1 << offset;
206 /// Read-only values (empty)
207 pub mod R {}
208 /// Write-only values (empty)
209 pub mod W {}
210 /// Read-write values (empty)
211 pub mod RW {}
212 }
213
214 /// Update interrupt flag
215 pub mod UIF {
216 /// Offset (0 bits)
217 pub const offset: u32 = 0;
218 /// Mask (1 bit: 1 << 0)
219 pub const mask: u32 = 1 << offset;
220 /// Read-only values (empty)
221 pub mod R {}
222 /// Write-only values (empty)
223 pub mod W {}
224 /// Read-write values
225 pub mod RW {
226
227 /// 0b0: No update occurred
228 pub const Clear: u32 = 0b0;
229
230 /// 0b1: Update interrupt pending.
231 pub const UpdatePending: u32 = 0b1;
232 }
233 }
234}
235
236/// event generation register
237pub mod EGR {
238
239 /// Capture/compare 1 generation
240 pub mod CC1G {
241 /// Offset (1 bits)
242 pub const offset: u32 = 1;
243 /// Mask (1 bit: 1 << 1)
244 pub const mask: u32 = 1 << offset;
245 /// Read-only values (empty)
246 pub mod R {}
247 /// Write-only values (empty)
248 pub mod W {}
249 /// Read-write values (empty)
250 pub mod RW {}
251 }
252
253 /// Update generation
254 pub mod UG {
255 /// Offset (0 bits)
256 pub const offset: u32 = 0;
257 /// Mask (1 bit: 1 << 0)
258 pub const mask: u32 = 1 << offset;
259 /// Read-only values (empty)
260 pub mod R {}
261 /// Write-only values
262 pub mod W {
263
264 /// 0b1: Re-initializes the timer counter and generates an update of the registers.
265 pub const Update: u32 = 0b1;
266 }
267 /// Read-write values (empty)
268 pub mod RW {}
269 }
270}
271
272/// CCMR1_Output and CCMR1_Input
273/// CCMR1_Output: capture/compare mode register (output mode)
274/// CCMR1_Input: capture/compare mode register (input mode)
275pub mod CCMR1 {
276
277 /// Capture/Compare 1 selection
278 pub mod CC1S {
279 /// Offset (0 bits)
280 pub const offset: u32 = 0;
281 /// Mask (2 bits: 0b11 << 0)
282 pub const mask: u32 = 0b11 << offset;
283 /// Read-only values (empty)
284 pub mod R {}
285 /// Write-only values (empty)
286 pub mod W {}
287 /// Read-write values (empty)
288 pub mod RW {}
289 }
290
291 /// Output compare 1 fast enable
292 pub mod OC1FE {
293 /// Offset (2 bits)
294 pub const offset: u32 = 2;
295 /// Mask (1 bit: 1 << 2)
296 pub const mask: u32 = 1 << offset;
297 /// Read-only values (empty)
298 pub mod R {}
299 /// Write-only values (empty)
300 pub mod W {}
301 /// Read-write values (empty)
302 pub mod RW {}
303 }
304
305 /// Output Compare 1 preload enable
306 pub mod OC1PE {
307 /// Offset (3 bits)
308 pub const offset: u32 = 3;
309 /// Mask (1 bit: 1 << 3)
310 pub const mask: u32 = 1 << offset;
311 /// Read-only values (empty)
312 pub mod R {}
313 /// Write-only values (empty)
314 pub mod W {}
315 /// Read-write values (empty)
316 pub mod RW {}
317 }
318
319 /// Output Compare 1 mode
320 pub mod OC1M {
321 /// Offset (4 bits)
322 pub const offset: u32 = 4;
323 /// Mask (3 bits: 0b111 << 4)
324 pub const mask: u32 = 0b111 << offset;
325 /// Read-only values (empty)
326 pub mod R {}
327 /// Write-only values (empty)
328 pub mod W {}
329 /// Read-write values
330 pub mod RW {
331
332 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
333 pub const Frozen: u32 = 0b000;
334
335 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
336 pub const ActiveOnMatch: u32 = 0b001;
337
338 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
339 pub const InactiveOnMatch: u32 = 0b010;
340
341 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy
342 pub const Toggle: u32 = 0b011;
343
344 /// 0b100: OCyREF is forced low
345 pub const ForceInactive: u32 = 0b100;
346
347 /// 0b101: OCyREF is forced high
348 pub const ForceActive: u32 = 0b101;
349
350 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
351 pub const PwmMode1: u32 = 0b110;
352
353 /// 0b111: Inversely to PwmMode1
354 pub const PwmMode2: u32 = 0b111;
355 }
356 }
357
358 /// Input capture 1 filter
359 pub mod IC1F {
360 /// Offset (4 bits)
361 pub const offset: u32 = 4;
362 /// Mask (4 bits: 0b1111 << 4)
363 pub const mask: u32 = 0b1111 << offset;
364 /// Read-only values (empty)
365 pub mod R {}
366 /// Write-only values (empty)
367 pub mod W {}
368 /// Read-write values (empty)
369 pub mod RW {}
370 }
371
372 /// Input capture 1 prescaler
373 pub mod IC1PSC {
374 /// Offset (2 bits)
375 pub const offset: u32 = 2;
376 /// Mask (2 bits: 0b11 << 2)
377 pub const mask: u32 = 0b11 << offset;
378 /// Read-only values (empty)
379 pub mod R {}
380 /// Write-only values (empty)
381 pub mod W {}
382 /// Read-write values (empty)
383 pub mod RW {}
384 }
385}
386
387/// capture/compare enable register
388pub mod CCER {
389
390 /// Capture/Compare 1 output Polarity
391 pub mod CC1NP {
392 /// Offset (3 bits)
393 pub const offset: u32 = 3;
394 /// Mask (1 bit: 1 << 3)
395 pub const mask: u32 = 1 << offset;
396 /// Read-only values (empty)
397 pub mod R {}
398 /// Write-only values (empty)
399 pub mod W {}
400 /// Read-write values (empty)
401 pub mod RW {}
402 }
403
404 /// Capture/Compare 1 output Polarity
405 pub mod CC1P {
406 /// Offset (1 bits)
407 pub const offset: u32 = 1;
408 /// Mask (1 bit: 1 << 1)
409 pub const mask: u32 = 1 << offset;
410 /// Read-only values (empty)
411 pub mod R {}
412 /// Write-only values (empty)
413 pub mod W {}
414 /// Read-write values (empty)
415 pub mod RW {}
416 }
417
418 /// Capture/Compare 1 output enable
419 pub mod CC1E {
420 /// Offset (0 bits)
421 pub const offset: u32 = 0;
422 /// Mask (1 bit: 1 << 0)
423 pub const mask: u32 = 1 << offset;
424 /// Read-only values (empty)
425 pub mod R {}
426 /// Write-only values (empty)
427 pub mod W {}
428 /// Read-write values (empty)
429 pub mod RW {}
430 }
431}
432
433/// counter
434pub mod CNT {
435
436 /// counter value
437 pub mod CNT {
438 /// Offset (0 bits)
439 pub const offset: u32 = 0;
440 /// Mask (16 bits: 0xffff << 0)
441 pub const mask: u32 = 0xffff << offset;
442 /// Read-only values (empty)
443 pub mod R {}
444 /// Write-only values (empty)
445 pub mod W {}
446 /// Read-write values (empty)
447 pub mod RW {}
448 }
449}
450
451/// prescaler
452pub mod PSC {
453
454 /// Prescaler value
455 pub mod PSC {
456 /// Offset (0 bits)
457 pub const offset: u32 = 0;
458 /// Mask (16 bits: 0xffff << 0)
459 pub const mask: u32 = 0xffff << offset;
460 /// Read-only values (empty)
461 pub mod R {}
462 /// Write-only values (empty)
463 pub mod W {}
464 /// Read-write values (empty)
465 pub mod RW {}
466 }
467}
468
469/// auto-reload register
470pub mod ARR {
471
472 /// Auto-reload value
473 pub mod ARR {
474 /// Offset (0 bits)
475 pub const offset: u32 = 0;
476 /// Mask (16 bits: 0xffff << 0)
477 pub const mask: u32 = 0xffff << offset;
478 /// Read-only values (empty)
479 pub mod R {}
480 /// Write-only values (empty)
481 pub mod W {}
482 /// Read-write values (empty)
483 pub mod RW {}
484 }
485}
486
487/// capture/compare register
488pub mod CCR1 {
489
490 /// Capture/Compare value
491 pub mod CCR {
492 /// Offset (0 bits)
493 pub const offset: u32 = 0;
494 /// Mask (16 bits: 0xffff << 0)
495 pub const mask: u32 = 0xffff << offset;
496 /// Read-only values (empty)
497 pub mod R {}
498 /// Write-only values (empty)
499 pub mod W {}
500 /// Read-write values (empty)
501 pub mod RW {}
502 }
503}
504#[repr(C)]
505pub struct RegisterBlock {
506 /// control register 1
507 pub CR1: RWRegister<u32>,
508
509 _reserved1: [u8; 8],
510
511 /// DMA/Interrupt enable register
512 pub DIER: RWRegister<u32>,
513
514 /// status register
515 pub SR: RWRegister<u32>,
516
517 /// event generation register
518 pub EGR: WORegister<u32>,
519
520 /// CCMR1_Output and CCMR1_Input
521 /// CCMR1_Output: capture/compare mode register (output mode)
522 /// CCMR1_Input: capture/compare mode register (input mode)
523 pub CCMR1: RWRegister<u32>,
524
525 _reserved2: [u8; 4],
526
527 /// capture/compare enable register
528 pub CCER: RWRegister<u32>,
529
530 /// counter
531 pub CNT: RWRegister<u32>,
532
533 /// prescaler
534 pub PSC: RWRegister<u32>,
535
536 /// auto-reload register
537 pub ARR: RWRegister<u32>,
538
539 _reserved3: [u8; 4],
540
541 /// capture/compare register
542 pub CCR1: RWRegister<u32>,
543}
544pub struct ResetValues {
545 pub CR1: u32,
546 pub DIER: u32,
547 pub SR: u32,
548 pub EGR: u32,
549 pub CCMR1: u32,
550 pub CCER: u32,
551 pub CNT: u32,
552 pub PSC: u32,
553 pub ARR: u32,
554 pub CCR1: u32,
555}
556#[cfg(not(feature = "nosync"))]
557pub struct Instance {
558 pub(crate) addr: u32,
559 pub(crate) _marker: PhantomData<*const RegisterBlock>,
560}
561#[cfg(not(feature = "nosync"))]
562impl ::core::ops::Deref for Instance {
563 type Target = RegisterBlock;
564 #[inline(always)]
565 fn deref(&self) -> &RegisterBlock {
566 unsafe { &*(self.addr as *const _) }
567 }
568}
569#[cfg(feature = "rtic")]
570unsafe impl Send for Instance {}