stm32ral/stm32f1/peripherals/spi_v2.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Serial peripheral interface
4//!
5//! Used by: stm32f101, stm32f103, stm32f107
6
7use crate::{RORegister, RWRegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// control register 1
12pub mod CR1 {
13
14 /// Bidirectional data mode enable
15 pub mod BIDIMODE {
16 /// Offset (15 bits)
17 pub const offset: u32 = 15;
18 /// Mask (1 bit: 1 << 15)
19 pub const mask: u32 = 1 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values
25 pub mod RW {
26
27 /// 0b0: 2-line unidirectional data mode selected
28 pub const Unidirectional: u32 = 0b0;
29
30 /// 0b1: 1-line bidirectional data mode selected
31 pub const Bidirectional: u32 = 0b1;
32 }
33 }
34
35 /// Output enable in bidirectional mode
36 pub mod BIDIOE {
37 /// Offset (14 bits)
38 pub const offset: u32 = 14;
39 /// Mask (1 bit: 1 << 14)
40 pub const mask: u32 = 1 << offset;
41 /// Read-only values (empty)
42 pub mod R {}
43 /// Write-only values (empty)
44 pub mod W {}
45 /// Read-write values
46 pub mod RW {
47
48 /// 0b0: Output disabled (receive-only mode)
49 pub const OutputDisabled: u32 = 0b0;
50
51 /// 0b1: Output enabled (transmit-only mode)
52 pub const OutputEnabled: u32 = 0b1;
53 }
54 }
55
56 /// Hardware CRC calculation enable
57 pub mod CRCEN {
58 /// Offset (13 bits)
59 pub const offset: u32 = 13;
60 /// Mask (1 bit: 1 << 13)
61 pub const mask: u32 = 1 << offset;
62 /// Read-only values (empty)
63 pub mod R {}
64 /// Write-only values (empty)
65 pub mod W {}
66 /// Read-write values
67 pub mod RW {
68
69 /// 0b0: CRC calculation disabled
70 pub const Disabled: u32 = 0b0;
71
72 /// 0b1: CRC calculation enabled
73 pub const Enabled: u32 = 0b1;
74 }
75 }
76
77 /// CRC transfer next
78 pub mod CRCNEXT {
79 /// Offset (12 bits)
80 pub const offset: u32 = 12;
81 /// Mask (1 bit: 1 << 12)
82 pub const mask: u32 = 1 << offset;
83 /// Read-only values (empty)
84 pub mod R {}
85 /// Write-only values (empty)
86 pub mod W {}
87 /// Read-write values
88 pub mod RW {
89
90 /// 0b0: Next transmit value is from Tx buffer
91 pub const TxBuffer: u32 = 0b0;
92
93 /// 0b1: Next transmit value is from Tx CRC register
94 pub const CRC: u32 = 0b1;
95 }
96 }
97
98 /// Data frame format
99 pub mod DFF {
100 /// Offset (11 bits)
101 pub const offset: u32 = 11;
102 /// Mask (1 bit: 1 << 11)
103 pub const mask: u32 = 1 << offset;
104 /// Read-only values (empty)
105 pub mod R {}
106 /// Write-only values (empty)
107 pub mod W {}
108 /// Read-write values
109 pub mod RW {
110
111 /// 0b0: 8-bit data frame format is selected for transmission/reception
112 pub const EightBit: u32 = 0b0;
113
114 /// 0b1: 16-bit data frame format is selected for transmission/reception
115 pub const SixteenBit: u32 = 0b1;
116 }
117 }
118
119 /// Receive only
120 pub mod RXONLY {
121 /// Offset (10 bits)
122 pub const offset: u32 = 10;
123 /// Mask (1 bit: 1 << 10)
124 pub const mask: u32 = 1 << offset;
125 /// Read-only values (empty)
126 pub mod R {}
127 /// Write-only values (empty)
128 pub mod W {}
129 /// Read-write values
130 pub mod RW {
131
132 /// 0b0: Full duplex (Transmit and receive)
133 pub const FullDuplex: u32 = 0b0;
134
135 /// 0b1: Output disabled (Receive-only mode)
136 pub const OutputDisabled: u32 = 0b1;
137 }
138 }
139
140 /// Software slave management
141 pub mod SSM {
142 /// Offset (9 bits)
143 pub const offset: u32 = 9;
144 /// Mask (1 bit: 1 << 9)
145 pub const mask: u32 = 1 << offset;
146 /// Read-only values (empty)
147 pub mod R {}
148 /// Write-only values (empty)
149 pub mod W {}
150 /// Read-write values
151 pub mod RW {
152
153 /// 0b0: Software slave management disabled
154 pub const Disabled: u32 = 0b0;
155
156 /// 0b1: Software slave management enabled
157 pub const Enabled: u32 = 0b1;
158 }
159 }
160
161 /// Internal slave select
162 pub mod SSI {
163 /// Offset (8 bits)
164 pub const offset: u32 = 8;
165 /// Mask (1 bit: 1 << 8)
166 pub const mask: u32 = 1 << offset;
167 /// Read-only values (empty)
168 pub mod R {}
169 /// Write-only values (empty)
170 pub mod W {}
171 /// Read-write values
172 pub mod RW {
173
174 /// 0b0: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
175 pub const SlaveSelected: u32 = 0b0;
176
177 /// 0b1: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
178 pub const SlaveNotSelected: u32 = 0b1;
179 }
180 }
181
182 /// Frame format
183 pub mod LSBFIRST {
184 /// Offset (7 bits)
185 pub const offset: u32 = 7;
186 /// Mask (1 bit: 1 << 7)
187 pub const mask: u32 = 1 << offset;
188 /// Read-only values (empty)
189 pub mod R {}
190 /// Write-only values (empty)
191 pub mod W {}
192 /// Read-write values
193 pub mod RW {
194
195 /// 0b0: Data is transmitted/received with the MSB first
196 pub const MSBFirst: u32 = 0b0;
197
198 /// 0b1: Data is transmitted/received with the LSB first
199 pub const LSBFirst: u32 = 0b1;
200 }
201 }
202
203 /// SPI enable
204 pub mod SPE {
205 /// Offset (6 bits)
206 pub const offset: u32 = 6;
207 /// Mask (1 bit: 1 << 6)
208 pub const mask: u32 = 1 << offset;
209 /// Read-only values (empty)
210 pub mod R {}
211 /// Write-only values (empty)
212 pub mod W {}
213 /// Read-write values
214 pub mod RW {
215
216 /// 0b0: Peripheral disabled
217 pub const Disabled: u32 = 0b0;
218
219 /// 0b1: Peripheral enabled
220 pub const Enabled: u32 = 0b1;
221 }
222 }
223
224 /// Baud rate control
225 pub mod BR {
226 /// Offset (3 bits)
227 pub const offset: u32 = 3;
228 /// Mask (3 bits: 0b111 << 3)
229 pub const mask: u32 = 0b111 << offset;
230 /// Read-only values (empty)
231 pub mod R {}
232 /// Write-only values (empty)
233 pub mod W {}
234 /// Read-write values
235 pub mod RW {
236
237 /// 0b000: f_PCLK / 2
238 pub const Div2: u32 = 0b000;
239
240 /// 0b001: f_PCLK / 4
241 pub const Div4: u32 = 0b001;
242
243 /// 0b010: f_PCLK / 8
244 pub const Div8: u32 = 0b010;
245
246 /// 0b011: f_PCLK / 16
247 pub const Div16: u32 = 0b011;
248
249 /// 0b100: f_PCLK / 32
250 pub const Div32: u32 = 0b100;
251
252 /// 0b101: f_PCLK / 64
253 pub const Div64: u32 = 0b101;
254
255 /// 0b110: f_PCLK / 128
256 pub const Div128: u32 = 0b110;
257
258 /// 0b111: f_PCLK / 256
259 pub const Div256: u32 = 0b111;
260 }
261 }
262
263 /// Master selection
264 pub mod MSTR {
265 /// Offset (2 bits)
266 pub const offset: u32 = 2;
267 /// Mask (1 bit: 1 << 2)
268 pub const mask: u32 = 1 << offset;
269 /// Read-only values (empty)
270 pub mod R {}
271 /// Write-only values (empty)
272 pub mod W {}
273 /// Read-write values
274 pub mod RW {
275
276 /// 0b0: Slave configuration
277 pub const Slave: u32 = 0b0;
278
279 /// 0b1: Master configuration
280 pub const Master: u32 = 0b1;
281 }
282 }
283
284 /// Clock polarity
285 pub mod CPOL {
286 /// Offset (1 bits)
287 pub const offset: u32 = 1;
288 /// Mask (1 bit: 1 << 1)
289 pub const mask: u32 = 1 << offset;
290 /// Read-only values (empty)
291 pub mod R {}
292 /// Write-only values (empty)
293 pub mod W {}
294 /// Read-write values
295 pub mod RW {
296
297 /// 0b0: CK to 0 when idle
298 pub const IdleLow: u32 = 0b0;
299
300 /// 0b1: CK to 1 when idle
301 pub const IdleHigh: u32 = 0b1;
302 }
303 }
304
305 /// Clock phase
306 pub mod CPHA {
307 /// Offset (0 bits)
308 pub const offset: u32 = 0;
309 /// Mask (1 bit: 1 << 0)
310 pub const mask: u32 = 1 << offset;
311 /// Read-only values (empty)
312 pub mod R {}
313 /// Write-only values (empty)
314 pub mod W {}
315 /// Read-write values
316 pub mod RW {
317
318 /// 0b0: The first clock transition is the first data capture edge
319 pub const FirstEdge: u32 = 0b0;
320
321 /// 0b1: The second clock transition is the first data capture edge
322 pub const SecondEdge: u32 = 0b1;
323 }
324 }
325}
326
327/// control register 2
328pub mod CR2 {
329
330 /// Tx buffer empty interrupt enable
331 pub mod TXEIE {
332 /// Offset (7 bits)
333 pub const offset: u32 = 7;
334 /// Mask (1 bit: 1 << 7)
335 pub const mask: u32 = 1 << offset;
336 /// Read-only values (empty)
337 pub mod R {}
338 /// Write-only values (empty)
339 pub mod W {}
340 /// Read-write values
341 pub mod RW {
342
343 /// 0b0: TXE interrupt masked
344 pub const Masked: u32 = 0b0;
345
346 /// 0b1: TXE interrupt not masked
347 pub const NotMasked: u32 = 0b1;
348 }
349 }
350
351 /// RX buffer not empty interrupt enable
352 pub mod RXNEIE {
353 /// Offset (6 bits)
354 pub const offset: u32 = 6;
355 /// Mask (1 bit: 1 << 6)
356 pub const mask: u32 = 1 << offset;
357 /// Read-only values (empty)
358 pub mod R {}
359 /// Write-only values (empty)
360 pub mod W {}
361 /// Read-write values
362 pub mod RW {
363
364 /// 0b0: RXE interrupt masked
365 pub const Masked: u32 = 0b0;
366
367 /// 0b1: RXE interrupt not masked
368 pub const NotMasked: u32 = 0b1;
369 }
370 }
371
372 /// Error interrupt enable
373 pub mod ERRIE {
374 /// Offset (5 bits)
375 pub const offset: u32 = 5;
376 /// Mask (1 bit: 1 << 5)
377 pub const mask: u32 = 1 << offset;
378 /// Read-only values (empty)
379 pub mod R {}
380 /// Write-only values (empty)
381 pub mod W {}
382 /// Read-write values
383 pub mod RW {
384
385 /// 0b0: Error interrupt masked
386 pub const Masked: u32 = 0b0;
387
388 /// 0b1: Error interrupt not masked
389 pub const NotMasked: u32 = 0b1;
390 }
391 }
392
393 /// SS output enable
394 pub mod SSOE {
395 /// Offset (2 bits)
396 pub const offset: u32 = 2;
397 /// Mask (1 bit: 1 << 2)
398 pub const mask: u32 = 1 << offset;
399 /// Read-only values (empty)
400 pub mod R {}
401 /// Write-only values (empty)
402 pub mod W {}
403 /// Read-write values
404 pub mod RW {
405
406 /// 0b0: SS output is disabled in master mode
407 pub const Disabled: u32 = 0b0;
408
409 /// 0b1: SS output is enabled in master mode
410 pub const Enabled: u32 = 0b1;
411 }
412 }
413
414 /// Tx buffer DMA enable
415 pub mod TXDMAEN {
416 /// Offset (1 bits)
417 pub const offset: u32 = 1;
418 /// Mask (1 bit: 1 << 1)
419 pub const mask: u32 = 1 << offset;
420 /// Read-only values (empty)
421 pub mod R {}
422 /// Write-only values (empty)
423 pub mod W {}
424 /// Read-write values
425 pub mod RW {
426
427 /// 0b0: Tx buffer DMA disabled
428 pub const Disabled: u32 = 0b0;
429
430 /// 0b1: Tx buffer DMA enabled
431 pub const Enabled: u32 = 0b1;
432 }
433 }
434
435 /// Rx buffer DMA enable
436 pub mod RXDMAEN {
437 /// Offset (0 bits)
438 pub const offset: u32 = 0;
439 /// Mask (1 bit: 1 << 0)
440 pub const mask: u32 = 1 << offset;
441 /// Read-only values (empty)
442 pub mod R {}
443 /// Write-only values (empty)
444 pub mod W {}
445 /// Read-write values
446 pub mod RW {
447
448 /// 0b0: Rx buffer DMA disabled
449 pub const Disabled: u32 = 0b0;
450
451 /// 0b1: Rx buffer DMA enabled
452 pub const Enabled: u32 = 0b1;
453 }
454 }
455}
456
457/// status register
458pub mod SR {
459
460 /// Busy flag
461 pub mod BSY {
462 /// Offset (7 bits)
463 pub const offset: u32 = 7;
464 /// Mask (1 bit: 1 << 7)
465 pub const mask: u32 = 1 << offset;
466 /// Read-only values
467 pub mod R {
468
469 /// 0b0: SPI not busy
470 pub const NotBusy: u32 = 0b0;
471
472 /// 0b1: SPI busy
473 pub const Busy: u32 = 0b1;
474 }
475 /// Write-only values (empty)
476 pub mod W {}
477 /// Read-write values (empty)
478 pub mod RW {}
479 }
480
481 /// Overrun flag
482 pub mod OVR {
483 /// Offset (6 bits)
484 pub const offset: u32 = 6;
485 /// Mask (1 bit: 1 << 6)
486 pub const mask: u32 = 1 << offset;
487 /// Read-only values
488 pub mod R {
489
490 /// 0b0: No overrun occurred
491 pub const NoOverrun: u32 = 0b0;
492
493 /// 0b1: Overrun occurred
494 pub const Overrun: u32 = 0b1;
495 }
496 /// Write-only values (empty)
497 pub mod W {}
498 /// Read-write values (empty)
499 pub mod RW {}
500 }
501
502 /// Mode fault
503 pub mod MODF {
504 /// Offset (5 bits)
505 pub const offset: u32 = 5;
506 /// Mask (1 bit: 1 << 5)
507 pub const mask: u32 = 1 << offset;
508 /// Read-only values
509 pub mod R {
510
511 /// 0b0: No mode fault occurred
512 pub const NoFault: u32 = 0b0;
513
514 /// 0b1: Mode fault occurred
515 pub const Fault: u32 = 0b1;
516 }
517 /// Write-only values (empty)
518 pub mod W {}
519 /// Read-write values (empty)
520 pub mod RW {}
521 }
522
523 /// CRC error flag
524 pub mod CRCERR {
525 /// Offset (4 bits)
526 pub const offset: u32 = 4;
527 /// Mask (1 bit: 1 << 4)
528 pub const mask: u32 = 1 << offset;
529 /// Read-only values (empty)
530 pub mod R {}
531 /// Write-only values (empty)
532 pub mod W {}
533 /// Read-write values
534 pub mod RW {
535
536 /// 0b0: CRC value received matches the SPIx_RXCRCR value
537 pub const Match: u32 = 0b0;
538
539 /// 0b1: CRC value received does not match the SPIx_RXCRCR value
540 pub const NoMatch: u32 = 0b1;
541 }
542 }
543
544 /// Underrun flag
545 pub mod UDR {
546 /// Offset (3 bits)
547 pub const offset: u32 = 3;
548 /// Mask (1 bit: 1 << 3)
549 pub const mask: u32 = 1 << offset;
550 /// Read-only values
551 pub mod R {
552
553 /// 0b0: No underrun occurred
554 pub const NoUnderrun: u32 = 0b0;
555
556 /// 0b1: Underrun occurred
557 pub const Underrun: u32 = 0b1;
558 }
559 /// Write-only values (empty)
560 pub mod W {}
561 /// Read-write values (empty)
562 pub mod RW {}
563 }
564
565 /// Channel side
566 pub mod CHSIDE {
567 /// Offset (2 bits)
568 pub const offset: u32 = 2;
569 /// Mask (1 bit: 1 << 2)
570 pub const mask: u32 = 1 << offset;
571 /// Read-only values
572 pub mod R {
573
574 /// 0b0: Channel left has to be transmitted or has been received
575 pub const Left: u32 = 0b0;
576
577 /// 0b1: Channel right has to be transmitted or has been received
578 pub const Right: u32 = 0b1;
579 }
580 /// Write-only values (empty)
581 pub mod W {}
582 /// Read-write values (empty)
583 pub mod RW {}
584 }
585
586 /// Transmit buffer empty
587 pub mod TXE {
588 /// Offset (1 bits)
589 pub const offset: u32 = 1;
590 /// Mask (1 bit: 1 << 1)
591 pub const mask: u32 = 1 << offset;
592 /// Read-only values
593 pub mod R {
594
595 /// 0b0: Tx buffer not empty
596 pub const NotEmpty: u32 = 0b0;
597
598 /// 0b1: Tx buffer empty
599 pub const Empty: u32 = 0b1;
600 }
601 /// Write-only values (empty)
602 pub mod W {}
603 /// Read-write values (empty)
604 pub mod RW {}
605 }
606
607 /// Receive buffer not empty
608 pub mod RXNE {
609 /// Offset (0 bits)
610 pub const offset: u32 = 0;
611 /// Mask (1 bit: 1 << 0)
612 pub const mask: u32 = 1 << offset;
613 /// Read-only values
614 pub mod R {
615
616 /// 0b0: Rx buffer empty
617 pub const Empty: u32 = 0b0;
618
619 /// 0b1: Rx buffer not empty
620 pub const NotEmpty: u32 = 0b1;
621 }
622 /// Write-only values (empty)
623 pub mod W {}
624 /// Read-write values (empty)
625 pub mod RW {}
626 }
627}
628
629/// data register
630pub mod DR {
631
632 /// Data register
633 pub mod DR {
634 /// Offset (0 bits)
635 pub const offset: u32 = 0;
636 /// Mask (16 bits: 0xffff << 0)
637 pub const mask: u32 = 0xffff << offset;
638 /// Read-only values (empty)
639 pub mod R {}
640 /// Write-only values (empty)
641 pub mod W {}
642 /// Read-write values (empty)
643 pub mod RW {}
644 }
645}
646
647/// CRC polynomial register
648pub mod CRCPR {
649
650 /// CRC polynomial register
651 pub mod CRCPOLY {
652 /// Offset (0 bits)
653 pub const offset: u32 = 0;
654 /// Mask (16 bits: 0xffff << 0)
655 pub const mask: u32 = 0xffff << offset;
656 /// Read-only values (empty)
657 pub mod R {}
658 /// Write-only values (empty)
659 pub mod W {}
660 /// Read-write values (empty)
661 pub mod RW {}
662 }
663}
664
665/// RX CRC register
666pub mod RXCRCR {
667
668 /// Rx CRC register
669 pub mod RxCRC {
670 /// Offset (0 bits)
671 pub const offset: u32 = 0;
672 /// Mask (16 bits: 0xffff << 0)
673 pub const mask: u32 = 0xffff << offset;
674 /// Read-only values (empty)
675 pub mod R {}
676 /// Write-only values (empty)
677 pub mod W {}
678 /// Read-write values (empty)
679 pub mod RW {}
680 }
681}
682
683/// TX CRC register
684pub mod TXCRCR {
685
686 /// Tx CRC register
687 pub mod TxCRC {
688 /// Offset (0 bits)
689 pub const offset: u32 = 0;
690 /// Mask (16 bits: 0xffff << 0)
691 pub const mask: u32 = 0xffff << offset;
692 /// Read-only values (empty)
693 pub mod R {}
694 /// Write-only values (empty)
695 pub mod W {}
696 /// Read-write values (empty)
697 pub mod RW {}
698 }
699}
700
701/// I2S configuration register
702pub mod I2SCFGR {
703
704 /// I2S mode selection
705 pub mod I2SMOD {
706 /// Offset (11 bits)
707 pub const offset: u32 = 11;
708 /// Mask (1 bit: 1 << 11)
709 pub const mask: u32 = 1 << offset;
710 /// Read-only values (empty)
711 pub mod R {}
712 /// Write-only values (empty)
713 pub mod W {}
714 /// Read-write values
715 pub mod RW {
716
717 /// 0b0: SPI mode is selected
718 pub const SPIMode: u32 = 0b0;
719
720 /// 0b1: I2S mode is selected
721 pub const I2SMode: u32 = 0b1;
722 }
723 }
724
725 /// I2S Enable
726 pub mod I2SE {
727 /// Offset (10 bits)
728 pub const offset: u32 = 10;
729 /// Mask (1 bit: 1 << 10)
730 pub const mask: u32 = 1 << offset;
731 /// Read-only values (empty)
732 pub mod R {}
733 /// Write-only values (empty)
734 pub mod W {}
735 /// Read-write values
736 pub mod RW {
737
738 /// 0b0: I2S peripheral is disabled
739 pub const Disabled: u32 = 0b0;
740
741 /// 0b1: I2S peripheral is enabled
742 pub const Enabled: u32 = 0b1;
743 }
744 }
745
746 /// I2S configuration mode
747 pub mod I2SCFG {
748 /// Offset (8 bits)
749 pub const offset: u32 = 8;
750 /// Mask (2 bits: 0b11 << 8)
751 pub const mask: u32 = 0b11 << offset;
752 /// Read-only values (empty)
753 pub mod R {}
754 /// Write-only values (empty)
755 pub mod W {}
756 /// Read-write values
757 pub mod RW {
758
759 /// 0b00: Slave - transmit
760 pub const SlaveTx: u32 = 0b00;
761
762 /// 0b01: Slave - receive
763 pub const SlaveRx: u32 = 0b01;
764
765 /// 0b10: Master - transmit
766 pub const MasterTx: u32 = 0b10;
767
768 /// 0b11: Master - receive
769 pub const MasterRx: u32 = 0b11;
770 }
771 }
772
773 /// PCM frame synchronization
774 pub mod PCMSYNC {
775 /// Offset (7 bits)
776 pub const offset: u32 = 7;
777 /// Mask (1 bit: 1 << 7)
778 pub const mask: u32 = 1 << offset;
779 /// Read-only values (empty)
780 pub mod R {}
781 /// Write-only values (empty)
782 pub mod W {}
783 /// Read-write values
784 pub mod RW {
785
786 /// 0b0: Short frame synchronisation
787 pub const Short: u32 = 0b0;
788
789 /// 0b1: Long frame synchronisation
790 pub const Long: u32 = 0b1;
791 }
792 }
793
794 /// I2S standard selection
795 pub mod I2SSTD {
796 /// Offset (4 bits)
797 pub const offset: u32 = 4;
798 /// Mask (2 bits: 0b11 << 4)
799 pub const mask: u32 = 0b11 << offset;
800 /// Read-only values (empty)
801 pub mod R {}
802 /// Write-only values (empty)
803 pub mod W {}
804 /// Read-write values
805 pub mod RW {
806
807 /// 0b00: I2S Philips standard
808 pub const Philips: u32 = 0b00;
809
810 /// 0b01: MSB justified standard
811 pub const MSB: u32 = 0b01;
812
813 /// 0b10: LSB justified standard
814 pub const LSB: u32 = 0b10;
815
816 /// 0b11: PCM standard
817 pub const PCM: u32 = 0b11;
818 }
819 }
820
821 /// Steady state clock polarity
822 pub mod CKPOL {
823 /// Offset (3 bits)
824 pub const offset: u32 = 3;
825 /// Mask (1 bit: 1 << 3)
826 pub const mask: u32 = 1 << offset;
827 /// Read-only values (empty)
828 pub mod R {}
829 /// Write-only values (empty)
830 pub mod W {}
831 /// Read-write values
832 pub mod RW {
833
834 /// 0b0: I2S clock inactive state is low level
835 pub const IdleLow: u32 = 0b0;
836
837 /// 0b1: I2S clock inactive state is high level
838 pub const IdleHigh: u32 = 0b1;
839 }
840 }
841
842 /// Data length to be transferred
843 pub mod DATLEN {
844 /// Offset (1 bits)
845 pub const offset: u32 = 1;
846 /// Mask (2 bits: 0b11 << 1)
847 pub const mask: u32 = 0b11 << offset;
848 /// Read-only values (empty)
849 pub mod R {}
850 /// Write-only values (empty)
851 pub mod W {}
852 /// Read-write values
853 pub mod RW {
854
855 /// 0b00: 16-bit data length
856 pub const SixteenBit: u32 = 0b00;
857
858 /// 0b01: 24-bit data length
859 pub const TwentyFourBit: u32 = 0b01;
860
861 /// 0b10: 32-bit data length
862 pub const ThirtyTwoBit: u32 = 0b10;
863 }
864 }
865
866 /// Channel length (number of bits per audio channel)
867 pub mod CHLEN {
868 /// Offset (0 bits)
869 pub const offset: u32 = 0;
870 /// Mask (1 bit: 1 << 0)
871 pub const mask: u32 = 1 << offset;
872 /// Read-only values (empty)
873 pub mod R {}
874 /// Write-only values (empty)
875 pub mod W {}
876 /// Read-write values
877 pub mod RW {
878
879 /// 0b0: 16-bit wide
880 pub const SixteenBit: u32 = 0b0;
881
882 /// 0b1: 32-bit wide
883 pub const ThirtyTwoBit: u32 = 0b1;
884 }
885 }
886}
887
888/// I2S prescaler register
889pub mod I2SPR {
890
891 /// Master clock output enable
892 pub mod MCKOE {
893 /// Offset (9 bits)
894 pub const offset: u32 = 9;
895 /// Mask (1 bit: 1 << 9)
896 pub const mask: u32 = 1 << offset;
897 /// Read-only values (empty)
898 pub mod R {}
899 /// Write-only values (empty)
900 pub mod W {}
901 /// Read-write values
902 pub mod RW {
903
904 /// 0b0: Master clock output is disabled
905 pub const Disabled: u32 = 0b0;
906
907 /// 0b1: Master clock output is enabled
908 pub const Enabled: u32 = 0b1;
909 }
910 }
911
912 /// Odd factor for the prescaler
913 pub mod ODD {
914 /// Offset (8 bits)
915 pub const offset: u32 = 8;
916 /// Mask (1 bit: 1 << 8)
917 pub const mask: u32 = 1 << offset;
918 /// Read-only values (empty)
919 pub mod R {}
920 /// Write-only values (empty)
921 pub mod W {}
922 /// Read-write values
923 pub mod RW {
924
925 /// 0b0: Real divider value is I2SDIV * 2
926 pub const Even: u32 = 0b0;
927
928 /// 0b1: Real divider value is (I2SDIV * 2) + 1
929 pub const Odd: u32 = 0b1;
930 }
931 }
932
933 /// I2S Linear prescaler
934 pub mod I2SDIV {
935 /// Offset (0 bits)
936 pub const offset: u32 = 0;
937 /// Mask (8 bits: 0xff << 0)
938 pub const mask: u32 = 0xff << offset;
939 /// Read-only values (empty)
940 pub mod R {}
941 /// Write-only values (empty)
942 pub mod W {}
943 /// Read-write values (empty)
944 pub mod RW {}
945 }
946}
947#[repr(C)]
948pub struct RegisterBlock {
949 /// control register 1
950 pub CR1: RWRegister<u32>,
951
952 /// control register 2
953 pub CR2: RWRegister<u32>,
954
955 /// status register
956 pub SR: RWRegister<u32>,
957
958 /// data register
959 pub DR: RWRegister<u32>,
960
961 /// CRC polynomial register
962 pub CRCPR: RWRegister<u32>,
963
964 /// RX CRC register
965 pub RXCRCR: RORegister<u32>,
966
967 /// TX CRC register
968 pub TXCRCR: RORegister<u32>,
969
970 /// I2S configuration register
971 pub I2SCFGR: RWRegister<u32>,
972
973 /// I2S prescaler register
974 pub I2SPR: RWRegister<u32>,
975}
976pub struct ResetValues {
977 pub CR1: u32,
978 pub CR2: u32,
979 pub SR: u32,
980 pub DR: u32,
981 pub CRCPR: u32,
982 pub RXCRCR: u32,
983 pub TXCRCR: u32,
984 pub I2SCFGR: u32,
985 pub I2SPR: u32,
986}
987#[cfg(not(feature = "nosync"))]
988pub struct Instance {
989 pub(crate) addr: u32,
990 pub(crate) _marker: PhantomData<*const RegisterBlock>,
991}
992#[cfg(not(feature = "nosync"))]
993impl ::core::ops::Deref for Instance {
994 type Target = RegisterBlock;
995 #[inline(always)]
996 fn deref(&self) -> &RegisterBlock {
997 unsafe { &*(self.addr as *const _) }
998 }
999}
1000#[cfg(feature = "rtic")]
1001unsafe impl Send for Instance {}