stm32ral/stm32f1/peripherals/
pwr.rs

1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Power control
4//!
5//! Used by: stm32f100, stm32f101, stm32f102, stm32f103, stm32f107
6
7use crate::RWRegister;
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// Power control register (PWR_CR)
12pub mod CR {
13
14    /// Low Power Deep Sleep
15    pub mod LPDS {
16        /// Offset (0 bits)
17        pub const offset: u32 = 0;
18        /// Mask (1 bit: 1 << 0)
19        pub const mask: u32 = 1 << offset;
20        /// Read-only values (empty)
21        pub mod R {}
22        /// Write-only values (empty)
23        pub mod W {}
24        /// Read-write values (empty)
25        pub mod RW {}
26    }
27
28    /// Power Down Deep Sleep
29    pub mod PDDS {
30        /// Offset (1 bits)
31        pub const offset: u32 = 1;
32        /// Mask (1 bit: 1 << 1)
33        pub const mask: u32 = 1 << offset;
34        /// Read-only values (empty)
35        pub mod R {}
36        /// Write-only values (empty)
37        pub mod W {}
38        /// Read-write values
39        pub mod RW {
40
41            /// 0b0: Enter Stop mode when the CPU enters deepsleep
42            pub const STOP_MODE: u32 = 0b0;
43
44            /// 0b1: Enter Standby mode when the CPU enters deepsleep
45            pub const STANDBY_MODE: u32 = 0b1;
46        }
47    }
48
49    /// Clear Wake-up Flag
50    pub mod CWUF {
51        /// Offset (2 bits)
52        pub const offset: u32 = 2;
53        /// Mask (1 bit: 1 << 2)
54        pub const mask: u32 = 1 << offset;
55        /// Read-only values (empty)
56        pub mod R {}
57        /// Write-only values (empty)
58        pub mod W {}
59        /// Read-write values (empty)
60        pub mod RW {}
61    }
62
63    /// Clear STANDBY Flag
64    pub mod CSBF {
65        /// Offset (3 bits)
66        pub const offset: u32 = 3;
67        /// Mask (1 bit: 1 << 3)
68        pub const mask: u32 = 1 << offset;
69        /// Read-only values (empty)
70        pub mod R {}
71        /// Write-only values (empty)
72        pub mod W {}
73        /// Read-write values (empty)
74        pub mod RW {}
75    }
76
77    /// Power Voltage Detector Enable
78    pub mod PVDE {
79        /// Offset (4 bits)
80        pub const offset: u32 = 4;
81        /// Mask (1 bit: 1 << 4)
82        pub const mask: u32 = 1 << offset;
83        /// Read-only values (empty)
84        pub mod R {}
85        /// Write-only values (empty)
86        pub mod W {}
87        /// Read-write values (empty)
88        pub mod RW {}
89    }
90
91    /// PVD Level Selection
92    pub mod PLS {
93        /// Offset (5 bits)
94        pub const offset: u32 = 5;
95        /// Mask (3 bits: 0b111 << 5)
96        pub const mask: u32 = 0b111 << offset;
97        /// Read-only values (empty)
98        pub mod R {}
99        /// Write-only values (empty)
100        pub mod W {}
101        /// Read-write values (empty)
102        pub mod RW {}
103    }
104
105    /// Disable Backup Domain write protection
106    pub mod DBP {
107        /// Offset (8 bits)
108        pub const offset: u32 = 8;
109        /// Mask (1 bit: 1 << 8)
110        pub const mask: u32 = 1 << offset;
111        /// Read-only values (empty)
112        pub mod R {}
113        /// Write-only values (empty)
114        pub mod W {}
115        /// Read-write values (empty)
116        pub mod RW {}
117    }
118}
119
120/// Power control register (PWR_CR)
121pub mod CSR {
122
123    /// Wake-Up Flag
124    pub mod WUF {
125        /// Offset (0 bits)
126        pub const offset: u32 = 0;
127        /// Mask (1 bit: 1 << 0)
128        pub const mask: u32 = 1 << offset;
129        /// Read-only values (empty)
130        pub mod R {}
131        /// Write-only values (empty)
132        pub mod W {}
133        /// Read-write values (empty)
134        pub mod RW {}
135    }
136
137    /// STANDBY Flag
138    pub mod SBF {
139        /// Offset (1 bits)
140        pub const offset: u32 = 1;
141        /// Mask (1 bit: 1 << 1)
142        pub const mask: u32 = 1 << offset;
143        /// Read-only values (empty)
144        pub mod R {}
145        /// Write-only values (empty)
146        pub mod W {}
147        /// Read-write values (empty)
148        pub mod RW {}
149    }
150
151    /// PVD Output
152    pub mod PVDO {
153        /// Offset (2 bits)
154        pub const offset: u32 = 2;
155        /// Mask (1 bit: 1 << 2)
156        pub const mask: u32 = 1 << offset;
157        /// Read-only values (empty)
158        pub mod R {}
159        /// Write-only values (empty)
160        pub mod W {}
161        /// Read-write values (empty)
162        pub mod RW {}
163    }
164
165    /// Enable WKUP pin
166    pub mod EWUP {
167        /// Offset (8 bits)
168        pub const offset: u32 = 8;
169        /// Mask (1 bit: 1 << 8)
170        pub const mask: u32 = 1 << offset;
171        /// Read-only values (empty)
172        pub mod R {}
173        /// Write-only values (empty)
174        pub mod W {}
175        /// Read-write values (empty)
176        pub mod RW {}
177    }
178}
179#[repr(C)]
180pub struct RegisterBlock {
181    /// Power control register (PWR_CR)
182    pub CR: RWRegister<u32>,
183
184    /// Power control register (PWR_CR)
185    pub CSR: RWRegister<u32>,
186}
187pub struct ResetValues {
188    pub CR: u32,
189    pub CSR: u32,
190}
191#[cfg(not(feature = "nosync"))]
192pub struct Instance {
193    pub(crate) addr: u32,
194    pub(crate) _marker: PhantomData<*const RegisterBlock>,
195}
196#[cfg(not(feature = "nosync"))]
197impl ::core::ops::Deref for Instance {
198    type Target = RegisterBlock;
199    #[inline(always)]
200    fn deref(&self) -> &RegisterBlock {
201        unsafe { &*(self.addr as *const _) }
202    }
203}
204#[cfg(feature = "rtic")]
205unsafe impl Send for Instance {}
stm32ral/stm32f1/peripherals/pwr.rs

stm32ral/stm32f1/peripherals/
pwr.rs
