stm32ral/cortex_m/instances/
tpiu.rs

1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Trace Port Interface Unit
4//!
5//! Used by: armv7em, armv7m
6
7#[cfg(not(feature = "nosync"))]
8pub use crate::cortex_m::peripherals::tpiu::Instance;
9pub use crate::cortex_m::peripherals::tpiu::{RegisterBlock, ResetValues};
10pub use crate::cortex_m::peripherals::tpiu::{ACPR, CSPSR, LAR, LSR, SPPR, SSPSR, TYPE};
11
12/// Access functions for the TPIU peripheral instance
13pub mod TPIU {
14    use super::ResetValues;
15
16    #[cfg(not(feature = "nosync"))]
17    use super::Instance;
18
19    #[cfg(not(feature = "nosync"))]
20    const INSTANCE: Instance = Instance {
21        addr: 0xe0040000,
22        _marker: ::core::marker::PhantomData,
23    };
24
25    /// Reset values for each field in TPIU
26    pub const reset: ResetValues = ResetValues {
27        SSPSR: 0x00000000,
28        CSPSR: 0x00000000,
29        ACPR: 0x00000000,
30        SPPR: 0x00000000,
31        TYPE: 0x00000000,
32        LSR: 0x00000000,
33        LAR: 0x00000000,
34    };
35
36    #[cfg(not(feature = "nosync"))]
37    #[allow(renamed_and_removed_lints)]
38    #[allow(private_no_mangle_statics)]
39    #[no_mangle]
40    static mut TPIU_TAKEN: bool = false;
41
42    /// Safe access to TPIU
43    ///
44    /// This function returns `Some(Instance)` if this instance is not
45    /// currently taken, and `None` if it is. This ensures that if you
46    /// do get `Some(Instance)`, you are ensured unique access to
47    /// the peripheral and there cannot be data races (unless other
48    /// code uses `unsafe`, of course). You can then pass the
49    /// `Instance` around to other functions as required. When you're
50    /// done with it, you can call `release(instance)` to return it.
51    ///
52    /// `Instance` itself dereferences to a `RegisterBlock`, which
53    /// provides access to the peripheral's registers.
54    #[cfg(not(feature = "nosync"))]
55    #[inline]
56    pub fn take() -> Option<Instance> {
57        external_cortex_m::interrupt::free(|_| unsafe {
58            if TPIU_TAKEN {
59                None
60            } else {
61                TPIU_TAKEN = true;
62                Some(INSTANCE)
63            }
64        })
65    }
66
67    /// Release exclusive access to TPIU
68    ///
69    /// This function allows you to return an `Instance` so that it
70    /// is available to `take()` again. This function will panic if
71    /// you return a different `Instance` or if this instance is not
72    /// already taken.
73    #[cfg(not(feature = "nosync"))]
74    #[inline]
75    pub fn release(inst: Instance) {
76        external_cortex_m::interrupt::free(|_| unsafe {
77            if TPIU_TAKEN && inst.addr == INSTANCE.addr {
78                TPIU_TAKEN = false;
79            } else {
80                panic!("Released a peripheral which was not taken");
81            }
82        });
83    }
84
85    /// Unsafely steal TPIU
86    ///
87    /// This function is similar to take() but forcibly takes the
88    /// Instance, marking it as taken irregardless of its previous
89    /// state.
90    #[cfg(not(feature = "nosync"))]
91    #[inline]
92    pub unsafe fn steal() -> Instance {
93        TPIU_TAKEN = true;
94        INSTANCE
95    }
96}
97
98/// Raw pointer to TPIU
99///
100/// Dereferencing this is unsafe because you are not ensured unique
101/// access to the peripheral, so you may encounter data races with
102/// other users of this peripheral. It is up to you to ensure you
103/// will not cause data races.
104///
105/// This constant is provided for ease of use in unsafe code: you can
106/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
107pub const TPIU: *const RegisterBlock = 0xe0040000 as *const _;
stm32ral/cortex_m/instances/tpiu.rs

stm32ral/cortex_m/instances/
tpiu.rs
