stm32ral/stm32g4/stm32g484/
interrupts.rs

1#[cfg(feature = "rt")]
2extern "C" {
3    fn WWDG();
4    fn PVD_PVM();
5    fn RTC_TAMP_CSS_LSE();
6    fn RTC_WKUP();
7    fn FLASH();
8    fn RCC();
9    fn EXTI0();
10    fn EXTI1();
11    fn EXTI2();
12    fn EXTI3();
13    fn EXTI4();
14    fn DMA1_CH1();
15    fn DMA1_CH2();
16    fn DMA1_CH3();
17    fn DMA1_CH4();
18    fn DMA1_CH5();
19    fn DMA1_CH6();
20    fn DMA1_CH7();
21    fn ADC1_2();
22    fn USB_HP();
23    fn USB_LP();
24    fn fdcan1_intr1_it();
25    fn fdcan1_intr0_it();
26    fn EXTI9_5();
27    fn TIM1_BRK_TIM15();
28    fn TIM1_UP_TIM16();
29    fn TIM1_TRG_COM();
30    fn TIM1_CC();
31    fn TIM2();
32    fn TIM3();
33    fn TIM4();
34    fn I2C1_EV();
35    fn I2C1_ER();
36    fn I2C2_EV();
37    fn I2C2_ER();
38    fn SPI1();
39    fn SPI2();
40    fn USART1();
41    fn USART2();
42    fn USART3();
43    fn EXTI15_10();
44    fn RTC_ALARM();
45    fn USBWakeUP();
46    fn TIM8_BRK();
47    fn TIM8_UP();
48    fn TIM8_TRG_COM();
49    fn TIM8_CC();
50    fn ADC3();
51    fn FMC();
52    fn LPTIM1();
53    fn TIM5();
54    fn SPI3();
55    fn UART4();
56    fn UART5();
57    fn TIM6_DACUNDER();
58    fn TIM7();
59    fn DMA2_CH1();
60    fn DMA2_CH2();
61    fn DMA2_CH3();
62    fn DMA2_CH4();
63    fn DMA2_CH5();
64    fn ADC4();
65    fn ADC5();
66    fn UCPD1();
67    fn COMP1_2_3();
68    fn COMP4_5_6();
69    fn COMP7();
70    fn HRTIM_Master_IRQn();
71    fn HRTIM_TIMA_IRQn();
72    fn HRTIM_TIMB_IRQn();
73    fn HRTIM_TIMC_IRQn();
74    fn HRTIM_TIMD_IRQn();
75    fn HRTIM_TIME_IRQn();
76    fn HRTIM_TIM_FLT_IRQn();
77    fn HRTIM_TIMF_IRQn();
78    fn CRS();
79    fn SAI();
80    fn TIM20_BRK();
81    fn TIM20_UP();
82    fn TIM20_TRG_COM();
83    fn TIM20_CC();
84    fn FPU();
85    fn I2C4_EV();
86    fn I2C4_ER();
87    fn SPI4();
88    fn AES();
89    fn FDCAN2_intr0();
90    fn FDCAN2_intr1();
91    fn FDCAN3_intr0();
92    fn FDCAN3_intr1();
93    fn RNG();
94    fn LPUART();
95    fn I2C3_EV();
96    fn I2C3_ER();
97    fn DMAMUX_OVR();
98    fn QUADSPI();
99    fn DMA1_CH8();
100    fn DMA2_CH6();
101    fn DMA2_CH7();
102    fn DMA2_CH8();
103    fn Cordic();
104    fn FMAC();
105}
106
107#[doc(hidden)]
108pub union Vector {
109    _handler: unsafe extern "C" fn(),
110    _reserved: u32,
111}
112
113#[cfg(feature = "rt")]
114#[doc(hidden)]
115#[link_section = ".vector_table.interrupts"]
116#[no_mangle]
117pub static __INTERRUPTS: [Vector; 102] = [
118    Vector { _handler: WWDG },
119    Vector { _handler: PVD_PVM },
120    Vector {
121        _handler: RTC_TAMP_CSS_LSE,
122    },
123    Vector { _handler: RTC_WKUP },
124    Vector { _handler: FLASH },
125    Vector { _handler: RCC },
126    Vector { _handler: EXTI0 },
127    Vector { _handler: EXTI1 },
128    Vector { _handler: EXTI2 },
129    Vector { _handler: EXTI3 },
130    Vector { _handler: EXTI4 },
131    Vector { _handler: DMA1_CH1 },
132    Vector { _handler: DMA1_CH2 },
133    Vector { _handler: DMA1_CH3 },
134    Vector { _handler: DMA1_CH4 },
135    Vector { _handler: DMA1_CH5 },
136    Vector { _handler: DMA1_CH6 },
137    Vector { _handler: DMA1_CH7 },
138    Vector { _handler: ADC1_2 },
139    Vector { _handler: USB_HP },
140    Vector { _handler: USB_LP },
141    Vector {
142        _handler: fdcan1_intr1_it,
143    },
144    Vector {
145        _handler: fdcan1_intr0_it,
146    },
147    Vector { _handler: EXTI9_5 },
148    Vector {
149        _handler: TIM1_BRK_TIM15,
150    },
151    Vector {
152        _handler: TIM1_UP_TIM16,
153    },
154    Vector {
155        _handler: TIM1_TRG_COM,
156    },
157    Vector { _handler: TIM1_CC },
158    Vector { _handler: TIM2 },
159    Vector { _handler: TIM3 },
160    Vector { _handler: TIM4 },
161    Vector { _handler: I2C1_EV },
162    Vector { _handler: I2C1_ER },
163    Vector { _handler: I2C2_EV },
164    Vector { _handler: I2C2_ER },
165    Vector { _handler: SPI1 },
166    Vector { _handler: SPI2 },
167    Vector { _handler: USART1 },
168    Vector { _handler: USART2 },
169    Vector { _handler: USART3 },
170    Vector {
171        _handler: EXTI15_10,
172    },
173    Vector {
174        _handler: RTC_ALARM,
175    },
176    Vector {
177        _handler: USBWakeUP,
178    },
179    Vector { _handler: TIM8_BRK },
180    Vector { _handler: TIM8_UP },
181    Vector {
182        _handler: TIM8_TRG_COM,
183    },
184    Vector { _handler: TIM8_CC },
185    Vector { _handler: ADC3 },
186    Vector { _handler: FMC },
187    Vector { _handler: LPTIM1 },
188    Vector { _handler: TIM5 },
189    Vector { _handler: SPI3 },
190    Vector { _handler: UART4 },
191    Vector { _handler: UART5 },
192    Vector {
193        _handler: TIM6_DACUNDER,
194    },
195    Vector { _handler: TIM7 },
196    Vector { _handler: DMA2_CH1 },
197    Vector { _handler: DMA2_CH2 },
198    Vector { _handler: DMA2_CH3 },
199    Vector { _handler: DMA2_CH4 },
200    Vector { _handler: DMA2_CH5 },
201    Vector { _handler: ADC4 },
202    Vector { _handler: ADC5 },
203    Vector { _handler: UCPD1 },
204    Vector {
205        _handler: COMP1_2_3,
206    },
207    Vector {
208        _handler: COMP4_5_6,
209    },
210    Vector { _handler: COMP7 },
211    Vector {
212        _handler: HRTIM_Master_IRQn,
213    },
214    Vector {
215        _handler: HRTIM_TIMA_IRQn,
216    },
217    Vector {
218        _handler: HRTIM_TIMB_IRQn,
219    },
220    Vector {
221        _handler: HRTIM_TIMC_IRQn,
222    },
223    Vector {
224        _handler: HRTIM_TIMD_IRQn,
225    },
226    Vector {
227        _handler: HRTIM_TIME_IRQn,
228    },
229    Vector {
230        _handler: HRTIM_TIM_FLT_IRQn,
231    },
232    Vector {
233        _handler: HRTIM_TIMF_IRQn,
234    },
235    Vector { _handler: CRS },
236    Vector { _handler: SAI },
237    Vector {
238        _handler: TIM20_BRK,
239    },
240    Vector { _handler: TIM20_UP },
241    Vector {
242        _handler: TIM20_TRG_COM,
243    },
244    Vector { _handler: TIM20_CC },
245    Vector { _handler: FPU },
246    Vector { _handler: I2C4_EV },
247    Vector { _handler: I2C4_ER },
248    Vector { _handler: SPI4 },
249    Vector { _handler: AES },
250    Vector {
251        _handler: FDCAN2_intr0,
252    },
253    Vector {
254        _handler: FDCAN2_intr1,
255    },
256    Vector {
257        _handler: FDCAN3_intr0,
258    },
259    Vector {
260        _handler: FDCAN3_intr1,
261    },
262    Vector { _handler: RNG },
263    Vector { _handler: LPUART },
264    Vector { _handler: I2C3_EV },
265    Vector { _handler: I2C3_ER },
266    Vector {
267        _handler: DMAMUX_OVR,
268    },
269    Vector { _handler: QUADSPI },
270    Vector { _handler: DMA1_CH8 },
271    Vector { _handler: DMA2_CH6 },
272    Vector { _handler: DMA2_CH7 },
273    Vector { _handler: DMA2_CH8 },
274    Vector { _handler: Cordic },
275    Vector { _handler: FMAC },
276];
277
278/// Available interrupts for this device
279#[repr(u16)]
280#[derive(Copy, Clone, Debug, PartialEq, Eq)]
281#[allow(non_camel_case_types)]
282pub enum Interrupt {
283    /// 0: Window Watchdog interrupt
284    WWDG = 0,
285    /// 1: PVD through EXTI line detection
286    PVD_PVM = 1,
287    /// 2: RTC_TAMP_CSS_LSE
288    RTC_TAMP_CSS_LSE = 2,
289    /// 3: RTC Wakeup timer
290    RTC_WKUP = 3,
291    /// 4: FLASH
292    FLASH = 4,
293    /// 5: RCC
294    RCC = 5,
295    /// 6: EXTI Line0 interrupt
296    EXTI0 = 6,
297    /// 7: EXTI Line1 interrupt
298    EXTI1 = 7,
299    /// 8: EXTI Line2 interrupt
300    EXTI2 = 8,
301    /// 9: EXTI Line3 interrupt
302    EXTI3 = 9,
303    /// 10: EXTI Line4 interrupt
304    EXTI4 = 10,
305    /// 11: DMA1 channel 1 interrupt
306    DMA1_CH1 = 11,
307    /// 12: DMA1 channel 2 interrupt
308    DMA1_CH2 = 12,
309    /// 13: DMA1 channel 3 interrupt
310    DMA1_CH3 = 13,
311    /// 14: DMA1 channel 4 interrupt
312    DMA1_CH4 = 14,
313    /// 15: DMA1 channel 5 interrupt
314    DMA1_CH5 = 15,
315    /// 16: DMA1 channel 6 interrupt
316    DMA1_CH6 = 16,
317    /// 17: DMA1 channel 7 interrupt
318    DMA1_CH7 = 17,
319    /// 18: ADC1 and ADC2 global interrupt
320    ADC1_2 = 18,
321    /// 19: USB_HP
322    USB_HP = 19,
323    /// 20: USB_LP
324    USB_LP = 20,
325    /// 21: fdcan1_intr1_it
326    fdcan1_intr1_it = 21,
327    /// 22: fdcan1_intr0_it
328    fdcan1_intr0_it = 22,
329    /// 23: EXTI9_5
330    EXTI9_5 = 23,
331    /// 24: TIM1_BRK_TIM15
332    TIM1_BRK_TIM15 = 24,
333    /// 25: TIM1_UP_TIM16
334    TIM1_UP_TIM16 = 25,
335    /// 26: TIM1_TRG_COM/
336    TIM1_TRG_COM = 26,
337    /// 27: TIM1 capture compare interrupt
338    TIM1_CC = 27,
339    /// 28: TIM2
340    TIM2 = 28,
341    /// 29: TIM3
342    TIM3 = 29,
343    /// 30: TIM4
344    TIM4 = 30,
345    /// 31: I2C1_EV
346    I2C1_EV = 31,
347    /// 32: I2C1_ER
348    I2C1_ER = 32,
349    /// 33: I2C2_EV
350    I2C2_EV = 33,
351    /// 34: I2C2_ER
352    I2C2_ER = 34,
353    /// 35: SPI1
354    SPI1 = 35,
355    /// 36: SPI2
356    SPI2 = 36,
357    /// 37: USART1
358    USART1 = 37,
359    /// 38: USART2
360    USART2 = 38,
361    /// 39: USART3
362    USART3 = 39,
363    /// 40: EXTI15_10
364    EXTI15_10 = 40,
365    /// 41: RTC_ALARM
366    RTC_ALARM = 41,
367    /// 42: USBWakeUP
368    USBWakeUP = 42,
369    /// 43: TIM8_BRK
370    TIM8_BRK = 43,
371    /// 44: TIM8_UP
372    TIM8_UP = 44,
373    /// 45: TIM8_TRG_COM
374    TIM8_TRG_COM = 45,
375    /// 46: TIM8_CC
376    TIM8_CC = 46,
377    /// 47: ADC3
378    ADC3 = 47,
379    /// 48: FMC
380    FMC = 48,
381    /// 49: LPTIM1
382    LPTIM1 = 49,
383    /// 50: TIM5
384    TIM5 = 50,
385    /// 51: SPI3
386    SPI3 = 51,
387    /// 52: UART4
388    UART4 = 52,
389    /// 53: UART5
390    UART5 = 53,
391    /// 54: TIM6_DACUNDER
392    TIM6_DACUNDER = 54,
393    /// 55: TIM7
394    TIM7 = 55,
395    /// 56: DMA2_CH1
396    DMA2_CH1 = 56,
397    /// 57: DMA2_CH2
398    DMA2_CH2 = 57,
399    /// 58: DMA2_CH3
400    DMA2_CH3 = 58,
401    /// 59: DMA2_CH4
402    DMA2_CH4 = 59,
403    /// 60: DMA2_CH5
404    DMA2_CH5 = 60,
405    /// 61: ADC4
406    ADC4 = 61,
407    /// 62: ADC5
408    ADC5 = 62,
409    /// 63: UCPD1
410    UCPD1 = 63,
411    /// 64: COMP1_2_3
412    COMP1_2_3 = 64,
413    /// 65: COMP4_5_6
414    COMP4_5_6 = 65,
415    /// 66: COMP7
416    COMP7 = 66,
417    /// 67: HRTIM_Master_IRQn
418    HRTIM_Master_IRQn = 67,
419    /// 68: HRTIM_TIMA_IRQn
420    HRTIM_TIMA_IRQn = 68,
421    /// 69: HRTIM_TIMB_IRQn
422    HRTIM_TIMB_IRQn = 69,
423    /// 70: HRTIM_TIMC_IRQn
424    HRTIM_TIMC_IRQn = 70,
425    /// 71: HRTIM_TIMD_IRQn
426    HRTIM_TIMD_IRQn = 71,
427    /// 72: HRTIM_TIME_IRQn
428    HRTIM_TIME_IRQn = 72,
429    /// 73: HRTIM_TIM_FLT_IRQn
430    HRTIM_TIM_FLT_IRQn = 73,
431    /// 74: HRTIM_TIMF_IRQn
432    HRTIM_TIMF_IRQn = 74,
433    /// 75: CRS
434    CRS = 75,
435    /// 76: SAI
436    SAI = 76,
437    /// 77: TIM20_BRK
438    TIM20_BRK = 77,
439    /// 78: TIM20_UP
440    TIM20_UP = 78,
441    /// 79: TIM20_TRG_COM
442    TIM20_TRG_COM = 79,
443    /// 80: TIM20_CC
444    TIM20_CC = 80,
445    /// 81: Floating point unit interrupt
446    FPU = 81,
447    /// 82: I2C4_EV
448    I2C4_EV = 82,
449    /// 83: I2C4_ER
450    I2C4_ER = 83,
451    /// 84: SPI4
452    SPI4 = 84,
453    /// 85: AES
454    AES = 85,
455    /// 86: FDCAN2_intr0
456    FDCAN2_intr0 = 86,
457    /// 87: FDCAN2_intr1
458    FDCAN2_intr1 = 87,
459    /// 88: FDCAN3_intr0
460    FDCAN3_intr0 = 88,
461    /// 89: FDCAN3_intr1
462    FDCAN3_intr1 = 89,
463    /// 90: RNG
464    RNG = 90,
465    /// 91: LPUART
466    LPUART = 91,
467    /// 92: I2C3_EV
468    I2C3_EV = 92,
469    /// 93: I2C3_ER
470    I2C3_ER = 93,
471    /// 94: DMAMUX_OVR
472    DMAMUX_OVR = 94,
473    /// 95: QUADSPI
474    QUADSPI = 95,
475    /// 96: DMA1_CH8
476    DMA1_CH8 = 96,
477    /// 97: DMA2_CH6
478    DMA2_CH6 = 97,
479    /// 98: DMA2_CH7
480    DMA2_CH7 = 98,
481    /// 99: DMA2_CH8
482    DMA2_CH8 = 99,
483    /// 100: Cordic
484    Cordic = 100,
485    /// 101: FMAC
486    FMAC = 101,
487}
488unsafe impl external_cortex_m::interrupt::InterruptNumber for Interrupt {
489    #[inline(always)]
490    fn number(self) -> u16 {
491        self as u16
492    }
493}
stm32ral/stm32g4/stm32g484/interrupts.rs

stm32ral/stm32g4/stm32g484/
interrupts.rs
