Struct stm32ral::stm32wl::stm32wle5::rcc::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 32 fields
pub CR: RWRegister<u32>,
pub ICSCR: RWRegister<u32>,
pub CFGR: RWRegister<u32>,
pub PLLCFGR: RWRegister<u32>,
pub CIER: RWRegister<u32>,
pub CIFR: RORegister<u32>,
pub CICR: WORegister<u32>,
pub AHB1RSTR: RWRegister<u32>,
pub AHB2RSTR: RWRegister<u32>,
pub AHB3RSTR: RWRegister<u32>,
pub APB1RSTR1: RWRegister<u32>,
pub APB1RSTR2: RWRegister<u32>,
pub APB2RSTR: RWRegister<u32>,
pub APB3RSTR: RWRegister<u32>,
pub AHB1ENR: RWRegister<u32>,
pub AHB2ENR: RWRegister<u32>,
pub AHB3ENR: RWRegister<u32>,
pub APB1ENR1: RWRegister<u32>,
pub APB1ENR2: RWRegister<u32>,
pub APB2ENR: RWRegister<u32>,
pub APB3ENR: RWRegister<u32>,
pub AHB1SMENR: RWRegister<u32>,
pub AHB2SMENR: RWRegister<u32>,
pub AHB3SMENR: RWRegister<u32>,
pub APB1SMENR1: RWRegister<u32>,
pub APB1SMENR2: RWRegister<u32>,
pub APB2SMENR: RWRegister<u32>,
pub APB3SMENR: RWRegister<u32>,
pub CCIPR: RWRegister<u32>,
pub BDCR: RWRegister<u32>,
pub CSR: RWRegister<u32>,
pub EXTCFGR: RWRegister<u32>,
// some fields omitted
}
Fields
CR: RWRegister<u32>
Clock control register
ICSCR: RWRegister<u32>
Internal clock sources calibration register
CFGR: RWRegister<u32>
Clock configuration register
PLLCFGR: RWRegister<u32>
PLL configuration register
CIER: RWRegister<u32>
Clock interrupt enable register
CIFR: RORegister<u32>
Clock interrupt flag register
CICR: WORegister<u32>
Clock interrupt clear register
AHB1RSTR: RWRegister<u32>
AHB1 peripheral reset register
AHB2RSTR: RWRegister<u32>
AHB2 peripheral reset register
AHB3RSTR: RWRegister<u32>
AHB3 peripheral reset register
APB1RSTR1: RWRegister<u32>
APB1 peripheral reset register 1
APB1RSTR2: RWRegister<u32>
APB1 peripheral reset register 2
APB2RSTR: RWRegister<u32>
APB2 peripheral reset register
APB3RSTR: RWRegister<u32>
APB3 peripheral reset register
AHB1ENR: RWRegister<u32>
AHB1 peripheral clock enable register
AHB2ENR: RWRegister<u32>
AHB2 peripheral clock enable register
AHB3ENR: RWRegister<u32>
AHB3 peripheral clock enable register
APB1ENR1: RWRegister<u32>
APB1 peripheral clock enable register 1
APB1ENR2: RWRegister<u32>
APB1 peripheral clock enable register 2
APB2ENR: RWRegister<u32>
APB2 peripheral clock enable register
APB3ENR: RWRegister<u32>
APB3 peripheral clock enable register
AHB1SMENR: RWRegister<u32>
AHB1 peripheral clocks enable in Sleep modes register
AHB2SMENR: RWRegister<u32>
AHB2 peripheral clocks enable in Sleep modes register
AHB3SMENR: RWRegister<u32>
AHB3 peripheral clocks enable in Sleep and Stop modes register
APB1SMENR1: RWRegister<u32>
APB1 peripheral clocks enable in Sleep mode register 1
APB1SMENR2: RWRegister<u32>
APB1 peripheral clocks enable in Sleep mode register 2
APB2SMENR: RWRegister<u32>
APB2 peripheral clocks enable in Sleep mode register
APB3SMENR: RWRegister<u32>
APB3 peripheral clock enable in Sleep mode register
CCIPR: RWRegister<u32>
Peripherals independent clock configuration register
BDCR: RWRegister<u32>
Backup domain control register
CSR: RWRegister<u32>
Control/status register
EXTCFGR: RWRegister<u32>
Extended clock recovery register