Struct stm32ral::stm32wl::stm32wl5x_cm0p::ipcc::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {
pub C1CR: RWRegister<u32>,
pub C1MR: RWRegister<u32>,
pub C1SCR: RWRegister<u32>,
pub C1TOC2SR: RORegister<u32>,
pub C2CR: RWRegister<u32>,
pub C2MR: RWRegister<u32>,
pub C2SCR: RWRegister<u32>,
pub C2TOC1SR: RORegister<u32>,
pub HWCFGR: RORegister<u32>,
pub VERR: RORegister<u32>,
pub IPIDR: RORegister<u32>,
pub SIDR: RORegister<u32>,
// some fields omitted
}
Fields
C1CR: RWRegister<u32>
IPCC Processor 1 control register
C1MR: RWRegister<u32>
IPCC Processor 1 mask register
C1SCR: RWRegister<u32>
Reading this register will always return 0x0000 0000.
C1TOC2SR: RORegister<u32>
IPCC processor 1 to processor 2 status register
C2CR: RWRegister<u32>
IPCC Processor 2 control register
C2MR: RWRegister<u32>
IPCC Processor 2 mask register
C2SCR: RWRegister<u32>
Reading this register will always return 0x0000 0000.
C2TOC1SR: RORegister<u32>
IPCC processor 2 to processor 1 status register
HWCFGR: RORegister<u32>
IPCC Hardware configuration register
VERR: RORegister<u32>
IPCC IP Version register
IPIDR: RORegister<u32>
IPCC IP Identification register
SIDR: RORegister<u32>
IPCC Size ID register