Struct stm32ral::stm32mp::peripherals::tim7::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub TIM7_CR1: RWRegister<u16>,
    pub TIM7_CR2: RWRegister<u32>,
    pub TIM7_SMCR: RWRegister<u32>,
    pub TIM7_DIER: RWRegister<u16>,
    pub TIM7_SR: RWRegister<u32>,
    pub TIM7_EGR: WORegister<u16>,
    pub TIM7_CCMR1ALTERNATE7: RWRegister<u32>,
    pub TIM7_CCMR2ALTERNATE23: RWRegister<u32>,
    pub TIM7_CCER: RWRegister<u32>,
    pub TIM7_CNT: RWRegister<u32>,
    pub TIM7_PSC: RWRegister<u16>,
    pub TIM7_ARR: RWRegister<u16>,
    pub TIM7_RCR: RWRegister<u16>,
    pub TIM7_CCR1: RWRegister<u16>,
    pub TIM7_CCR2: RWRegister<u16>,
    pub TIM7_CCR3: RWRegister<u16>,
    pub TIM7_CCR4: RWRegister<u16>,
    pub TIM7_BDTR: RWRegister<u32>,
    pub TIM7_DCR: RWRegister<u16>,
    pub TIM7_DMAR: RWRegister<u32>,
    pub TIM7_CCMR3: RWRegister<u32>,
    pub TIM7_CCR5: RWRegister<u32>,
    pub TIM7_CCR6: RWRegister<u16>,
    // some fields omitted
}

Fields

TIM7_CR1: RWRegister<u16>

TIM7 control register 1

TIM7_CR2: RWRegister<u32>

TIM7 control register 2

TIM7_SMCR: RWRegister<u32>

TIM7 slave mode control register

TIM7_DIER: RWRegister<u16>

TIM7 DMA/interrupt enable register

TIM7_SR: RWRegister<u32>

TIM7 status register

TIM7_EGR: WORegister<u16>

TIM7 event generation register

TIM7_CCMR1ALTERNATE7: RWRegister<u32>

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

TIM7_CCMR2ALTERNATE23: RWRegister<u32>

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

TIM7_CCER: RWRegister<u32>

TIM7 capture/compare enable register

TIM7_CNT: RWRegister<u32>

TIM7 counter

TIM7_PSC: RWRegister<u16>

TIM7 prescaler

TIM7_ARR: RWRegister<u16>

TIM7 auto-reload register

TIM7_RCR: RWRegister<u16>

TIM7 repetition counter register

TIM7_CCR1: RWRegister<u16>

TIM7 capture/compare register 1

TIM7_CCR2: RWRegister<u16>

TIM7 capture/compare register 2

TIM7_CCR3: RWRegister<u16>

TIM7 capture/compare register 3

TIM7_CCR4: RWRegister<u16>

TIM7 capture/compare register 4

TIM7_BDTR: RWRegister<u32>

As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

TIM7_DCR: RWRegister<u16>

TIM7 DMA control register

TIM7_DMAR: RWRegister<u32>

TIM7 DMA address for full transfer

TIM7_CCMR3: RWRegister<u32>

The channels 5 and 6 can only be configured in output. Output compare mode:

TIM7_CCR5: RWRegister<u32>

TIM7 capture/compare register 5

TIM7_CCR6: RWRegister<u16>

TIM7 capture/compare register 6