Struct stm32ral::stm32mp::peripherals::tim5::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub TIM5_CR1: RWRegister<u16>,
    pub TIM5_CR2: RWRegister<u32>,
    pub TIM5_SMCR: RWRegister<u32>,
    pub TIM5_DIER: RWRegister<u16>,
    pub TIM5_SR: RWRegister<u32>,
    pub TIM5_EGR: WORegister<u16>,
    pub TIM5_CCMR1ALTERNATE5: RWRegister<u32>,
    pub TIM5_CCMR2ALTERNATE21: RWRegister<u32>,
    pub TIM5_CCER: RWRegister<u32>,
    pub TIM5_CNT: RWRegister<u32>,
    pub TIM5_PSC: RWRegister<u16>,
    pub TIM5_ARR: RWRegister<u16>,
    pub TIM5_RCR: RWRegister<u16>,
    pub TIM5_CCR1: RWRegister<u16>,
    pub TIM5_CCR2: RWRegister<u16>,
    pub TIM5_CCR3: RWRegister<u16>,
    pub TIM5_CCR4: RWRegister<u16>,
    pub TIM5_BDTR: RWRegister<u32>,
    pub TIM5_DCR: RWRegister<u16>,
    pub TIM5_DMAR: RWRegister<u32>,
    pub TIM5_CCMR3: RWRegister<u32>,
    pub TIM5_CCR5: RWRegister<u32>,
    pub TIM5_CCR6: RWRegister<u16>,
    // some fields omitted
}

Fields

TIM5_CR1: RWRegister<u16>

TIM5 control register 1

TIM5_CR2: RWRegister<u32>

TIM5 control register 2

TIM5_SMCR: RWRegister<u32>

TIM5 slave mode control register

TIM5_DIER: RWRegister<u16>

TIM5 DMA/interrupt enable register

TIM5_SR: RWRegister<u32>

TIM5 status register

TIM5_EGR: WORegister<u16>

TIM5 event generation register

TIM5_CCMR1ALTERNATE5: RWRegister<u32>

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

TIM5_CCMR2ALTERNATE21: RWRegister<u32>

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

TIM5_CCER: RWRegister<u32>

TIM5 capture/compare enable register

TIM5_CNT: RWRegister<u32>

TIM5 counter

TIM5_PSC: RWRegister<u16>

TIM5 prescaler

TIM5_ARR: RWRegister<u16>

TIM5 auto-reload register

TIM5_RCR: RWRegister<u16>

TIM5 repetition counter register

TIM5_CCR1: RWRegister<u16>

TIM5 capture/compare register 1

TIM5_CCR2: RWRegister<u16>

TIM5 capture/compare register 2

TIM5_CCR3: RWRegister<u16>

TIM5 capture/compare register 3

TIM5_CCR4: RWRegister<u16>

TIM5 capture/compare register 4

TIM5_BDTR: RWRegister<u32>

As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

TIM5_DCR: RWRegister<u16>

TIM5 DMA control register

TIM5_DMAR: RWRegister<u32>

TIM5 DMA address for full transfer

TIM5_CCMR3: RWRegister<u32>

The channels 5 and 6 can only be configured in output. Output compare mode:

TIM5_CCR5: RWRegister<u32>

TIM5 capture/compare register 5

TIM5_CCR6: RWRegister<u16>

TIM5 capture/compare register 6