Struct stm32ral::stm32mp::peripherals::tim4::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub TIM4_CR1: RWRegister<u16>,
    pub TIM4_CR2: RWRegister<u32>,
    pub TIM4_SMCR: RWRegister<u32>,
    pub TIM4_DIER: RWRegister<u16>,
    pub TIM4_SR: RWRegister<u32>,
    pub TIM4_EGR: WORegister<u16>,
    pub TIM4_CCMR1ALTERNATE4: RWRegister<u32>,
    pub TIM4_CCMR2ALTERNATE20: RWRegister<u32>,
    pub TIM4_CCER: RWRegister<u32>,
    pub TIM4_CNT: RWRegister<u32>,
    pub TIM4_PSC: RWRegister<u16>,
    pub TIM4_ARR: RWRegister<u16>,
    pub TIM4_RCR: RWRegister<u16>,
    pub TIM4_CCR1: RWRegister<u16>,
    pub TIM4_CCR2: RWRegister<u16>,
    pub TIM4_CCR3: RWRegister<u16>,
    pub TIM4_CCR4: RWRegister<u16>,
    pub TIM4_BDTR: RWRegister<u32>,
    pub TIM4_DCR: RWRegister<u16>,
    pub TIM4_DMAR: RWRegister<u32>,
    pub TIM4_CCMR3: RWRegister<u32>,
    pub TIM4_CCR5: RWRegister<u32>,
    pub TIM4_CCR6: RWRegister<u16>,
    // some fields omitted
}

Fields

TIM4_CR1: RWRegister<u16>

TIM4 control register 1

TIM4_CR2: RWRegister<u32>

TIM4 control register 2

TIM4_SMCR: RWRegister<u32>

TIM4 slave mode control register

TIM4_DIER: RWRegister<u16>

TIM4 DMA/interrupt enable register

TIM4_SR: RWRegister<u32>

TIM4 status register

TIM4_EGR: WORegister<u16>

TIM4 event generation register

TIM4_CCMR1ALTERNATE4: RWRegister<u32>

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

TIM4_CCMR2ALTERNATE20: RWRegister<u32>

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

TIM4_CCER: RWRegister<u32>

TIM4 capture/compare enable register

TIM4_CNT: RWRegister<u32>

TIM4 counter

TIM4_PSC: RWRegister<u16>

TIM4 prescaler

TIM4_ARR: RWRegister<u16>

TIM4 auto-reload register

TIM4_RCR: RWRegister<u16>

TIM4 repetition counter register

TIM4_CCR1: RWRegister<u16>

TIM4 capture/compare register 1

TIM4_CCR2: RWRegister<u16>

TIM4 capture/compare register 2

TIM4_CCR3: RWRegister<u16>

TIM4 capture/compare register 3

TIM4_CCR4: RWRegister<u16>

TIM4 capture/compare register 4

TIM4_BDTR: RWRegister<u32>

As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

TIM4_DCR: RWRegister<u16>

TIM4 DMA control register

TIM4_DMAR: RWRegister<u32>

TIM4 DMA address for full transfer

TIM4_CCMR3: RWRegister<u32>

The channels 5 and 6 can only be configured in output. Output compare mode:

TIM4_CCR5: RWRegister<u32>

TIM4 capture/compare register 5

TIM4_CCR6: RWRegister<u16>

TIM4 capture/compare register 6