Struct stm32ral::stm32mp::peripherals::tim15::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub TIM15_CR1: RWRegister<u16>,
    pub TIM15_CR2: RWRegister<u16>,
    pub TIMx_SMCR: RWRegister<u32>,
    pub TIM15_DIER: RWRegister<u16>,
    pub TIM15_SR: RWRegister<u16>,
    pub TIMx_EGR: WORegister<u32>,
    pub TIMx_CCMR1: RWRegister<u32>,
    pub TIM15_CCER: RWRegister<u16>,
    pub TIM15_CNT: RWRegister<u32>,
    pub TIM15_PSC: RWRegister<u16>,
    pub TIM15_ARR: RWRegister<u16>,
    pub TIM15_RCR: RWRegister<u16>,
    pub TIM15_CCR1: RWRegister<u16>,
    pub TIM15_CCR2: RWRegister<u16>,
    pub TIMx_BDTR: RWRegister<u32>,
    pub TIM15_DCR: RWRegister<u16>,
    pub TIM15_DMAR: RWRegister<u16>,
    pub TIM15_AF1: RWRegister<u32>,
    pub TIM15_TISEL: RWRegister<u32>,
    // some fields omitted
}

Fields

TIM15_CR1: RWRegister<u16>

TIM15 control register 1

TIM15_CR2: RWRegister<u16>

TIM15 control register 2

TIMx_SMCR: RWRegister<u32>

slave mode control register

TIM15_DIER: RWRegister<u16>

TIM15 DMA/interrupt enable register

TIM15_SR: RWRegister<u16>

TIM15 status register

TIMx_EGR: WORegister<u32>

event generation register

TIMx_CCMR1: RWRegister<u32>

TIMx_CCMR1_Output and TIMx_CCMR1_Input TIMx_CCMR1_Output: capture/compare mode register 1 (output mode) TIMx_CCMR1_Input: capture/compare mode register 1 (input mode)

TIM15_CCER: RWRegister<u16>

TIM15 capture/compare enable register

TIM15_CNT: RWRegister<u32>

TIM15 counter

TIM15_PSC: RWRegister<u16>

TIM15 prescaler

TIM15_ARR: RWRegister<u16>

TIM15 auto-reload register

TIM15_RCR: RWRegister<u16>

TIM15 repetition counter register

TIM15_CCR1: RWRegister<u16>

TIM15 capture/compare register 1

TIM15_CCR2: RWRegister<u16>

TIM15 capture/compare register 2

TIMx_BDTR: RWRegister<u32>

As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

TIM15_DCR: RWRegister<u16>

TIM15 DMA control register

TIM15_DMAR: RWRegister<u16>

TIM15 DMA address for full transfer

TIM15_AF1: RWRegister<u32>

TIM15 alternate register 1

TIM15_TISEL: RWRegister<u32>

TIM15 input selection register