Struct stm32ral::stm32mp::peripherals::tim1::RegisterBlock[−][src]

#[repr(C)]
pub struct RegisterBlock {Show 26 fields
    pub TIM1_CR1: RWRegister<u16>,
    pub TIM1_CR2: RWRegister<u32>,
    pub TIM1_SMCR: RWRegister<u32>,
    pub TIM1_DIER: RWRegister<u16>,
    pub TIM1_SR: RWRegister<u32>,
    pub TIM1_EGR: WORegister<u16>,
    pub TIM1_CCMR1ALTERNATE1: RWRegister<u32>,
    pub TIM1_CCMR2ALTERNATE17: RWRegister<u32>,
    pub TIM1_CCER: RWRegister<u32>,
    pub TIM1_CNT: RWRegister<u32>,
    pub TIM1_PSC: RWRegister<u16>,
    pub TIM1_ARR: RWRegister<u16>,
    pub TIM1_RCR: RWRegister<u16>,
    pub TIM1_CCR1: RWRegister<u16>,
    pub TIM1_CCR2: RWRegister<u16>,
    pub TIM1_CCR3: RWRegister<u16>,
    pub TIM1_CCR4: RWRegister<u16>,
    pub TIM1_BDTR: RWRegister<u32>,
    pub TIM1_DCR: RWRegister<u16>,
    pub TIM1_DMAR: RWRegister<u32>,
    pub TIM1_CCMR3: RWRegister<u32>,
    pub TIM1_CCR5: RWRegister<u32>,
    pub TIM1_CCR6: RWRegister<u16>,
    pub TIM1_AF1: RWRegister<u32>,
    pub TIM1_AF2: RWRegister<u32>,
    pub TIM1_TISEL: RWRegister<u32>,
    // some fields omitted
}

Fields

TIM1_CR1: RWRegister<u16>

TIM1 control register 1

TIM1_CR2: RWRegister<u32>

TIM1 control register 2

TIM1_SMCR: RWRegister<u32>

TIM1 slave mode control register

TIM1_DIER: RWRegister<u16>

TIM1 DMA/interrupt enable register

TIM1_SR: RWRegister<u32>

TIM1 status register

TIM1_EGR: WORegister<u16>

TIM1 event generation register

TIM1_CCMR1ALTERNATE1: RWRegister<u32>

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

TIM1_CCMR2ALTERNATE17: RWRegister<u32>

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

TIM1_CCER: RWRegister<u32>

TIM1 capture/compare enable register

TIM1_CNT: RWRegister<u32>

TIM1 counter

TIM1_PSC: RWRegister<u16>

TIM1 prescaler

TIM1_ARR: RWRegister<u16>

TIM1 auto-reload register

TIM1_RCR: RWRegister<u16>

TIM1 repetition counter register

TIM1_CCR1: RWRegister<u16>

TIM1 capture/compare register 1

TIM1_CCR2: RWRegister<u16>

TIM1 capture/compare register 2

TIM1_CCR3: RWRegister<u16>

TIM1 capture/compare register 3

TIM1_CCR4: RWRegister<u16>

TIM1 capture/compare register 4

TIM1_BDTR: RWRegister<u32>

As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

TIM1_DCR: RWRegister<u16>

TIM1 DMA control register

TIM1_DMAR: RWRegister<u32>

TIM1 DMA address for full transfer

TIM1_CCMR3: RWRegister<u32>

The channels 5 and 6 can only be configured in output. Output compare mode:

TIM1_CCR5: RWRegister<u32>

TIM1 capture/compare register 5

TIM1_CCR6: RWRegister<u16>

TIM1 capture/compare register 6

TIM1_AF1: RWRegister<u32>

TIM1 alternate function option register 1