Struct stm32ral::stm32mp::peripherals::spi::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 18 fields
pub SPI2S_CR1: RWRegister<u32>,
pub SPI_CR2: RWRegister<u32>,
pub SPI_CFG1: RWRegister<u32>,
pub SPI_CFG2: RWRegister<u32>,
pub SPI2S_IER: RWRegister<u32>,
pub SPI2S_SR: RORegister<u32>,
pub SPI2S_IFCR: WORegister<u32>,
pub SPI2S_TXDR: WORegister<u32>,
pub SPI2S_RXDR: RORegister<u32>,
pub SPI_CRCPOLY: RWRegister<u32>,
pub SPI_TXCRC: RORegister<u32>,
pub SPI_RXCRC: RORegister<u32>,
pub SPI_UDRDR: RWRegister<u32>,
pub SPI_I2SCFGR: RWRegister<u32>,
pub SPI_I2S_HWCFGR: RORegister<u32>,
pub SPI_VERR: RORegister<u32>,
pub SPI_IPIDR: RORegister<u32>,
pub SPI_SIDR: RORegister<u32>,
// some fields omitted
}
Fields
SPI2S_CR1: RWRegister<u32>
SPI/I2S control register 1
SPI_CR2: RWRegister<u32>
SPI control register 2
SPI_CFG1: RWRegister<u32>
Content of this register is write protected when SPI is enabled
SPI_CFG2: RWRegister<u32>
The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register.
SPI2S_IER: RWRegister<u32>
SPI/I2S interrupt enable register
SPI2S_SR: RORegister<u32>
SPI/I2S status register
SPI2S_IFCR: WORegister<u32>
SPI/I2S interrupt/status flags clear register
SPI2S_TXDR: WORegister<u32>
SPI/I2S transmit data register
SPI2S_RXDR: RORegister<u32>
SPI/I2S receive data register
SPI_CRCPOLY: RWRegister<u32>
SPI polynomial register
SPI_TXCRC: RORegister<u32>
SPI transmitter CRC register
SPI_RXCRC: RORegister<u32>
SPI receiver CRC register
SPI_UDRDR: RWRegister<u32>
SPI underrun data register
SPI_I2SCFGR: RWRegister<u32>
All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode.
SPI_I2S_HWCFGR: RORegister<u32>
SPI/I2S hardware configuration register
SPI_VERR: RORegister<u32>
SPI/I2S version register
SPI_IPIDR: RORegister<u32>
SPI/I2S identification register
SPI_SIDR: RORegister<u32>
SPI/I2S size identification register