pub struct ResetValues {Show 224 fields
pub RCC_TZCR: u32,
pub RCC_OCENSETR: u32,
pub RCC_OCENCLRR: u32,
pub RCC_HSICFGR: u32,
pub RCC_CSICFGR: u32,
pub RCC_MPCKSELR: u32,
pub RCC_ASSCKSELR: u32,
pub RCC_RCK12SELR: u32,
pub RCC_MPCKDIVR: u32,
pub RCC_AXIDIVR: u32,
pub RCC_APB4DIVR: u32,
pub RCC_APB5DIVR: u32,
pub RCC_RTCDIVR: u32,
pub RCC_MSSCKSELR: u32,
pub RCC_PLL1CR: u32,
pub RCC_PLL1CFGR1: u32,
pub RCC_PLL1CFGR2: u32,
pub RCC_PLL1FRACR: u32,
pub RCC_PLL1CSGR: u32,
pub RCC_PLL2CR: u32,
pub RCC_PLL2CFGR1: u32,
pub RCC_PLL2CFGR2: u32,
pub RCC_PLL2FRACR: u32,
pub RCC_PLL2CSGR: u32,
pub RCC_I2C46CKSELR: u32,
pub RCC_SPI6CKSELR: u32,
pub RCC_UART1CKSELR: u32,
pub RCC_RNG1CKSELR: u32,
pub RCC_CPERCKSELR: u32,
pub RCC_STGENCKSELR: u32,
pub RCC_DDRITFCR: u32,
pub RCC_MP_BOOTCR: u32,
pub RCC_MP_SREQSETR: u32,
pub RCC_MP_SREQCLRR: u32,
pub RCC_MP_GCR: u32,
pub RCC_MP_APRSTCR: u32,
pub RCC_MP_APRSTSR: u32,
pub RCC_BDCR: u32,
pub RCC_RDLSICR: u32,
pub RCC_APB4RSTSETR: u32,
pub RCC_APB4RSTCLRR: u32,
pub RCC_APB5RSTSETR: u32,
pub RCC_APB5RSTCLRR: u32,
pub RCC_AHB5RSTSETR: u32,
pub RCC_AHB5RSTCLRR: u32,
pub RCC_AHB6RSTSETR: u32,
pub RCC_AHB6RSTCLRR: u32,
pub RCC_TZAHB6RSTSETR: u32,
pub RCC_TZAHB6RSTCLRR: u32,
pub RCC_MP_APB4ENSETR: u32,
pub RCC_MP_APB4ENCLRR: u32,
pub RCC_MP_APB5ENSETR: u32,
pub RCC_MP_APB5ENCLRR: u32,
pub RCC_MP_AHB5ENSETR: u32,
pub RCC_MP_AHB5ENCLRR: u32,
pub RCC_MP_AHB6ENSETR: u32,
pub RCC_MP_AHB6ENCLRR: u32,
pub RCC_MP_TZAHB6ENSETR: u32,
pub RCC_MP_TZAHB6ENCLRR: u32,
pub RCC_MC_APB4ENSETR: u32,
pub RCC_MC_APB4ENCLRR: u32,
pub RCC_MC_APB5ENSETR: u32,
pub RCC_MC_APB5ENCLRR: u32,
pub RCC_MC_AHB5ENSETR: u32,
pub RCC_MC_AHB5ENCLRR: u32,
pub RCC_MC_AHB6ENSETR: u32,
pub RCC_MC_AHB6ENCLRR: u32,
pub RCC_MP_APB4LPENSETR: u32,
pub RCC_MP_APB4LPENCLRR: u32,
pub RCC_MP_APB5LPENSETR: u32,
pub RCC_MP_APB5LPENCLRR: u32,
pub RCC_MP_AHB5LPENSETR: u32,
pub RCC_MP_AHB5LPENCLRR: u32,
pub RCC_MP_AHB6LPENSETR: u32,
pub RCC_MP_AHB6LPENCLRR: u32,
pub RCC_MP_TZAHB6LPENSETR: u32,
pub RCC_MP_TZAHB6LPENCLRR: u32,
pub RCC_MC_APB4LPENSETR: u32,
pub RCC_MC_APB4LPENCLRR: u32,
pub RCC_MC_APB5LPENSETR: u32,
pub RCC_MC_APB5LPENCLRR: u32,
pub RCC_MC_AHB5LPENSETR: u32,
pub RCC_MC_AHB5LPENCLRR: u32,
pub RCC_MC_AHB6LPENSETR: u32,
pub RCC_MC_AHB6LPENCLRR: u32,
pub RCC_BR_RSTSCLRR: u32,
pub RCC_MP_GRSTCSETR: u32,
pub RCC_MP_RSTSCLRR: u32,
pub RCC_MP_IWDGFZSETR: u32,
pub RCC_MP_IWDGFZCLRR: u32,
pub RCC_MP_CIER: u32,
pub RCC_MP_CIFR: u32,
pub RCC_PWRLPDLYCR: u32,
pub RCC_MP_RSTSSETR: u32,
pub RCC_MCO1CFGR: u32,
pub RCC_MCO2CFGR: u32,
pub RCC_OCRDYR: u32,
pub RCC_DBGCFGR: u32,
pub RCC_RCK3SELR: u32,
pub RCC_RCK4SELR: u32,
pub RCC_TIMG1PRER: u32,
pub RCC_TIMG2PRER: u32,
pub RCC_MCUDIVR: u32,
pub RCC_APB1DIVR: u32,
pub RCC_APB2DIVR: u32,
pub RCC_APB3DIVR: u32,
pub RCC_PLL3CR: u32,
pub RCC_PLL3CFGR1: u32,
pub RCC_PLL3CFGR2: u32,
pub RCC_PLL3FRACR: u32,
pub RCC_PLL3CSGR: u32,
pub RCC_PLL4CR: u32,
pub RCC_PLL4CFGR1: u32,
pub RCC_PLL4CFGR2: u32,
pub RCC_PLL4FRACR: u32,
pub RCC_PLL4CSGR: u32,
pub RCC_I2C12CKSELR: u32,
pub RCC_I2C35CKSELR: u32,
pub RCC_SAI1CKSELR: u32,
pub RCC_SAI2CKSELR: u32,
pub RCC_SAI3CKSELR: u32,
pub RCC_SAI4CKSELR: u32,
pub RCC_SPI2S1CKSELR: u32,
pub RCC_SPI2S23CKSELR: u32,
pub RCC_SPI45CKSELR: u32,
pub RCC_UART6CKSELR: u32,
pub RCC_UART24CKSELR: u32,
pub RCC_UART35CKSELR: u32,
pub RCC_UART78CKSELR: u32,
pub RCC_SDMMC12CKSELR: u32,
pub RCC_SDMMC3CKSELR: u32,
pub RCC_ETHCKSELR: u32,
pub RCC_QSPICKSELR: u32,
pub RCC_FMCCKSELR: u32,
pub RCC_FDCANCKSELR: u32,
pub RCC_SPDIFCKSELR: u32,
pub RCC_CECCKSELR: u32,
pub RCC_USBCKSELR: u32,
pub RCC_RNG2CKSELR: u32,
pub RCC_DSICKSELR: u32,
pub RCC_ADCCKSELR: u32,
pub RCC_LPTIM45CKSELR: u32,
pub RCC_LPTIM23CKSELR: u32,
pub RCC_LPTIM1CKSELR: u32,
pub RCC_APB1RSTSETR: u32,
pub RCC_APB1RSTCLRR: u32,
pub RCC_APB2RSTSETR: u32,
pub RCC_APB2RSTCLRR: u32,
pub RCC_APB3RSTSETR: u32,
pub RCC_APB3RSTCLRR: u32,
pub RCC_AHB2RSTSETR: u32,
pub RCC_AHB2RSTCLRR: u32,
pub RCC_AHB3RSTSETR: u32,
pub RCC_AHB3RSTCLRR: u32,
pub RCC_AHB4RSTSETR: u32,
pub RCC_AHB4RSTCLRR: u32,
pub RCC_MP_APB1ENSETR: u32,
pub RCC_MP_APB1ENCLRR: u32,
pub RCC_MP_APB2ENSETR: u32,
pub RCC_MP_APB2ENCLRR: u32,
pub RCC_MP_APB3ENSETR: u32,
pub RCC_MP_APB3ENCLRR: u32,
pub RCC_MP_AHB2ENSETR: u32,
pub RCC_MP_AHB2ENCLRR: u32,
pub RCC_MP_AHB3ENSETR: u32,
pub RCC_MP_AHB3ENCLRR: u32,
pub RCC_MP_AHB4ENSETR: u32,
pub RCC_MP_AHB4ENCLRR: u32,
pub RCC_MP_MLAHBENSETR: u32,
pub RCC_MP_MLAHBENCLRR: u32,
pub RCC_MC_APB1ENSETR: u32,
pub RCC_MC_APB1ENCLRR: u32,
pub RCC_MC_APB2ENSETR: u32,
pub RCC_MC_APB2ENCLRR: u32,
pub RCC_MC_APB3ENSETR: u32,
pub RCC_MC_APB3ENCLRR: u32,
pub RCC_MC_AHB2ENSETR: u32,
pub RCC_MC_AHB2ENCLRR: u32,
pub RCC_MC_AHB3ENSETR: u32,
pub RCC_MC_AHB3ENCLRR: u32,
pub RCC_MC_AHB4ENSETR: u32,
pub RCC_MC_AHB4ENCLRR: u32,
pub RCC_MC_AXIMENSETR: u32,
pub RCC_MC_AXIMENCLRR: u32,
pub RCC_MC_MLAHBENSETR: u32,
pub RCC_MC_MLAHBENCLRR: u32,
pub RCC_MP_APB1LPENSETR: u32,
pub RCC_MP_APB1LPENCLRR: u32,
pub RCC_MP_APB2LPENSETR: u32,
pub RCC_MP_APB2LPENCLRR: u32,
pub RCC_MP_APB3LPENSETR: u32,
pub RCC_MP_APB3LPENCLRR: u32,
pub RCC_MP_AHB2LPENSETR: u32,
pub RCC_MP_AHB2LPENCLRR: u32,
pub RCC_MP_AHB3LPENSETR: u32,
pub RCC_MP_AHB3LPENCLRR: u32,
pub RCC_MP_AHB4LPENSETR: u32,
pub RCC_MP_AHB4LPENCLRR: u32,
pub RCC_MP_AXIMLPENSETR: u32,
pub RCC_MP_AXIMLPENCLRR: u32,
pub RCC_MP_MLAHBLPENSETR: u32,
pub RCC_MP_MLAHBLPENCLRR: u32,
pub RCC_MC_APB1LPENSETR: u32,
pub RCC_MC_APB1LPENCLRR: u32,
pub RCC_MC_APB2LPENSETR: u32,
pub RCC_MC_APB2LPENCLRR: u32,
pub RCC_MC_APB3LPENSETR: u32,
pub RCC_MC_APB3LPENCLRR: u32,
pub RCC_MC_AHB2LPENSETR: u32,
pub RCC_MC_AHB2LPENCLRR: u32,
pub RCC_MC_AHB3LPENSETR: u32,
pub RCC_MC_AHB3LPENCLRR: u32,
pub RCC_MC_AHB4LPENSETR: u32,
pub RCC_MC_AHB4LPENCLRR: u32,
pub RCC_MC_AXIMLPENSETR: u32,
pub RCC_MC_AXIMLPENCLRR: u32,
pub RCC_MC_MLAHBLPENSETR: u32,
pub RCC_MC_MLAHBLPENCLRR: u32,
pub RCC_MC_RSTSCLRR: u32,
pub RCC_MC_CIER: u32,
pub RCC_MC_CIFR: u32,
pub RCC_VERR: u32,
pub RCC_IDR: u32,
pub RCC_SIDR: u32,