Struct stm32ral::stm32mp::peripherals::pwr::RegisterBlock[−][src]

#[repr(C)]
pub struct RegisterBlock {Show 13 fields
    pub PWR_CR1: RWRegister<u32>,
    pub PWR_CSR1: RORegister<u32>,
    pub PWR_CR2: RWRegister<u32>,
    pub PWR_CR3: RWRegister<u32>,
    pub PWR_MPUCR: RWRegister<u32>,
    pub PWR_MCUCR: RWRegister<u32>,
    pub PWR_WKUPCR: RWRegister<u32>,
    pub PWR_WKUPFR: RORegister<u32>,
    pub PWR_MPUWKUPENR: RWRegister<u32>,
    pub PWR_MCUWKUPENR: RWRegister<u32>,
    pub PWR_VER: RORegister<u32>,
    pub PWR_ID: RORegister<u32>,
    pub PWR_SID: RORegister<u32>,
    // some fields omitted
}

Fields

PWR_CR1: RWRegister<u32>

Reset on any system reset. This register provides write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value.

PWR_CSR1: RORegister<u32>

Reset on any system reset.

PWR_CR2: RWRegister<u32>

Not reset by wakeup from Standby mode, Application reset (NRST, IWDG, …) and VDD POR, but reset only by VSW POR and VSWRST. Access 6 wait states when writing this register. After reset the register is write-protected and the DBP bit in the PWR control register 1 (PWR_CR1) has to be set before it can be written. When DBP is cleared, there is no bus errors generated when writing this register. This register shall not be accessed when the RCC VSWRST register bit in Section10.7.89: RCC Backup Domain Control Register (RCC_BDCR) resets the VSW domain. This register provides Write access security when enabled by TZEN register bit in Section10.7.2: RCC TrustZone Control Register (RCC_TZCR). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.

PWR_CR3: RWRegister<u32>

Not reset by wakeup from Standby mode and Application reset (such as NRST, IWDG) but only reset by VDD POR. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.

PWR_MPUCR: RWRegister<u32>

See individual bits for reset condition. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.

PWR_MCUCR: RWRegister<u32>

See individual bits for reset condition. Access 6 wait states when writing this register. This register is always non-secure. When a system reset occurs during the register write cycle the written data is not guaranteed.

PWR_WKUPCR: RWRegister<u32>

Not reset by wakeup from Standby mode, but by any application reset (such as NRST, IWDG). Access 6 wait states when writing this register (when clearing a WKUPF, the AHB write access completes after the WKUPF has cleared). This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access on individual WKUPC[6:1], WKUPP[6:1] bits and WKUPPUPD[6:1] bit pairs are discarded when the corresponding WKUPEN[6:1] bit in PWR MPU wakeup enable register (PWR_MPUWKUPENR) is set. No bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.

PWR_WKUPFR: RORegister<u32>

Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, …)

PWR_MPUWKUPENR: RWRegister<u32>

Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, …). Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access is discarded and a bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.

PWR_MCUWKUPENR: RWRegister<u32>

Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, …) Access 6 wait states when writing this register. When a system reset occurs during the register write cycle the written data is not guaranteed.

PWR_VER: RORegister<u32>

PWR IP version register

PWR_ID: RORegister<u32>

PWR IP identification register

PWR_SID: RORegister<u32>

PWR size ID register