Struct stm32ral::stm32mp::peripherals::hsem::ResetValues [−][src]
pub struct ResetValues {Show 79 fields
pub HSEM_R0: u32,
pub HSEM_R1: u32,
pub HSEM_R2: u32,
pub HSEM_R3: u32,
pub HSEM_R4: u32,
pub HSEM_R5: u32,
pub HSEM_R6: u32,
pub HSEM_R7: u32,
pub HSEM_R8: u32,
pub HSEM_R9: u32,
pub HSEM_R10: u32,
pub HSEM_R11: u32,
pub HSEM_R12: u32,
pub HSEM_R13: u32,
pub HSEM_R14: u32,
pub HSEM_R15: u32,
pub HSEM_R16: u32,
pub HSEM_R17: u32,
pub HSEM_R18: u32,
pub HSEM_R19: u32,
pub HSEM_R20: u32,
pub HSEM_R21: u32,
pub HSEM_R22: u32,
pub HSEM_R23: u32,
pub HSEM_R24: u32,
pub HSEM_R25: u32,
pub HSEM_R26: u32,
pub HSEM_R27: u32,
pub HSEM_R28: u32,
pub HSEM_R29: u32,
pub HSEM_R30: u32,
pub HSEM_R31: u32,
pub HSEM_RLR0: u32,
pub HSEM_RLR1: u32,
pub HSEM_RLR2: u32,
pub HSEM_RLR3: u32,
pub HSEM_RLR4: u32,
pub HSEM_RLR5: u32,
pub HSEM_RLR6: u32,
pub HSEM_RLR7: u32,
pub HSEM_RLR8: u32,
pub HSEM_RLR9: u32,
pub HSEM_RLR10: u32,
pub HSEM_RLR11: u32,
pub HSEM_RLR12: u32,
pub HSEM_RLR13: u32,
pub HSEM_RLR14: u32,
pub HSEM_RLR15: u32,
pub HSEM_RLR16: u32,
pub HSEM_RLR17: u32,
pub HSEM_RLR18: u32,
pub HSEM_RLR19: u32,
pub HSEM_RLR20: u32,
pub HSEM_RLR21: u32,
pub HSEM_RLR22: u32,
pub HSEM_RLR23: u32,
pub HSEM_RLR24: u32,
pub HSEM_RLR25: u32,
pub HSEM_RLR26: u32,
pub HSEM_RLR27: u32,
pub HSEM_RLR28: u32,
pub HSEM_RLR29: u32,
pub HSEM_RLR30: u32,
pub HSEM_RLR31: u32,
pub HSEM_C1IER: u32,
pub HSEM_C1ICR: u32,
pub HSEM_C1ISR: u32,
pub HSEM_C1MISR: u32,
pub HSEM_C2IER: u32,
pub HSEM_C2ICR: u32,
pub HSEM_C2ISR: u32,
pub HSEM_C2MISR: u32,
pub HSEM_CR: u32,
pub HSEM_KEYR: u32,
pub HSEM_HWCFGR2: u32,
pub HSEM_HWCFGR1: u32,
pub HSEM_VERR: u32,
pub HSEM_IPIDR: u32,
pub HSEM_SIDR: u32,
}Fields
HSEM_R0: u32HSEM_R1: u32HSEM_R2: u32HSEM_R3: u32HSEM_R4: u32HSEM_R5: u32HSEM_R6: u32HSEM_R7: u32HSEM_R8: u32HSEM_R9: u32HSEM_R10: u32HSEM_R11: u32HSEM_R12: u32HSEM_R13: u32HSEM_R14: u32HSEM_R15: u32HSEM_R16: u32HSEM_R17: u32HSEM_R18: u32HSEM_R19: u32HSEM_R20: u32HSEM_R21: u32HSEM_R22: u32HSEM_R23: u32HSEM_R24: u32HSEM_R25: u32HSEM_R26: u32HSEM_R27: u32HSEM_R28: u32HSEM_R29: u32HSEM_R30: u32HSEM_R31: u32HSEM_RLR0: u32HSEM_RLR1: u32HSEM_RLR2: u32HSEM_RLR3: u32HSEM_RLR4: u32HSEM_RLR5: u32HSEM_RLR6: u32HSEM_RLR7: u32HSEM_RLR8: u32HSEM_RLR9: u32HSEM_RLR10: u32HSEM_RLR11: u32HSEM_RLR12: u32HSEM_RLR13: u32HSEM_RLR14: u32HSEM_RLR15: u32HSEM_RLR16: u32HSEM_RLR17: u32HSEM_RLR18: u32HSEM_RLR19: u32HSEM_RLR20: u32HSEM_RLR21: u32HSEM_RLR22: u32HSEM_RLR23: u32HSEM_RLR24: u32HSEM_RLR25: u32HSEM_RLR26: u32HSEM_RLR27: u32HSEM_RLR28: u32HSEM_RLR29: u32HSEM_RLR30: u32HSEM_RLR31: u32HSEM_C1IER: u32HSEM_C1ICR: u32HSEM_C1ISR: u32HSEM_C1MISR: u32HSEM_C2IER: u32HSEM_C2ICR: u32HSEM_C2ISR: u32HSEM_C2MISR: u32HSEM_CR: u32HSEM_KEYR: u32HSEM_HWCFGR2: u32HSEM_HWCFGR1: u32HSEM_VERR: u32HSEM_IPIDR: u32HSEM_SIDR: u32