Struct stm32ral::stm32mp::peripherals::gpioj::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub GPIOJ_MODER: RWRegister<u32>,
    pub GPIOJ_OTYPER: RWRegister<u32>,
    pub GPIOJ_OSPEEDR: RWRegister<u32>,
    pub GPIOJ_PUPDR: RWRegister<u32>,
    pub GPIOJ_IDR: RORegister<u32>,
    pub GPIOJ_ODR: RWRegister<u32>,
    pub GPIOJ_BSRR: WORegister<u32>,
    pub GPIOJ_LCKR: RWRegister<u32>,
    pub GPIOJ_AFRL: RWRegister<u32>,
    pub GPIOJ_AFRH: RWRegister<u32>,
    pub GPIOJ_BRR: WORegister<u32>,
    pub GPIOJ_HWCFGR10: RORegister<u32>,
    pub GPIOJ_HWCFGR9: RORegister<u32>,
    pub GPIOJ_HWCFGR8: RORegister<u32>,
    pub GPIOJ_HWCFGR7: RORegister<u32>,
    pub GPIOJ_HWCFGR6: RORegister<u32>,
    pub GPIOJ_HWCFGR5: RORegister<u32>,
    pub GPIOJ_HWCFGR4: RORegister<u32>,
    pub GPIOJ_HWCFGR3: RORegister<u32>,
    pub GPIOJ_HWCFGR2: RORegister<u32>,
    pub GPIOJ_HWCFGR1: RORegister<u32>,
    pub GPIOJ_HWCFGR0: RORegister<u32>,
    pub GPIOJ_VERR: RORegister<u32>,
    pub GPIOJ_IPIDR: RORegister<u32>,
    pub GPIOJ_SIDR: RORegister<u32>,
    // some fields omitted
}

Fields

GPIOJ_MODER: RWRegister<u32>

GPIO port mode register

GPIOJ_OTYPER: RWRegister<u32>

GPIO port output type register

GPIOJ_OSPEEDR: RWRegister<u32>

GPIO port output speed register

GPIOJ_PUPDR: RWRegister<u32>

GPIO port pull-up/pull-down register

GPIOJ_IDR: RORegister<u32>

GPIO port input data register

GPIOJ_ODR: RWRegister<u32>

GPIO port output data register

GPIOJ_BSRR: WORegister<u32>

GPIO port bit set/reset register

GPIOJ_LCKR: RWRegister<u32>

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).

GPIOJ_AFRL: RWRegister<u32>

GPIO alternate function low register

GPIOJ_AFRH: RWRegister<u32>

GPIO alternate function high register

GPIOJ_BRR: WORegister<u32>

GPIO port bit reset register

GPIOJ_HWCFGR10: RORegister<u32>

For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:

GPIOJ_HWCFGR9: RORegister<u32>

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

GPIOJ_HWCFGR8: RORegister<u32>

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

GPIOJ_HWCFGR7: RORegister<u32>

GPIO hardware configuration register 7

GPIOJ_HWCFGR6: RORegister<u32>

GPIO hardware configuration register 6

GPIOJ_HWCFGR5: RORegister<u32>

GPIO hardware configuration register 5

GPIOJ_HWCFGR4: RORegister<u32>

GPIO hardware configuration register 4

GPIOJ_HWCFGR3: RORegister<u32>

GPIO hardware configuration register 3

GPIOJ_HWCFGR2: RORegister<u32>

GPIO hardware configuration register 2

GPIOJ_HWCFGR1: RORegister<u32>

GPIO hardware configuration register 1

GPIOJ_HWCFGR0: RORegister<u32>

GPIO hardware configuration register 0

GPIOJ_VERR: RORegister<u32>

GPIO version register

GPIOJ_IPIDR: RORegister<u32>

GPIO identification register

GPIOJ_SIDR: RORegister<u32>

GPIO size identification register