Struct stm32ral::stm32mp::peripherals::gpioh::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub GPIOH_MODER: RWRegister<u32>,
    pub GPIOH_OTYPER: RWRegister<u32>,
    pub GPIOH_OSPEEDR: RWRegister<u32>,
    pub GPIOH_PUPDR: RWRegister<u32>,
    pub GPIOH_IDR: RORegister<u32>,
    pub GPIOH_ODR: RWRegister<u32>,
    pub GPIOH_BSRR: WORegister<u32>,
    pub GPIOH_LCKR: RWRegister<u32>,
    pub GPIOH_AFRL: RWRegister<u32>,
    pub GPIOH_AFRH: RWRegister<u32>,
    pub GPIOH_BRR: WORegister<u32>,
    pub GPIOH_HWCFGR10: RORegister<u32>,
    pub GPIOH_HWCFGR9: RORegister<u32>,
    pub GPIOH_HWCFGR8: RORegister<u32>,
    pub GPIOH_HWCFGR7: RORegister<u32>,
    pub GPIOH_HWCFGR6: RORegister<u32>,
    pub GPIOH_HWCFGR5: RORegister<u32>,
    pub GPIOH_HWCFGR4: RORegister<u32>,
    pub GPIOH_HWCFGR3: RORegister<u32>,
    pub GPIOH_HWCFGR2: RORegister<u32>,
    pub GPIOH_HWCFGR1: RORegister<u32>,
    pub GPIOH_HWCFGR0: RORegister<u32>,
    pub GPIOH_VERR: RORegister<u32>,
    pub GPIOH_IPIDR: RORegister<u32>,
    pub GPIOH_SIDR: RORegister<u32>,
    // some fields omitted
}

Fields

GPIOH_MODER: RWRegister<u32>

GPIO port mode register

GPIOH_OTYPER: RWRegister<u32>

GPIO port output type register

GPIOH_OSPEEDR: RWRegister<u32>

GPIO port output speed register

GPIOH_PUPDR: RWRegister<u32>

GPIO port pull-up/pull-down register

GPIOH_IDR: RORegister<u32>

GPIO port input data register

GPIOH_ODR: RWRegister<u32>

GPIO port output data register

GPIOH_BSRR: WORegister<u32>

GPIO port bit set/reset register

GPIOH_LCKR: RWRegister<u32>

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).

GPIOH_AFRL: RWRegister<u32>

GPIO alternate function low register

GPIOH_AFRH: RWRegister<u32>

GPIO alternate function high register

GPIOH_BRR: WORegister<u32>

GPIO port bit reset register

GPIOH_HWCFGR10: RORegister<u32>

For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:

GPIOH_HWCFGR9: RORegister<u32>

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

GPIOH_HWCFGR8: RORegister<u32>

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

GPIOH_HWCFGR7: RORegister<u32>

GPIO hardware configuration register 7

GPIOH_HWCFGR6: RORegister<u32>

GPIO hardware configuration register 6

GPIOH_HWCFGR5: RORegister<u32>

GPIO hardware configuration register 5

GPIOH_HWCFGR4: RORegister<u32>

GPIO hardware configuration register 4

GPIOH_HWCFGR3: RORegister<u32>

GPIO hardware configuration register 3

GPIOH_HWCFGR2: RORegister<u32>

GPIO hardware configuration register 2

GPIOH_HWCFGR1: RORegister<u32>

GPIO hardware configuration register 1

GPIOH_HWCFGR0: RORegister<u32>

GPIO hardware configuration register 0

GPIOH_VERR: RORegister<u32>

GPIO version register

GPIOH_IPIDR: RORegister<u32>

GPIO identification register

GPIOH_SIDR: RORegister<u32>

GPIO size identification register