Struct stm32ral::stm32mp::peripherals::gicd::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 257 fields
pub GICD_CTLR: RWRegister<u32>,
pub GICD_TYPER: RORegister<u32>,
pub GICD_IIDR: RORegister<u32>,
pub GICD_IGROUPR0: RWRegister<u32>,
pub GICD_IGROUPR1: RWRegister<u32>,
pub GICD_IGROUPR2: RWRegister<u32>,
pub GICD_IGROUPR3: RWRegister<u32>,
pub GICD_IGROUPR4: RWRegister<u32>,
pub GICD_IGROUPR5: RWRegister<u32>,
pub GICD_IGROUPR6: RWRegister<u32>,
pub GICD_IGROUPR7: RWRegister<u32>,
pub GICD_IGROUPR8: RWRegister<u32>,
pub GICD_ISENABLER0: RWRegister<u32>,
pub GICD_ISENABLER1: RWRegister<u32>,
pub GICD_ISENABLER2: RWRegister<u32>,
pub GICD_ISENABLER3: RWRegister<u32>,
pub GICD_ISENABLER4: RWRegister<u32>,
pub GICD_ISENABLER5: RWRegister<u32>,
pub GICD_ISENABLER6: RWRegister<u32>,
pub GICD_ISENABLER7: RWRegister<u32>,
pub GICD_ISENABLER8: RWRegister<u32>,
pub GICD_ICENABLER0: RWRegister<u32>,
pub GICD_ICENABLER1: RWRegister<u32>,
pub GICD_ICENABLER2: RWRegister<u32>,
pub GICD_ICENABLER3: RWRegister<u32>,
pub GICD_ICENABLER4: RWRegister<u32>,
pub GICD_ICENABLER5: RWRegister<u32>,
pub GICD_ICENABLER6: RWRegister<u32>,
pub GICD_ICENABLER7: RWRegister<u32>,
pub GICD_ICENABLER8: RWRegister<u32>,
pub GICD_ISPENDR0: RWRegister<u32>,
pub GICD_ISPENDR1: RWRegister<u32>,
pub GICD_ISPENDR2: RWRegister<u32>,
pub GICD_ISPENDR3: RWRegister<u32>,
pub GICD_ISPENDR4: RWRegister<u32>,
pub GICD_ISPENDR5: RWRegister<u32>,
pub GICD_ISPENDR6: RWRegister<u32>,
pub GICD_ISPENDR7: RWRegister<u32>,
pub GICD_ISPENDR8: RWRegister<u32>,
pub GICD_ICPENDR0: RWRegister<u32>,
pub GICD_ICPENDR1: RWRegister<u32>,
pub GICD_ICPENDR2: RWRegister<u32>,
pub GICD_ICPENDR3: RWRegister<u32>,
pub GICD_ICPENDR4: RWRegister<u32>,
pub GICD_ICPENDR5: RWRegister<u32>,
pub GICD_ICPENDR6: RWRegister<u32>,
pub GICD_ICPENDR7: RWRegister<u32>,
pub GICD_ICPENDR8: RWRegister<u32>,
pub GICD_ISACTIVER0: RWRegister<u32>,
pub GICD_ISACTIVER1: RWRegister<u32>,
pub GICD_ISACTIVER2: RWRegister<u32>,
pub GICD_ISACTIVER3: RWRegister<u32>,
pub GICD_ISACTIVER4: RWRegister<u32>,
pub GICD_ISACTIVER5: RWRegister<u32>,
pub GICD_ISACTIVER6: RWRegister<u32>,
pub GICD_ISACTIVER7: RWRegister<u32>,
pub GICD_ISACTIVER8: RWRegister<u32>,
pub GICD_ICACTIVER0: RWRegister<u32>,
pub GICD_ICACTIVER1: RWRegister<u32>,
pub GICD_ICACTIVER2: RWRegister<u32>,
pub GICD_ICACTIVER3: RWRegister<u32>,
pub GICD_ICACTIVER4: RWRegister<u32>,
pub GICD_ICACTIVER5: RWRegister<u32>,
pub GICD_ICACTIVER6: RWRegister<u32>,
pub GICD_ICACTIVER7: RWRegister<u32>,
pub GICD_ICACTIVER8: RWRegister<u32>,
pub GICD_IPRIORITYR0: RWRegister<u32>,
pub GICD_IPRIORITYR1: RWRegister<u32>,
pub GICD_IPRIORITYR2: RWRegister<u32>,
pub GICD_IPRIORITYR3: RWRegister<u32>,
pub GICD_IPRIORITYR4: RWRegister<u32>,
pub GICD_IPRIORITYR5: RWRegister<u32>,
pub GICD_IPRIORITYR6: RWRegister<u32>,
pub GICD_IPRIORITYR7: RWRegister<u32>,
pub GICD_IPRIORITYR8: RWRegister<u32>,
pub GICD_IPRIORITYR9: RWRegister<u32>,
pub GICD_IPRIORITYR10: RWRegister<u32>,
pub GICD_IPRIORITYR11: RWRegister<u32>,
pub GICD_IPRIORITYR12: RWRegister<u32>,
pub GICD_IPRIORITYR13: RWRegister<u32>,
pub GICD_IPRIORITYR14: RWRegister<u32>,
pub GICD_IPRIORITYR15: RWRegister<u32>,
pub GICD_IPRIORITYR16: RWRegister<u32>,
pub GICD_IPRIORITYR17: RWRegister<u32>,
pub GICD_IPRIORITYR18: RWRegister<u32>,
pub GICD_IPRIORITYR19: RWRegister<u32>,
pub GICD_IPRIORITYR20: RWRegister<u32>,
pub GICD_IPRIORITYR21: RWRegister<u32>,
pub GICD_IPRIORITYR22: RWRegister<u32>,
pub GICD_IPRIORITYR23: RWRegister<u32>,
pub GICD_IPRIORITYR24: RWRegister<u32>,
pub GICD_IPRIORITYR25: RWRegister<u32>,
pub GICD_IPRIORITYR26: RWRegister<u32>,
pub GICD_IPRIORITYR27: RWRegister<u32>,
pub GICD_IPRIORITYR28: RWRegister<u32>,
pub GICD_IPRIORITYR29: RWRegister<u32>,
pub GICD_IPRIORITYR30: RWRegister<u32>,
pub GICD_IPRIORITYR31: RWRegister<u32>,
pub GICD_IPRIORITYR32: RWRegister<u32>,
pub GICD_IPRIORITYR33: RWRegister<u32>,
pub GICD_IPRIORITYR34: RWRegister<u32>,
pub GICD_IPRIORITYR35: RWRegister<u32>,
pub GICD_IPRIORITYR36: RWRegister<u32>,
pub GICD_IPRIORITYR37: RWRegister<u32>,
pub GICD_IPRIORITYR38: RWRegister<u32>,
pub GICD_IPRIORITYR39: RWRegister<u32>,
pub GICD_IPRIORITYR40: RWRegister<u32>,
pub GICD_IPRIORITYR41: RWRegister<u32>,
pub GICD_IPRIORITYR42: RWRegister<u32>,
pub GICD_IPRIORITYR43: RWRegister<u32>,
pub GICD_IPRIORITYR44: RWRegister<u32>,
pub GICD_IPRIORITYR45: RWRegister<u32>,
pub GICD_IPRIORITYR46: RWRegister<u32>,
pub GICD_IPRIORITYR47: RWRegister<u32>,
pub GICD_IPRIORITYR48: RWRegister<u32>,
pub GICD_IPRIORITYR49: RWRegister<u32>,
pub GICD_IPRIORITYR50: RWRegister<u32>,
pub GICD_IPRIORITYR51: RWRegister<u32>,
pub GICD_IPRIORITYR52: RWRegister<u32>,
pub GICD_IPRIORITYR53: RWRegister<u32>,
pub GICD_IPRIORITYR54: RWRegister<u32>,
pub GICD_IPRIORITYR55: RWRegister<u32>,
pub GICD_IPRIORITYR56: RWRegister<u32>,
pub GICD_IPRIORITYR57: RWRegister<u32>,
pub GICD_IPRIORITYR58: RWRegister<u32>,
pub GICD_IPRIORITYR59: RWRegister<u32>,
pub GICD_IPRIORITYR60: RWRegister<u32>,
pub GICD_IPRIORITYR61: RWRegister<u32>,
pub GICD_IPRIORITYR62: RWRegister<u32>,
pub GICD_IPRIORITYR63: RWRegister<u32>,
pub GICD_IPRIORITYR64: RWRegister<u32>,
pub GICD_IPRIORITYR65: RWRegister<u32>,
pub GICD_IPRIORITYR66: RWRegister<u32>,
pub GICD_IPRIORITYR67: RWRegister<u32>,
pub GICD_IPRIORITYR68: RWRegister<u32>,
pub GICD_IPRIORITYR69: RWRegister<u32>,
pub GICD_IPRIORITYR70: RWRegister<u32>,
pub GICD_IPRIORITYR71: RWRegister<u32>,
pub GICD_ITARGETSR0: RORegister<u32>,
pub GICD_ITARGETSR1: RORegister<u32>,
pub GICD_ITARGETSR2: RORegister<u32>,
pub GICD_ITARGETSR3: RORegister<u32>,
pub GICD_ITARGETSR4: RORegister<u32>,
pub GICD_ITARGETSR5: RORegister<u32>,
pub GICD_ITARGETSR6: RORegister<u32>,
pub GICD_ITARGETSR7: RORegister<u32>,
pub GICD_ITARGETSR8: RWRegister<u32>,
pub GICD_ITARGETSR9: RWRegister<u32>,
pub GICD_ITARGETSR10: RWRegister<u32>,
pub GICD_ITARGETSR11: RWRegister<u32>,
pub GICD_ITARGETSR12: RWRegister<u32>,
pub GICD_ITARGETSR13: RWRegister<u32>,
pub GICD_ITARGETSR14: RWRegister<u32>,
pub GICD_ITARGETSR15: RWRegister<u32>,
pub GICD_ITARGETSR16: RWRegister<u32>,
pub GICD_ITARGETSR17: RWRegister<u32>,
pub GICD_ITARGETSR18: RWRegister<u32>,
pub GICD_ITARGETSR19: RWRegister<u32>,
pub GICD_ITARGETSR20: RWRegister<u32>,
pub GICD_ITARGETSR21: RWRegister<u32>,
pub GICD_ITARGETSR22: RWRegister<u32>,
pub GICD_ITARGETSR23: RWRegister<u32>,
pub GICD_ITARGETSR24: RWRegister<u32>,
pub GICD_ITARGETSR25: RWRegister<u32>,
pub GICD_ITARGETSR26: RWRegister<u32>,
pub GICD_ITARGETSR27: RWRegister<u32>,
pub GICD_ITARGETSR28: RWRegister<u32>,
pub GICD_ITARGETSR29: RWRegister<u32>,
pub GICD_ITARGETSR30: RWRegister<u32>,
pub GICD_ITARGETSR31: RWRegister<u32>,
pub GICD_ITARGETSR32: RWRegister<u32>,
pub GICD_ITARGETSR33: RWRegister<u32>,
pub GICD_ITARGETSR34: RWRegister<u32>,
pub GICD_ITARGETSR35: RWRegister<u32>,
pub GICD_ITARGETSR36: RWRegister<u32>,
pub GICD_ITARGETSR37: RWRegister<u32>,
pub GICD_ITARGETSR38: RWRegister<u32>,
pub GICD_ITARGETSR39: RWRegister<u32>,
pub GICD_ITARGETSR40: RWRegister<u32>,
pub GICD_ITARGETSR41: RWRegister<u32>,
pub GICD_ITARGETSR42: RWRegister<u32>,
pub GICD_ITARGETSR43: RWRegister<u32>,
pub GICD_ITARGETSR44: RWRegister<u32>,
pub GICD_ITARGETSR45: RWRegister<u32>,
pub GICD_ITARGETSR46: RWRegister<u32>,
pub GICD_ITARGETSR47: RWRegister<u32>,
pub GICD_ITARGETSR48: RWRegister<u32>,
pub GICD_ITARGETSR49: RWRegister<u32>,
pub GICD_ITARGETSR50: RWRegister<u32>,
pub GICD_ITARGETSR51: RWRegister<u32>,
pub GICD_ITARGETSR52: RWRegister<u32>,
pub GICD_ITARGETSR53: RWRegister<u32>,
pub GICD_ITARGETSR54: RWRegister<u32>,
pub GICD_ITARGETSR55: RWRegister<u32>,
pub GICD_ITARGETSR56: RWRegister<u32>,
pub GICD_ITARGETSR57: RWRegister<u32>,
pub GICD_ITARGETSR58: RWRegister<u32>,
pub GICD_ITARGETSR59: RWRegister<u32>,
pub GICD_ITARGETSR60: RWRegister<u32>,
pub GICD_ITARGETSR61: RWRegister<u32>,
pub GICD_ITARGETSR62: RWRegister<u32>,
pub GICD_ITARGETSR63: RWRegister<u32>,
pub GICD_ITARGETSR64: RWRegister<u32>,
pub GICD_ITARGETSR65: RWRegister<u32>,
pub GICD_ITARGETSR66: RWRegister<u32>,
pub GICD_ITARGETSR67: RWRegister<u32>,
pub GICD_ITARGETSR68: RWRegister<u32>,
pub GICD_ITARGETSR69: RWRegister<u32>,
pub GICD_ITARGETSR70: RWRegister<u32>,
pub GICD_ITARGETSR71: RWRegister<u32>,
pub GICD_ICFGR0: RWRegister<u32>,
pub GICD_ICFGR1: RWRegister<u32>,
pub GICD_ICFGR2: RWRegister<u32>,
pub GICD_ICFGR3: RWRegister<u32>,
pub GICD_ICFGR4: RWRegister<u32>,
pub GICD_ICFGR5: RWRegister<u32>,
pub GICD_ICFGR6: RWRegister<u32>,
pub GICD_ICFGR7: RWRegister<u32>,
pub GICD_ICFGR8: RWRegister<u32>,
pub GICD_ICFGR9: RWRegister<u32>,
pub GICD_ICFGR10: RWRegister<u32>,
pub GICD_ICFGR11: RWRegister<u32>,
pub GICD_ICFGR12: RWRegister<u32>,
pub GICD_ICFGR13: RWRegister<u32>,
pub GICD_ICFGR14: RWRegister<u32>,
pub GICD_ICFGR15: RWRegister<u32>,
pub GICD_ICFGR16: RWRegister<u32>,
pub GICD_ICFGR17: RWRegister<u32>,
pub GICD_PPISR: RORegister<u32>,
pub GICD_SPISR1: RORegister<u32>,
pub GICD_SPISR2: RORegister<u32>,
pub GICD_SPISR3: RORegister<u32>,
pub GICD_SPISR4: RORegister<u32>,
pub GICD_SPISR5: RORegister<u32>,
pub GICD_SPISR6: RORegister<u32>,
pub GICD_SPISR7: RORegister<u32>,
pub GICD_SGIR: WORegister<u32>,
pub GICD_CPENDSGIR0: RWRegister<u32>,
pub GICD_CPENDSGIR1: RWRegister<u32>,
pub GICD_CPENDSGIR2: RWRegister<u32>,
pub GICD_CPENDSGIR3: RWRegister<u32>,
pub GICD_SPENDSGIR0: RWRegister<u32>,
pub GICD_SPENDSGIR1: RWRegister<u32>,
pub GICD_SPENDSGIR2: RWRegister<u32>,
pub GICD_SPENDSGIR3: RWRegister<u32>,
pub GICD_PIDR4: RORegister<u32>,
pub GICD_PIDR5: RORegister<u32>,
pub GICD_PIDR6: RORegister<u32>,
pub GICD_PIDR7: RORegister<u32>,
pub GICD_PIDR0: RORegister<u32>,
pub GICD_PIDR1: RORegister<u32>,
pub GICD_PIDR2: RORegister<u32>,
pub GICD_PIDR3: RORegister<u32>,
pub GICD_CIDR0: RORegister<u32>,
pub GICD_CIDR1: RORegister<u32>,
pub GICD_CIDR2: RORegister<u32>,
pub GICD_CIDR3: RORegister<u32>,
// some fields omitted
}Fields
GICD_CTLR: RWRegister<u32>GICD control register
GICD_TYPER: RORegister<u32>GICD interrupt controller type register
GICD_IIDR: RORegister<u32>GICD implementer identification register
GICD_IGROUPR0: RWRegister<u32>For interrupts ID
GICD_IGROUPR1: RWRegister<u32>For interrupts ID
GICD_IGROUPR2: RWRegister<u32>For interrupts ID
GICD_IGROUPR3: RWRegister<u32>For interrupts ID = x32 to ID = x32+31
GICD_IGROUPR4: RWRegister<u32>For interrupts ID = x32 to ID = x32+31
GICD_IGROUPR5: RWRegister<u32>For interrupts ID
GICD_IGROUPR6: RWRegister<u32>For interrupts ID
GICD_IGROUPR7: RWRegister<u32>For interrupts ID
GICD_IGROUPR8: RWRegister<u32>For interrupts ID
GICD_ISENABLER0: RWRegister<u32>For interrupts ID = 0 to ID = 31
GICD_ISENABLER1: RWRegister<u32>For interrupts ID
GICD_ISENABLER2: RWRegister<u32>For interrupts ID
GICD_ISENABLER3: RWRegister<u32>For interrupts ID
GICD_ISENABLER4: RWRegister<u32>For interrupts ID
GICD_ISENABLER5: RWRegister<u32>For interrupts ID
GICD_ISENABLER6: RWRegister<u32>For interrupts ID
GICD_ISENABLER7: RWRegister<u32>For interrupts ID
GICD_ISENABLER8: RWRegister<u32>For interrupts ID
GICD_ICENABLER0: RWRegister<u32>For interrupts ID = 0 to ID = 31
GICD_ICENABLER1: RWRegister<u32>For interrupts ID
GICD_ICENABLER2: RWRegister<u32>For interrupts ID
GICD_ICENABLER3: RWRegister<u32>For interrupts ID
GICD_ICENABLER4: RWRegister<u32>For interrupts ID
GICD_ICENABLER5: RWRegister<u32>For interrupts ID
GICD_ICENABLER6: RWRegister<u32>For interrupts ID
GICD_ICENABLER7: RWRegister<u32>For interrupts ID
GICD_ICENABLER8: RWRegister<u32>For interrupts ID
GICD_ISPENDR0: RWRegister<u32>For interrupts ID
GICD_ISPENDR1: RWRegister<u32>For interrupts ID
GICD_ISPENDR2: RWRegister<u32>For interrupts ID
GICD_ISPENDR3: RWRegister<u32>For interrupts ID
GICD_ISPENDR4: RWRegister<u32>For interrupts ID
GICD_ISPENDR5: RWRegister<u32>For interrupts ID
GICD_ISPENDR6: RWRegister<u32>For interrupts ID
GICD_ISPENDR7: RWRegister<u32>For interrupts ID
GICD_ISPENDR8: RWRegister<u32>For interrupts ID
GICD_ICPENDR0: RWRegister<u32>For interrupts ID
GICD_ICPENDR1: RWRegister<u32>For interrupts ID
GICD_ICPENDR2: RWRegister<u32>For interrupts ID
GICD_ICPENDR3: RWRegister<u32>For interrupts ID
GICD_ICPENDR4: RWRegister<u32>For interrupts ID
GICD_ICPENDR5: RWRegister<u32>For interrupts ID
GICD_ICPENDR6: RWRegister<u32>For interrupts ID
GICD_ICPENDR7: RWRegister<u32>For interrupts ID
GICD_ICPENDR8: RWRegister<u32>For interrupts ID
GICD_ISACTIVER0: RWRegister<u32>For interrupts ID
GICD_ISACTIVER1: RWRegister<u32>For interrupts ID
GICD_ISACTIVER2: RWRegister<u32>For interrupts ID
GICD_ISACTIVER3: RWRegister<u32>For interrupts ID
GICD_ISACTIVER4: RWRegister<u32>For interrupts ID
GICD_ISACTIVER5: RWRegister<u32>For interrupts ID
GICD_ISACTIVER6: RWRegister<u32>For interrupts ID
GICD_ISACTIVER7: RWRegister<u32>For interrupts ID
GICD_ISACTIVER8: RWRegister<u32>For interrupts ID
GICD_ICACTIVER0: RWRegister<u32>For interrupts ID
GICD_ICACTIVER1: RWRegister<u32>For interrupts ID
GICD_ICACTIVER2: RWRegister<u32>For interrupts ID
GICD_ICACTIVER3: RWRegister<u32>For interrupts ID
GICD_ICACTIVER4: RWRegister<u32>For interrupts ID
GICD_ICACTIVER5: RWRegister<u32>For interrupts ID
GICD_ICACTIVER6: RWRegister<u32>For interrupts ID
GICD_ICACTIVER7: RWRegister<u32>For interrupts ID
GICD_ICACTIVER8: RWRegister<u32>For interrupts ID
GICD_IPRIORITYR0: RWRegister<u32>GICD interrupt priority register 0
GICD_IPRIORITYR1: RWRegister<u32>GICD interrupt priority register 1
GICD_IPRIORITYR2: RWRegister<u32>GICD interrupt priority register 2
GICD_IPRIORITYR3: RWRegister<u32>GICD interrupt priority register 3
GICD_IPRIORITYR4: RWRegister<u32>GICD interrupt priority register 4
GICD_IPRIORITYR5: RWRegister<u32>GICD interrupt priority register 5
GICD_IPRIORITYR6: RWRegister<u32>GICD interrupt priority register 6
GICD_IPRIORITYR7: RWRegister<u32>GICD interrupt priority register 7
GICD_IPRIORITYR8: RWRegister<u32>GICD interrupt priority register 8
GICD_IPRIORITYR9: RWRegister<u32>GICD interrupt priority register 9
GICD_IPRIORITYR10: RWRegister<u32>GICD interrupt priority register 10
GICD_IPRIORITYR11: RWRegister<u32>GICD interrupt priority register 11
GICD_IPRIORITYR12: RWRegister<u32>GICD interrupt priority register 12
GICD_IPRIORITYR13: RWRegister<u32>GICD interrupt priority register 13
GICD_IPRIORITYR14: RWRegister<u32>GICD interrupt priority register 14
GICD_IPRIORITYR15: RWRegister<u32>GICD interrupt priority register 15
GICD_IPRIORITYR16: RWRegister<u32>GICD interrupt priority register 16
GICD_IPRIORITYR17: RWRegister<u32>GICD interrupt priority register 17
GICD_IPRIORITYR18: RWRegister<u32>GICD interrupt priority register 18
GICD_IPRIORITYR19: RWRegister<u32>GICD interrupt priority register 19
GICD_IPRIORITYR20: RWRegister<u32>GICD interrupt priority register 20
GICD_IPRIORITYR21: RWRegister<u32>GICD interrupt priority register 21
GICD_IPRIORITYR22: RWRegister<u32>GICD interrupt priority register 22
GICD_IPRIORITYR23: RWRegister<u32>GICD interrupt priority register 23
GICD_IPRIORITYR24: RWRegister<u32>GICD interrupt priority register 24
GICD_IPRIORITYR25: RWRegister<u32>GICD interrupt priority register 25
GICD_IPRIORITYR26: RWRegister<u32>GICD interrupt priority register 26
GICD_IPRIORITYR27: RWRegister<u32>GICD interrupt priority register 27
GICD_IPRIORITYR28: RWRegister<u32>GICD interrupt priority register 28
GICD_IPRIORITYR29: RWRegister<u32>GICD interrupt priority register 29
GICD_IPRIORITYR30: RWRegister<u32>GICD interrupt priority register 30
GICD_IPRIORITYR31: RWRegister<u32>GICD interrupt priority register 31
GICD_IPRIORITYR32: RWRegister<u32>GICD interrupt priority register 32
GICD_IPRIORITYR33: RWRegister<u32>GICD interrupt priority register 33
GICD_IPRIORITYR34: RWRegister<u32>GICD interrupt priority register 34
GICD_IPRIORITYR35: RWRegister<u32>GICD interrupt priority register 35
GICD_IPRIORITYR36: RWRegister<u32>GICD interrupt priority register 36
GICD_IPRIORITYR37: RWRegister<u32>GICD interrupt priority register 37
GICD_IPRIORITYR38: RWRegister<u32>GICD interrupt priority register 38
GICD_IPRIORITYR39: RWRegister<u32>GICD interrupt priority register 39
GICD_IPRIORITYR40: RWRegister<u32>GICD interrupt priority register 40
GICD_IPRIORITYR41: RWRegister<u32>GICD interrupt priority register 41
GICD_IPRIORITYR42: RWRegister<u32>GICD interrupt priority register 42
GICD_IPRIORITYR43: RWRegister<u32>GICD interrupt priority register 43
GICD_IPRIORITYR44: RWRegister<u32>GICD interrupt priority register 44
GICD_IPRIORITYR45: RWRegister<u32>GICD interrupt priority register 45
GICD_IPRIORITYR46: RWRegister<u32>GICD interrupt priority register 46
GICD_IPRIORITYR47: RWRegister<u32>GICD interrupt priority register 47
GICD_IPRIORITYR48: RWRegister<u32>GICD interrupt priority register 48
GICD_IPRIORITYR49: RWRegister<u32>GICD interrupt priority register 49
GICD_IPRIORITYR50: RWRegister<u32>GICD interrupt priority register 50
GICD_IPRIORITYR51: RWRegister<u32>GICD interrupt priority register 51
GICD_IPRIORITYR52: RWRegister<u32>GICD interrupt priority register 52
GICD_IPRIORITYR53: RWRegister<u32>GICD interrupt priority register 53
GICD_IPRIORITYR54: RWRegister<u32>GICD interrupt priority register 54
GICD_IPRIORITYR55: RWRegister<u32>GICD interrupt priority register 55
GICD_IPRIORITYR56: RWRegister<u32>GICD interrupt priority register 56
GICD_IPRIORITYR57: RWRegister<u32>GICD interrupt priority register 57
GICD_IPRIORITYR58: RWRegister<u32>GICD interrupt priority register 58
GICD_IPRIORITYR59: RWRegister<u32>GICD interrupt priority register 59
GICD_IPRIORITYR60: RWRegister<u32>GICD interrupt priority register 60
GICD_IPRIORITYR61: RWRegister<u32>GICD interrupt priority register 61
GICD_IPRIORITYR62: RWRegister<u32>GICD interrupt priority register 62
GICD_IPRIORITYR63: RWRegister<u32>GICD interrupt priority register 63
GICD_IPRIORITYR64: RWRegister<u32>GICD interrupt priority register 64
GICD_IPRIORITYR65: RWRegister<u32>GICD interrupt priority register 65
GICD_IPRIORITYR66: RWRegister<u32>GICD interrupt priority register 66
GICD_IPRIORITYR67: RWRegister<u32>GICD interrupt priority register 67
GICD_IPRIORITYR68: RWRegister<u32>GICD interrupt priority register 68
GICD_IPRIORITYR69: RWRegister<u32>GICD interrupt priority register 69
GICD_IPRIORITYR70: RWRegister<u32>GICD interrupt priority register 70
GICD_IPRIORITYR71: RWRegister<u32>GICD interrupt priority register 71
GICD_ITARGETSR0: RORegister<u32>For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
GICD_ITARGETSR1: RORegister<u32>For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
GICD_ITARGETSR2: RORegister<u32>For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
GICD_ITARGETSR3: RORegister<u32>For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
GICD_ITARGETSR4: RORegister<u32>For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
GICD_ITARGETSR5: RORegister<u32>For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
GICD_ITARGETSR6: RORegister<u32>For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
GICD_ITARGETSR7: RORegister<u32>For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
GICD_ITARGETSR8: RWRegister<u32>GICD interrupt processor target register 8
GICD_ITARGETSR9: RWRegister<u32>GICD interrupt processor target register 9
GICD_ITARGETSR10: RWRegister<u32>GICD interrupt processor target register 10
GICD_ITARGETSR11: RWRegister<u32>GICD interrupt processor target register 11
GICD_ITARGETSR12: RWRegister<u32>GICD interrupt processor target register 12
GICD_ITARGETSR13: RWRegister<u32>GICD interrupt processor target register 13
GICD_ITARGETSR14: RWRegister<u32>GICD interrupt processor target register 14
GICD_ITARGETSR15: RWRegister<u32>GICD interrupt processor target register 15
GICD_ITARGETSR16: RWRegister<u32>GICD interrupt processor target register 16
GICD_ITARGETSR17: RWRegister<u32>GICD interrupt processor target register 17
GICD_ITARGETSR18: RWRegister<u32>GICD interrupt processor target register 18
GICD_ITARGETSR19: RWRegister<u32>GICD interrupt processor target register 19
GICD_ITARGETSR20: RWRegister<u32>GICD interrupt processor target register 20
GICD_ITARGETSR21: RWRegister<u32>GICD interrupt processor target register 21
GICD_ITARGETSR22: RWRegister<u32>GICD interrupt processor target register 22
GICD_ITARGETSR23: RWRegister<u32>GICD interrupt processor target register 23
GICD_ITARGETSR24: RWRegister<u32>GICD interrupt processor target register 24
GICD_ITARGETSR25: RWRegister<u32>GICD interrupt processor target register 25
GICD_ITARGETSR26: RWRegister<u32>GICD interrupt processor target register 26
GICD_ITARGETSR27: RWRegister<u32>GICD interrupt processor target register 27
GICD_ITARGETSR28: RWRegister<u32>GICD interrupt processor target register 28
GICD_ITARGETSR29: RWRegister<u32>GICD interrupt processor target register 29
GICD_ITARGETSR30: RWRegister<u32>GICD interrupt processor target register 30
GICD_ITARGETSR31: RWRegister<u32>GICD interrupt processor target register 31
GICD_ITARGETSR32: RWRegister<u32>GICD interrupt processor target register 32
GICD_ITARGETSR33: RWRegister<u32>GICD interrupt processor target register 33
GICD_ITARGETSR34: RWRegister<u32>GICD interrupt processor target register 34
GICD_ITARGETSR35: RWRegister<u32>GICD interrupt processor target register 35
GICD_ITARGETSR36: RWRegister<u32>GICD interrupt processor target register 36
GICD_ITARGETSR37: RWRegister<u32>GICD interrupt processor target register 37
GICD_ITARGETSR38: RWRegister<u32>GICD interrupt processor target register 38
GICD_ITARGETSR39: RWRegister<u32>GICD interrupt processor target register 39
GICD_ITARGETSR40: RWRegister<u32>GICD interrupt processor target register 40
GICD_ITARGETSR41: RWRegister<u32>GICD interrupt processor target register 41
GICD_ITARGETSR42: RWRegister<u32>GICD interrupt processor target register 42
GICD_ITARGETSR43: RWRegister<u32>GICD interrupt processor target register 43
GICD_ITARGETSR44: RWRegister<u32>GICD interrupt processor target register 44
GICD_ITARGETSR45: RWRegister<u32>GICD interrupt processor target register 45
GICD_ITARGETSR46: RWRegister<u32>GICD interrupt processor target register 46
GICD_ITARGETSR47: RWRegister<u32>GICD interrupt processor target register 47
GICD_ITARGETSR48: RWRegister<u32>GICD interrupt processor target register 48
GICD_ITARGETSR49: RWRegister<u32>GICD interrupt processor target register 49
GICD_ITARGETSR50: RWRegister<u32>GICD interrupt processor target register 50
GICD_ITARGETSR51: RWRegister<u32>GICD interrupt processor target register 51
GICD_ITARGETSR52: RWRegister<u32>GICD interrupt processor target register 52
GICD_ITARGETSR53: RWRegister<u32>GICD interrupt processor target register 53
GICD_ITARGETSR54: RWRegister<u32>GICD interrupt processor target register 54
GICD_ITARGETSR55: RWRegister<u32>GICD interrupt processor target register 55
GICD_ITARGETSR56: RWRegister<u32>GICD interrupt processor target register 56
GICD_ITARGETSR57: RWRegister<u32>GICD interrupt processor target register 57
GICD_ITARGETSR58: RWRegister<u32>GICD interrupt processor target register 58
GICD_ITARGETSR59: RWRegister<u32>GICD interrupt processor target register 59
GICD_ITARGETSR60: RWRegister<u32>GICD interrupt processor target register 60
GICD_ITARGETSR61: RWRegister<u32>GICD interrupt processor target register 61
GICD_ITARGETSR62: RWRegister<u32>GICD interrupt processor target register 62
GICD_ITARGETSR63: RWRegister<u32>GICD interrupt processor target register 63
GICD_ITARGETSR64: RWRegister<u32>GICD interrupt processor target register 64
GICD_ITARGETSR65: RWRegister<u32>GICD interrupt processor target register 65
GICD_ITARGETSR66: RWRegister<u32>GICD interrupt processor target register 66
GICD_ITARGETSR67: RWRegister<u32>GICD interrupt processor target register 67
GICD_ITARGETSR68: RWRegister<u32>GICD interrupt processor target register 68
GICD_ITARGETSR69: RWRegister<u32>GICD interrupt processor target register 69
GICD_ITARGETSR70: RWRegister<u32>GICD interrupt processor target register 70
GICD_ITARGETSR71: RWRegister<u32>GICD interrupt processor target register 71
GICD_ICFGR0: RWRegister<u32>GICD interrupt configuration register
GICD_ICFGR1: RWRegister<u32>GICD interrupt configuration register
GICD_ICFGR2: RWRegister<u32>GICD interrupt configuration register 2
GICD_ICFGR3: RWRegister<u32>GICD interrupt configuration register 3
GICD_ICFGR4: RWRegister<u32>GICD interrupt configuration register 4
GICD_ICFGR5: RWRegister<u32>GICD interrupt configuration register 5
GICD_ICFGR6: RWRegister<u32>GICD interrupt configuration register 6
GICD_ICFGR7: RWRegister<u32>GICD interrupt configuration register 7
GICD_ICFGR8: RWRegister<u32>GICD interrupt configuration register 8
GICD_ICFGR9: RWRegister<u32>GICD interrupt configuration register 9
GICD_ICFGR10: RWRegister<u32>GICD interrupt configuration register 10
GICD_ICFGR11: RWRegister<u32>GICD interrupt configuration register 11
GICD_ICFGR12: RWRegister<u32>GICD interrupt configuration register 12
GICD_ICFGR13: RWRegister<u32>GICD interrupt configuration register 13
GICD_ICFGR14: RWRegister<u32>GICD interrupt configuration register 14
GICD_ICFGR15: RWRegister<u32>GICD interrupt configuration register 15
GICD_ICFGR16: RWRegister<u32>GICD interrupt configuration register 16
GICD_ICFGR17: RWRegister<u32>GICD interrupt configuration register 17
GICD_PPISR: RORegister<u32>GICD private peripheral interrupt status register
GICD_SPISR1: RORegister<u32>For interrupts ID = SPI number+32, from SPI [x32+31] to SPI [x32]
GICD_SPISR2: RORegister<u32>For interrupts ID
GICD_SPISR3: RORegister<u32>For interrupts ID
GICD_SPISR4: RORegister<u32>For interrupts ID
GICD_SPISR5: RORegister<u32>For interrupts ID
GICD_SPISR6: RORegister<u32>For interrupts ID
GICD_SPISR7: RORegister<u32>For interrupts ID
GICD_SGIR: WORegister<u32>GICD software generated interrupt register
GICD_CPENDSGIR0: RWRegister<u32>For SGI x4 to SGI x4+3
GICD_CPENDSGIR1: RWRegister<u32>For SGI x4 to SGI x4+3
GICD_CPENDSGIR2: RWRegister<u32>For SGI x4 to SGI x4+3
GICD_CPENDSGIR3: RWRegister<u32>For SGI x4 to SGI x4+3
GICD_SPENDSGIR0: RWRegister<u32>For SGI x4 to SGI x4+3
GICD_SPENDSGIR1: RWRegister<u32>For SGI x4 to SGI x4+3
GICD_SPENDSGIR2: RWRegister<u32>For SGI x4 to SGI x4+3
GICD_SPENDSGIR3: RWRegister<u32>For SGI x4 to SGI x4+3
GICD_PIDR4: RORegister<u32>GICD peripheral ID4 register
GICD_PIDR5: RORegister<u32>GICD peripheral ID5 to ID7 register 5
GICD_PIDR6: RORegister<u32>GICD peripheral ID5 to ID7 register 6
GICD_PIDR7: RORegister<u32>GICD peripheral ID5 to ID7 register 7
GICD_PIDR0: RORegister<u32>GICD peripheral ID0 register
GICD_PIDR1: RORegister<u32>GICD peripheral ID1 register
GICD_PIDR2: RORegister<u32>GICD peripheral ID2 register
GICD_PIDR3: RORegister<u32>GICD peripheral ID3 register
GICD_CIDR0: RORegister<u32>GICD component ID0 register
GICD_CIDR1: RORegister<u32>GICD component ID1 register
GICD_CIDR2: RORegister<u32>GICD component ID2 register
GICD_CIDR3: RORegister<u32>GICD component ID3 register