Struct stm32ral::stm32mp::peripherals::gicc::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub GICC_CTLR: RWRegister<u32>,
    pub GICC_PMR: RWRegister<u32>,
    pub GICC_BPR: RWRegister<u32>,
    pub GICC_IAR: RORegister<u32>,
    pub GICC_EOIR: WORegister<u32>,
    pub GICC_RPR: RORegister<u32>,
    pub GICC_HPPIR: RORegister<u32>,
    pub GICC_ABPR: RWRegister<u32>,
    pub GICC_AIAR: RORegister<u32>,
    pub GICC_AEOIR: WORegister<u32>,
    pub GICC_AHPPIR: RORegister<u32>,
    pub GICC_APR0: RWRegister<u32>,
    pub GICC_NSAPR0: RWRegister<u32>,
    pub GICC_IIDR: RORegister<u32>,
    pub GICC_DIR: WORegister<u32>,
    // some fields omitted
}

Fields

GICC_CTLR: RWRegister<u32>

GICC control register

GICC_PMR: RWRegister<u32>

GICC input priority mask register

GICC_BPR: RWRegister<u32>

GICC binary point register

GICC_IAR: RORegister<u32>

GICC interrupt acknowledge register

GICC_EOIR: WORegister<u32>

GICC end of interrupt register

GICC_RPR: RORegister<u32>

GICC running priority register

GICC_HPPIR: RORegister<u32>

GICC highest priority pending interrupt register

GICC_ABPR: RWRegister<u32>

GICC_ABPR is an alias of the non-secure GICC_BPR. When GICC_CTLR.CBPR is set to 0, a secure access to this register is equivalent to a non-secure access to GICC_BPR.

GICC_AIAR: RORegister<u32>

GICC_AIAR is an alias of the non-secure view of GICC_IAR. A secure access to this register is identical to a non-secure access to GICC_IAR.

GICC_AEOIR: WORegister<u32>

GICC_AEOIR is an alias of the Non-secure GICC_EOIR. A secure access to this register is similar to a non-secure access to GICC_EOIR, except that the GICC_CTLR.EOImodeS bit is used.

GICC_AHPPIR: RORegister<u32>

ICC_AHPPIR is an alias of the non-secure GICC_HPPIR. A secure access to this register is equivalent to a non-secure access to GICC_HPPIR.

GICC_APR0: RWRegister<u32>

GICC active priority register

GICC_NSAPR0: RWRegister<u32>

GICC non-secure active priority register

GICC_IIDR: RORegister<u32>

GICC interface identification register

GICC_DIR: WORegister<u32>

GICC deactivate interrupt register