Struct stm32ral::stm32mp::peripherals::eth_mac_mmc::ResetValues[−][src]

pub struct ResetValues {Show 95 fields
    pub ETH_MACCR: u32,
    pub ETH_MACECR: u32,
    pub ETH_MACPFR: u32,
    pub ETH_MACWTR: u32,
    pub ETH_MACHT0R: u32,
    pub ETH_MACHT1R: u32,
    pub ETH_MACVTR: u32,
    pub ETH_MACVHTR: u32,
    pub ETH_MACVIR: u32,
    pub ETH_MACIVIR: u32,
    pub ETH_MACQ0TxFCR: u32,
    pub ETH_MACRxFCR: u32,
    pub ETH_MACTxQPMR: u32,
    pub ETH_MACRxQC0R: u32,
    pub ETH_MACRxQC1R: u32,
    pub ETH_MACRxQC2R: u32,
    pub ETH_MACISR: u32,
    pub ETH_MACIER: u32,
    pub ETH_MACRxTxSR: u32,
    pub ETH_MACPCSR: u32,
    pub ETH_MACRWKPFR: u32,
    pub ETH_MACLCSR: u32,
    pub ETH_MACLTCR: u32,
    pub ETH_MACLETR: u32,
    pub ETH_MAC1USTCR: u32,
    pub ETH_MACPHYCSR: u32,
    pub ETH_MACVR: u32,
    pub ETH_MACDR: u32,
    pub ETH_MACHWF1R: u32,
    pub ETH_MACHWF2R: u32,
    pub ETH_MACMDIOAR: u32,
    pub ETH_MACMDIODR: u32,
    pub ETH_MACA0HR: u32,
    pub ETH_MACA0LR: u32,
    pub ETH_MACA1HR: u32,
    pub ETH_MACA1LR: u32,
    pub ETH_MACA2HR: u32,
    pub ETH_MACA2LR: u32,
    pub ETH_MACA3HR: u32,
    pub ETH_MACA3LR: u32,
    pub MMC_CONTROL: u32,
    pub MMC_RX_INTERRUPT: u32,
    pub MMC_TX_INTERRUPT: u32,
    pub MMC_RX_INTERRUPT_MASK: u32,
    pub MMC_TX_INTERRUPT_MASK: u32,
    pub TX_SINGLE_COLLISION_GOOD_PACKETS: u32,
    pub TX_MULTIPLE_COLLISION_GOOD_PACKETS: u32,
    pub TX_PACKET_COUNT_GOOD: u32,
    pub RX_CRC_ERROR_PACKETS: u32,
    pub RX_ALIGNMENT_ERROR_PACKETS: u32,
    pub RX_UNICAST_PACKETS_GOOD: u32,
    pub TX_LPI_USEC_CNTR: u32,
    pub TX_LPI_TRAN_CNTR: u32,
    pub RX_LPI_USEC_CNTR: u32,
    pub RX_LPI_TRAN_CNTR: u32,
    pub ETH_MACL3L4C0R: u32,
    pub ETH_MACL4A0R: u32,
    pub ETH_MACL3A00R: u32,
    pub ETH_MACL3A10R: u32,
    pub ETH_MACL3A20: u32,
    pub ETH_MACL3A30: u32,
    pub ETH_MACL3L4C1R: u32,
    pub ETH_MACL4A1R: u32,
    pub ETH_MACL3A01R: u32,
    pub ETH_MACL3A11R: u32,
    pub ETH_MACL3A21R: u32,
    pub ETH_MACL3A31R: u32,
    pub ETH_MACARPAR: u32,
    pub ETH_MACTSCR: u32,
    pub ETH_MACSSIR: u32,
    pub ETH_MACSTSR: u32,
    pub ETH_MACSTNR: u32,
    pub ETH_MACSTSUR: u32,
    pub ETH_MACSTNUR: u32,
    pub ETH_MACTSAR: u32,
    pub ETH_MACTSSR: u32,
    pub ETH_MACTxTSSNR: u32,
    pub ETH_MACTxTSSSR: u32,
    pub ETH_MACACR: u32,
    pub ETH_MACATSNR: u32,
    pub ETH_MACATSSR: u32,
    pub ETH_MACTSIACR: u32,
    pub ETH_MACTSEACR: u32,
    pub ETH_MACTSICNR: u32,
    pub ETH_MACTSECNR: u32,
    pub ETH_MACPPSCR: u32,
    pub ETH_MACPPSTTSR: u32,
    pub ETH_MACPPSTTNR: u32,
    pub ETH_MACPPSIR: u32,
    pub ETH_MACPPSWR: u32,
    pub ETH_MACPOCR: u32,
    pub ETH_MACSPI0R: u32,
    pub ETH_MACSPI1R: u32,
    pub ETH_MACSPI2R: u32,
    pub ETH_MACLMIR: u32,
}

Fields

ETH_MACCR: u32ETH_MACECR: u32ETH_MACPFR: u32ETH_MACWTR: u32ETH_MACHT0R: u32ETH_MACHT1R: u32ETH_MACVTR: u32ETH_MACVHTR: u32ETH_MACVIR: u32ETH_MACIVIR: u32ETH_MACQ0TxFCR: u32ETH_MACRxFCR: u32ETH_MACTxQPMR: u32ETH_MACRxQC0R: u32ETH_MACRxQC1R: u32ETH_MACRxQC2R: u32ETH_MACISR: u32ETH_MACIER: u32ETH_MACRxTxSR: u32ETH_MACPCSR: u32ETH_MACRWKPFR: u32ETH_MACLCSR: u32ETH_MACLTCR: u32ETH_MACLETR: u32ETH_MAC1USTCR: u32ETH_MACPHYCSR: u32ETH_MACVR: u32ETH_MACDR: u32ETH_MACHWF1R: u32ETH_MACHWF2R: u32ETH_MACMDIOAR: u32ETH_MACMDIODR: u32ETH_MACA0HR: u32ETH_MACA0LR: u32ETH_MACA1HR: u32ETH_MACA1LR: u32ETH_MACA2HR: u32ETH_MACA2LR: u32ETH_MACA3HR: u32ETH_MACA3LR: u32MMC_CONTROL: u32MMC_RX_INTERRUPT: u32MMC_TX_INTERRUPT: u32MMC_RX_INTERRUPT_MASK: u32MMC_TX_INTERRUPT_MASK: u32TX_SINGLE_COLLISION_GOOD_PACKETS: u32TX_MULTIPLE_COLLISION_GOOD_PACKETS: u32TX_PACKET_COUNT_GOOD: u32RX_CRC_ERROR_PACKETS: u32RX_ALIGNMENT_ERROR_PACKETS: u32RX_UNICAST_PACKETS_GOOD: u32TX_LPI_USEC_CNTR: u32TX_LPI_TRAN_CNTR: u32RX_LPI_USEC_CNTR: u32RX_LPI_TRAN_CNTR: u32ETH_MACL3L4C0R: u32ETH_MACL4A0R: u32ETH_MACL3A00R: u32ETH_MACL3A10R: u32ETH_MACL3A20: u32ETH_MACL3A30: u32ETH_MACL3L4C1R: u32ETH_MACL4A1R: u32ETH_MACL3A01R: u32ETH_MACL3A11R: u32ETH_MACL3A21R: u32ETH_MACL3A31R: u32ETH_MACARPAR: u32ETH_MACTSCR: u32ETH_MACSSIR: u32ETH_MACSTSR: u32ETH_MACSTNR: u32ETH_MACSTSUR: u32ETH_MACSTNUR: u32ETH_MACTSAR: u32ETH_MACTSSR: u32ETH_MACTxTSSNR: u32ETH_MACTxTSSSR: u32ETH_MACACR: u32ETH_MACATSNR: u32ETH_MACATSSR: u32ETH_MACTSIACR: u32ETH_MACTSEACR: u32ETH_MACTSICNR: u32ETH_MACTSECNR: u32ETH_MACPPSCR: u32ETH_MACPPSTTSR: u32ETH_MACPPSTTNR: u32ETH_MACPPSIR: u32ETH_MACPPSWR: u32ETH_MACPOCR: u32ETH_MACSPI0R: u32ETH_MACSPI1R: u32ETH_MACSPI2R: u32ETH_MACLMIR: u32