pub struct ResetValues {Show 142 fields
pub DFSDM_CH0CFGR1: u32,
pub DFSDM_CH0CFGR2: u32,
pub DFSDM_CH0AWSCDR: u32,
pub DFSDM_CH0WDATR: u32,
pub DFSDM_CH0DATINR: u32,
pub DFSDM_CH0DLYR: u32,
pub DFSDM_CH1CFGR1: u32,
pub DFSDM_CH1CFGR2: u32,
pub DFSDM_CH1AWSCDR: u32,
pub DFSDM_CH1WDATR: u32,
pub DFSDM_CH1DATINR: u32,
pub DFSDM_CH1DLYR: u32,
pub DFSDM_CH2CFGR1: u32,
pub DFSDM_CH2CFGR2: u32,
pub DFSDM_CH2AWSCDR: u32,
pub DFSDM_CH2WDATR: u32,
pub DFSDM_CH2DATINR: u32,
pub DFSDM_CH2DLYR: u32,
pub DFSDM_CH3CFGR1: u32,
pub DFSDM_CH3CFGR2: u32,
pub DFSDM_CH3AWSCDR: u32,
pub DFSDM_CH3WDATR: u32,
pub DFSDM_CH3DATINR: u32,
pub DFSDM_CH3DLYR: u32,
pub DFSDM_CH4CFGR1: u32,
pub DFSDM_CH4CFGR2: u32,
pub DFSDM_CH4AWSCDR: u32,
pub DFSDM_CH4WDATR: u32,
pub DFSDM_CH4DATINR: u32,
pub DFSDM_CH4DLYR: u32,
pub DFSDM_CH5CFGR1: u32,
pub DFSDM_CH5CFGR2: u32,
pub DFSDM_CH5AWSCDR: u32,
pub DFSDM_CH5WDATR: u32,
pub DFSDM_CH5DATINR: u32,
pub DFSDM_CH5DLYR: u32,
pub DFSDM_CH6CFGR1: u32,
pub DFSDM_CH6CFGR2: u32,
pub DFSDM_CH6AWSCDR: u32,
pub DFSDM_CH6WDATR: u32,
pub DFSDM_CH6DATINR: u32,
pub DFSDM_CH6DLYR: u32,
pub DFSDM_CH7CFGR1: u32,
pub DFSDM_CH7CFGR2: u32,
pub DFSDM_CH7AWSCDR: u32,
pub DFSDM_CH7WDATR: u32,
pub DFSDM_CH7DATINR: u32,
pub DFSDM_CH7DLYR: u32,
pub DFSDM_FLT0CR1: u32,
pub DFSDM_FLT0CR2: u32,
pub DFSDM_FLT0ISR: u32,
pub DFSDM_FLT0ICR: u32,
pub DFSDM_FLT0JCHGR: u32,
pub DFSDM_FLT0FCR: u32,
pub DFSDM_FLT0JDATAR: u32,
pub DFSDM_FLT0RDATAR: u32,
pub DFSDM_FLT0AWHTR: u32,
pub DFSDM_FLT0AWLTR: u32,
pub DFSDM_FLT0AWSR: u32,
pub DFSDM_FLT0AWCFR: u32,
pub DFSDM_FLT0EXMAX: u32,
pub DFSDM_FLT0EXMIN: u32,
pub DFSDM_FLT0CNVTIMR: u32,
pub DFSDM_FLT1CR1: u32,
pub DFSDM_FLT1CR2: u32,
pub DFSDM_FLT1ISR: u32,
pub DFSDM_FLT1ICR: u32,
pub DFSDM_FLT1JCHGR: u32,
pub DFSDM_FLT1FCR: u32,
pub DFSDM_FLT1JDATAR: u32,
pub DFSDM_FLT1RDATAR: u32,
pub DFSDM_FLT1AWHTR: u32,
pub DFSDM_FLT1AWLTR: u32,
pub DFSDM_FLT1AWSR: u32,
pub DFSDM_FLT1AWCFR: u32,
pub DFSDM_FLT1EXMAX: u32,
pub DFSDM_FLT1EXMIN: u32,
pub DFSDM_FLT1CNVTIMR: u32,
pub DFSDM_FLT2CR1: u32,
pub DFSDM_FLT2CR2: u32,
pub DFSDM_FLT2ISR: u32,
pub DFSDM_FLT2ICR: u32,
pub DFSDM_FLT2JCHGR: u32,
pub DFSDM_FLT2FCR: u32,
pub DFSDM_FLT2JDATAR: u32,
pub DFSDM_FLT2RDATAR: u32,
pub DFSDM_FLT2AWHTR: u32,
pub DFSDM_FLT2AWLTR: u32,
pub DFSDM_FLT2AWSR: u32,
pub DFSDM_FLT2AWCFR: u32,
pub DFSDM_FLT2EXMAX: u32,
pub DFSDM_FLT2EXMIN: u32,
pub DFSDM_FLT2CNVTIMR: u32,
pub DFSDM_FLT3CR1: u32,
pub DFSDM_FLT3CR2: u32,
pub DFSDM_FLT3ISR: u32,
pub DFSDM_FLT3ICR: u32,
pub DFSDM_FLT3JCHGR: u32,
pub DFSDM_FLT3FCR: u32,
pub DFSDM_FLT3JDATAR: u32,
pub DFSDM_FLT3RDATAR: u32,
pub DFSDM_FLT3AWHTR: u32,
pub DFSDM_FLT3AWLTR: u32,
pub DFSDM_FLT3AWSR: u32,
pub DFSDM_FLT3AWCFR: u32,
pub DFSDM_FLT3EXMAX: u32,
pub DFSDM_FLT3EXMIN: u32,
pub DFSDM_FLT3CNVTIMR: u32,
pub DFSDM_FLT4CR1: u32,
pub DFSDM_FLT4CR2: u32,
pub DFSDM_FLT4ISR: u32,
pub DFSDM_FLT4ICR: u32,
pub DFSDM_FLT4JCHGR: u32,
pub DFSDM_FLT4FCR: u32,
pub DFSDM_FLT4JDATAR: u32,
pub DFSDM_FLT4RDATAR: u32,
pub DFSDM_FLT4AWHTR: u32,
pub DFSDM_FLT4AWLTR: u32,
pub DFSDM_FLT4AWSR: u32,
pub DFSDM_FLT4AWCFR: u32,
pub DFSDM_FLT4EXMAX: u32,
pub DFSDM_FLT4EXMIN: u32,
pub DFSDM_FLT4CNVTIMR: u32,
pub DFSDM_FLT5CR1: u32,
pub DFSDM_FLT5CR2: u32,
pub DFSDM_FLT5ISR: u32,
pub DFSDM_FLT5ICR: u32,
pub DFSDM_FLT5JCHGR: u32,
pub DFSDM_FLT5FCR: u32,
pub DFSDM_FLT5JDATAR: u32,
pub DFSDM_FLT5RDATAR: u32,
pub DFSDM_FLT5AWHTR: u32,
pub DFSDM_FLT5AWLTR: u32,
pub DFSDM_FLT5AWSR: u32,
pub DFSDM_FLT5AWCFR: u32,
pub DFSDM_FLT5EXMAX: u32,
pub DFSDM_FLT5EXMIN: u32,
pub DFSDM_FLT5CNVTIMR: u32,
pub DFSDM_HWCFGR: u32,
pub DFSDM_VERR: u32,
pub DFSDM_IPIDR: u32,
pub DFSDM_SIDR: u32,