Struct stm32ral::stm32mp::peripherals::ddrphyc::ResetValues[−][src]

pub struct ResetValues {Show 54 fields
    pub DDRPHYC_RIDR: u32,
    pub DDRPHYC_PIR: u32,
    pub DDRPHYC_PGCR: u32,
    pub DDRPHYC_PGSR: u32,
    pub DDRPHYC_DLLGCR: u32,
    pub DDRPHYC_ACDLLCR: u32,
    pub DDRPHYC_PTR0: u32,
    pub DDRPHYC_PTR1: u32,
    pub DDRPHYC_PTR2: u32,
    pub DDRPHYC_ACIOCR: u32,
    pub DDRPHYC_DXCCR: u32,
    pub DDRPHYC_DSGCR: u32,
    pub DDRPHYC_DCR: u32,
    pub DDRPHYC_DTPR0: u32,
    pub DDRPHYC_DTPR1: u32,
    pub DDRPHYC_DTPR2: u32,
    pub DDRPHYC_DDR3_MR0: u16,
    pub DDRPHYC_DDR3_MR1: u16,
    pub DDRPHYC_DDR3_MR2: u16,
    pub DDRPHYC_DDR3_MR3: u8,
    pub DDRPHYC_ODTCR: u32,
    pub DDRPHYC_DTAR: u32,
    pub DDRPHYC_DTDR0: u32,
    pub DDRPHYC_DTDR1: u32,
    pub DDRPHYC_GPR0: u32,
    pub DDRPHYC_GPR1: u32,
    pub DDRPHYC_ZQ0CR0: u32,
    pub DDRPHYC_ZQ0CR1: u8,
    pub DDRPHYC_ZQ0SR0: u32,
    pub DDRPHYC_ZQ0SR1: u8,
    pub DDRPHYC_DX0GCR: u32,
    pub DDRPHYC_DX0GSR0: u16,
    pub DDRPHYC_DX0GSR1: u32,
    pub DDRPHYC_DX0DLLCR: u32,
    pub DDRPHYC_DX0DQTR: u32,
    pub DDRPHYC_DX0DQSTR: u32,
    pub DDRPHYC_DX1GCR: u32,
    pub DDRPHYC_DX1GSR0: u16,
    pub DDRPHYC_DX1GSR1: u32,
    pub DDRPHYC_DX1DLLCR: u32,
    pub DDRPHYC_DX1DQTR: u32,
    pub DDRPHYC_DX1DQSTR: u32,
    pub DDRPHYC_DX2GCR: u32,
    pub DDRPHYC_DX2GSR0: u16,
    pub DDRPHYC_DX2GSR1: u32,
    pub DDRPHYC_DX2DLLCR: u32,
    pub DDRPHYC_DX2DQTR: u32,
    pub DDRPHYC_DX2DQSTR: u32,
    pub DDRPHYC_DX3GCR: u32,
    pub DDRPHYC_DX3GSR0: u16,
    pub DDRPHYC_DX3GSR1: u32,
    pub DDRPHYC_DX3DLLCR: u32,
    pub DDRPHYC_DX3DQTR: u32,
    pub DDRPHYC_DX3DQSTR: u32,
}

Fields

DDRPHYC_RIDR: u32DDRPHYC_PIR: u32DDRPHYC_PGCR: u32DDRPHYC_PGSR: u32DDRPHYC_DLLGCR: u32DDRPHYC_ACDLLCR: u32DDRPHYC_PTR0: u32DDRPHYC_PTR1: u32DDRPHYC_PTR2: u32DDRPHYC_ACIOCR: u32DDRPHYC_DXCCR: u32DDRPHYC_DSGCR: u32DDRPHYC_DCR: u32DDRPHYC_DTPR0: u32DDRPHYC_DTPR1: u32DDRPHYC_DTPR2: u32DDRPHYC_DDR3_MR0: u16DDRPHYC_DDR3_MR1: u16DDRPHYC_DDR3_MR2: u16DDRPHYC_DDR3_MR3: u8DDRPHYC_ODTCR: u32DDRPHYC_DTAR: u32DDRPHYC_DTDR0: u32DDRPHYC_DTDR1: u32DDRPHYC_GPR0: u32DDRPHYC_GPR1: u32DDRPHYC_ZQ0CR0: u32DDRPHYC_ZQ0CR1: u8DDRPHYC_ZQ0SR0: u32DDRPHYC_ZQ0SR1: u8DDRPHYC_DX0GCR: u32DDRPHYC_DX0GSR0: u16DDRPHYC_DX0GSR1: u32DDRPHYC_DX0DLLCR: u32DDRPHYC_DX0DQTR: u32DDRPHYC_DX0DQSTR: u32DDRPHYC_DX1GCR: u32DDRPHYC_DX1GSR0: u16DDRPHYC_DX1GSR1: u32DDRPHYC_DX1DLLCR: u32DDRPHYC_DX1DQTR: u32DDRPHYC_DX1DQSTR: u32DDRPHYC_DX2GCR: u32DDRPHYC_DX2GSR0: u16DDRPHYC_DX2GSR1: u32DDRPHYC_DX2DLLCR: u32DDRPHYC_DX2DQTR: u32DDRPHYC_DX2DQSTR: u32DDRPHYC_DX3GCR: u32DDRPHYC_DX3GSR0: u16DDRPHYC_DX3GSR1: u32DDRPHYC_DX3DLLCR: u32DDRPHYC_DX3DQTR: u32DDRPHYC_DX3DQSTR: u32