Struct stm32ral::stm32mp::peripherals::dac1::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub DAC_CR: RWRegister<u32>,
    pub DAC_SWTRGR: WORegister<u32>,
    pub DAC_DHR12R1: RWRegister<u32>,
    pub DAC_DHR12L1: RWRegister<u32>,
    pub DAC_DHR8R1: RWRegister<u32>,
    pub DAC_DHR12R2: RWRegister<u32>,
    pub DAC_DHR12L2: RWRegister<u32>,
    pub DAC_DHR8R2: RWRegister<u32>,
    pub DAC_DHR12RD: RWRegister<u32>,
    pub DAC_DHR12LD: RWRegister<u32>,
    pub DAC_DHR8RD: RWRegister<u32>,
    pub DAC_DOR1: RORegister<u32>,
    pub DAC_DOR2: RORegister<u32>,
    pub DAC_SR: RWRegister<u32>,
    pub DAC_CCR: RWRegister<u32>,
    pub DAC_MCR: RWRegister<u32>,
    pub DAC_SHSR1: RWRegister<u32>,
    pub DAC_SHSR2: RWRegister<u32>,
    pub DAC_SHHR: RWRegister<u32>,
    pub DAC_SHRR: RWRegister<u32>,
    pub DAC_HWCFGR0: RORegister<u32>,
    pub DAC_VERR: RORegister<u32>,
    pub DAC_IPIDR: RORegister<u32>,
    pub DAC_SIDR: RORegister<u32>,
    // some fields omitted
}

Fields

DAC_CR: RWRegister<u32>

DAC control register

DAC_SWTRGR: WORegister<u32>

DAC software trigger register

DAC_DHR12R1: RWRegister<u32>

DAC channel1 12-bit right-aligned data holding register

DAC_DHR12L1: RWRegister<u32>

DAC channel1 12-bit left aligned data holding register

DAC_DHR8R1: RWRegister<u32>

DAC channel1 8-bit right aligned data holding register

DAC_DHR12R2: RWRegister<u32>

This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.

DAC_DHR12L2: RWRegister<u32>

This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.

DAC_DHR8R2: RWRegister<u32>

This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.

DAC_DHR12RD: RWRegister<u32>

Dual DAC 12-bit right-aligned data holding register

DAC_DHR12LD: RWRegister<u32>

Dual DAC 12-bit left aligned data holding register

DAC_DHR8RD: RWRegister<u32>

Dual DAC 8-bit right aligned data holding register

DAC_DOR1: RORegister<u32>

DAC channel1 data output register

DAC_DOR2: RORegister<u32>

This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.

DAC_SR: RWRegister<u32>

DAC status register

DAC_CCR: RWRegister<u32>

DAC calibration control register

DAC_MCR: RWRegister<u32>

DAC mode control register

DAC_SHSR1: RWRegister<u32>

DAC channel 1 sample and hold sample time register

DAC_SHSR2: RWRegister<u32>

This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.

DAC_SHHR: RWRegister<u32>

DAC sample and hold time register

DAC_SHRR: RWRegister<u32>

DAC sample and hold refresh time register

DAC_HWCFGR0: RORegister<u32>

DAC IP hardware configuration register

DAC_VERR: RORegister<u32>

No

DAC_IPIDR: RORegister<u32>

No

DAC_SIDR: RORegister<u32>

No