Struct stm32ral::stm32l5::peripherals::dfsdm1::RegisterBlock[][src]

#[repr(C)]
pub struct RegisterBlock {
Show 107 fields pub CH0CFGR1: RWRegister<u32>, pub CH0CFGR2: RWRegister<u32>, pub CH0AWSCDR: RWRegister<u32>, pub CH0WDATR: RWRegister<u32>, pub CH0DATINR: RWRegister<u32>, pub CH0DLYR: RWRegister<u32>, pub CH1CFGR1: RWRegister<u32>, pub CH1CFGR2: RWRegister<u32>, pub CH1AWSCDR: RWRegister<u32>, pub CH1WDATR: RWRegister<u32>, pub CH1DATINR: RWRegister<u32>, pub CH1DLYR: RWRegister<u32>, pub CH2CFGR1: RWRegister<u32>, pub CH2CFGR2: RWRegister<u32>, pub CH2AWSCDR: RWRegister<u32>, pub CH2WDATR: RWRegister<u32>, pub CH2DATINR: RWRegister<u32>, pub CH2DLYR: RWRegister<u32>, pub CH3CFGR1: RWRegister<u32>, pub CH3CFGR2: RWRegister<u32>, pub CH3AWSCDR: RWRegister<u32>, pub CH3WDATR: RWRegister<u32>, pub CH3DATINR: RWRegister<u32>, pub CH3DLYR: RWRegister<u32>, pub CH4CFGR1: RWRegister<u32>, pub CH4CFGR2: RWRegister<u32>, pub CH4AWSCDR: RWRegister<u32>, pub CH4WDATR: RWRegister<u32>, pub CH4DATINR: RWRegister<u32>, pub CH4DLYR: RWRegister<u32>, pub CH5CFGR1: RWRegister<u32>, pub CH5CFGR2: RWRegister<u32>, pub CH5AWSCDR: RWRegister<u32>, pub CH5WDATR: RWRegister<u32>, pub CH5DATINR: RWRegister<u32>, pub CH5DLYR: RWRegister<u32>, pub CH6CFGR1: RWRegister<u32>, pub CH6CFGR2: RWRegister<u32>, pub CH6AWSCDR: RWRegister<u32>, pub CH6WDATR: RWRegister<u32>, pub CH6DATINR: RWRegister<u32>, pub CH6DLYR: RWRegister<u32>, pub CH7CFGR1: RWRegister<u32>, pub CH7CFGR2: RWRegister<u32>, pub CH7AWSCDR: RWRegister<u32>, pub CH7WDATR: RWRegister<u32>, pub CH7DATINR: RWRegister<u32>, pub CH7DLYR: RWRegister<u32>, pub FLT0CR1: RWRegister<u32>, pub FLT0CR2: RWRegister<u32>, pub FLT0ISR: RORegister<u32>, pub FLT0ICR: RWRegister<u32>, pub FLT0JCHGR: RWRegister<u32>, pub FLT0FCR: RWRegister<u32>, pub FLT0JDATAR: RORegister<u32>, pub FLT0RDATAR: RORegister<u32>, pub FLT0AWHTR: RWRegister<u32>, pub FLT0AWLTR: RWRegister<u32>, pub FLT0AWSR: RORegister<u32>, pub FLT0AWCFR: RWRegister<u32>, pub FLT0EXMAX: RORegister<u32>, pub FLT0EXMIN: RORegister<u32>, pub FLT0CNVTIMR: RORegister<u32>, pub FLT1CR1: RWRegister<u32>, pub FLT1CR2: RWRegister<u32>, pub FLT1ISR: RORegister<u32>, pub FLT1ICR: RWRegister<u32>, pub FLT1JCHGR: RWRegister<u32>, pub FLT1FCR: RWRegister<u32>, pub FLT1JDATAR: RORegister<u32>, pub FLT1RDATAR: RORegister<u32>, pub FLT1AWLTR: RWRegister<u32>, pub FLT1AWSR: RORegister<u32>, pub FLT1AW: RWRegister<u32>, pub FLT1EXMAX: RORegister<u32>, pub FLT1EXMIN: RORegister<u32>, pub FLT1CNVTIMR: RORegister<u32>, pub FLT2CR1: RWRegister<u32>, pub FLT2CR2: RWRegister<u32>, pub FLT2ISR: RORegister<u32>, pub FLT2ICR: RWRegister<u32>, pub FLT2JCHGR: RWRegister<u32>, pub FLT2FCR: RWRegister<u32>, pub FLT2JDATAR: RORegister<u32>, pub FLT2RDATAR: RORegister<u32>, pub FLT2AWHTR: RWRegister<u32>, pub FLT2AWLTR: RWRegister<u32>, pub FLT2AWSR: RORegister<u32>, pub FLT2AWCFR: RWRegister<u32>, pub FLT2EXMAX: RORegister<u32>, pub FLT2EXMIN: RORegister<u32>, pub FLT2CNVTIMR: RORegister<u32>, pub FLT3CR1: RWRegister<u32>, pub FLT3CR2: RWRegister<u32>, pub FLT3ISR: RORegister<u32>, pub FLT3ICR: RWRegister<u32>, pub FLT3JCHGR: RWRegister<u32>, pub FLT3FCR: RWRegister<u32>, pub FLT3JDATAR: RORegister<u32>, pub FLT3RDATAR: RORegister<u32>, pub FLT3AWHTR: RWRegister<u32>, pub FLT3AWLTR: RWRegister<u32>, pub FLT3AWSR: RORegister<u32>, pub FLT3AWCFR: RWRegister<u32>, pub FLT3EXMAX: RORegister<u32>, pub FLT3EXMIN: RORegister<u32>, pub FLT3CNVTIMR: RORegister<u32>, // some fields omitted
}

Fields

CH0CFGR1: RWRegister<u32>

channel configuration y register

CH0CFGR2: RWRegister<u32>

channel configuration y register

CH0AWSCDR: RWRegister<u32>

analog watchdog and short-circuit detector register

CH0WDATR: RWRegister<u32>

channel watchdog filter data register

CH0DATINR: RWRegister<u32>

channel data input register

CH0DLYR: RWRegister<u32>

DFSDM channel y delay register

CH1CFGR1: RWRegister<u32>

CHCFG1R1

CH1CFGR2: RWRegister<u32>

CHCFG1R2

CH1AWSCDR: RWRegister<u32>

AWSCD1R

CH1WDATR: RWRegister<u32>

CHWDAT1R

CH1DATINR: RWRegister<u32>

CHDATIN1R

CH1DLYR: RWRegister<u32>

DFSDM channel y delay register

CH2CFGR1: RWRegister<u32>

CHCFG2R1

CH2CFGR2: RWRegister<u32>

CHCFG2R2

CH2AWSCDR: RWRegister<u32>

AWSCD2R

CH2WDATR: RWRegister<u32>

CHWDAT2R

CH2DATINR: RWRegister<u32>

CHDATIN2R

CH2DLYR: RWRegister<u32>

DFSDM channel y delay register

CH3CFGR1: RWRegister<u32>

CHCFG3R1

CH3CFGR2: RWRegister<u32>

CHCFG3R2

CH3AWSCDR: RWRegister<u32>

AWSCD3R

CH3WDATR: RWRegister<u32>

CHWDAT3R

CH3DATINR: RWRegister<u32>

CHDATIN3R

CH3DLYR: RWRegister<u32>

DFSDM channel y delay register

CH4CFGR1: RWRegister<u32>

CHCFG4R1

CH4CFGR2: RWRegister<u32>

CHCFG4R2

CH4AWSCDR: RWRegister<u32>

AWSCD4R

CH4WDATR: RWRegister<u32>

CHWDAT4R

CH4DATINR: RWRegister<u32>

CHDATIN4R

CH4DLYR: RWRegister<u32>

DFSDM channel y delay register

CH5CFGR1: RWRegister<u32>

CHCFG5R1

CH5CFGR2: RWRegister<u32>

CHCFG5R2

CH5AWSCDR: RWRegister<u32>

AWSCD5R

CH5WDATR: RWRegister<u32>

CHWDAT5R

CH5DATINR: RWRegister<u32>

CHDATIN5R

CH5DLYR: RWRegister<u32>

DFSDM channel y delay register

CH6CFGR1: RWRegister<u32>

CHCFG6R1

CH6CFGR2: RWRegister<u32>

CH6CFGR2

CH6AWSCDR: RWRegister<u32>

AWSCD6R

CH6WDATR: RWRegister<u32>

CHWDAT6R

CH6DATINR: RWRegister<u32>

CHDATIN6R

CH6DLYR: RWRegister<u32>

DFSDM channel y delay register

CH7CFGR1: RWRegister<u32>

CHCFG7R1

CH7CFGR2: RWRegister<u32>

CHCFG7R2

CH7AWSCDR: RWRegister<u32>

AWSCD7R

CH7WDATR: RWRegister<u32>

CHWDAT7R

CH7DATINR: RWRegister<u32>

CHDATIN7R

CH7DLYR: RWRegister<u32>

DFSDM channel y delay register

FLT0CR1: RWRegister<u32>

control register 1

FLT0CR2: RWRegister<u32>

control register 2

FLT0ISR: RORegister<u32>

interrupt and status register

FLT0ICR: RWRegister<u32>

interrupt flag clear register

FLT0JCHGR: RWRegister<u32>

injected channel group selection register

FLT0FCR: RWRegister<u32>

filter control register

FLT0JDATAR: RORegister<u32>

data register for injected group

FLT0RDATAR: RORegister<u32>

data register for the regular channel

FLT0AWHTR: RWRegister<u32>

analog watchdog high threshold register

FLT0AWLTR: RWRegister<u32>

analog watchdog low threshold register

FLT0AWSR: RORegister<u32>

analog watchdog status register

FLT0AWCFR: RWRegister<u32>

analog watchdog clear flag register

FLT0EXMAX: RORegister<u32>

Extremes detector maximum register

FLT0EXMIN: RORegister<u32>

Extremes detector minimum register

FLT0CNVTIMR: RORegister<u32>

conversion timer register

FLT1CR1: RWRegister<u32>

control register 1

FLT1CR2: RWRegister<u32>

control register 2

FLT1ISR: RORegister<u32>

interrupt and status register

FLT1ICR: RWRegister<u32>

interrupt flag clear register

FLT1JCHGR: RWRegister<u32>

injected channel group selection register

FLT1FCR: RWRegister<u32>

filter control register

FLT1JDATAR: RORegister<u32>

data register for injected group

FLT1RDATAR: RORegister<u32>

data register for the regular channel

FLT1AWLTR: RWRegister<u32>

analog watchdog low threshold register

FLT1AWSR: RORegister<u32>

analog watchdog status register

FLT1AW: RWRegister<u32>

FLT1AWHTR and FLT1AWCFR FLT1AWHTR: analog watchdog high threshold register FLT1AWCFR: analog watchdog clear flag register

FLT1EXMAX: RORegister<u32>

Extremes detector maximum register

FLT1EXMIN: RORegister<u32>

Extremes detector minimum register

FLT1CNVTIMR: RORegister<u32>

conversion timer register

FLT2CR1: RWRegister<u32>

control register 1

FLT2CR2: RWRegister<u32>

control register 2

FLT2ISR: RORegister<u32>

interrupt and status register

FLT2ICR: RWRegister<u32>

interrupt flag clear register

FLT2JCHGR: RWRegister<u32>

injected channel group selection register

FLT2FCR: RWRegister<u32>

filter control register

FLT2JDATAR: RORegister<u32>

data register for injected group

FLT2RDATAR: RORegister<u32>

data register for the regular channel

FLT2AWHTR: RWRegister<u32>

analog watchdog high threshold register

FLT2AWLTR: RWRegister<u32>

analog watchdog low threshold register

FLT2AWSR: RORegister<u32>

analog watchdog status register

FLT2AWCFR: RWRegister<u32>

analog watchdog clear flag register

FLT2EXMAX: RORegister<u32>

Extremes detector maximum register

FLT2EXMIN: RORegister<u32>

Extremes detector minimum register

FLT2CNVTIMR: RORegister<u32>

conversion timer register

FLT3CR1: RWRegister<u32>

control register 1

FLT3CR2: RWRegister<u32>

control register 2

FLT3ISR: RORegister<u32>

interrupt and status register

FLT3ICR: RWRegister<u32>

interrupt flag clear register

FLT3JCHGR: RWRegister<u32>

injected channel group selection register

FLT3FCR: RWRegister<u32>

filter control register

FLT3JDATAR: RORegister<u32>

data register for injected group

FLT3RDATAR: RORegister<u32>

data register for the regular channel

FLT3AWHTR: RWRegister<u32>

analog watchdog high threshold register

FLT3AWLTR: RWRegister<u32>

analog watchdog low threshold register

FLT3AWSR: RORegister<u32>

analog watchdog status register

FLT3AWCFR: RWRegister<u32>

analog watchdog clear flag register

FLT3EXMAX: RORegister<u32>

Extremes detector maximum register

FLT3EXMIN: RORegister<u32>

Extremes detector minimum register

FLT3CNVTIMR: RORegister<u32>

conversion timer register

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Performs the conversion.

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The type returned in the event of a conversion error.

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