Struct stm32ral::stm32l4::stm32l4x6::dfsdm1::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 100 fields
pub CHCFG0R1: RWRegister<u32>,
pub CHCFG0R2: RWRegister<u32>,
pub AWSCD0R: RWRegister<u32>,
pub CHWDAT0R: RWRegister<u32>,
pub CHDATIN0R: RWRegister<u32>,
pub CHCFG1R1: RWRegister<u32>,
pub CHCFG1R2: RWRegister<u32>,
pub AWSCD1R: RWRegister<u32>,
pub CHWDAT1R: RWRegister<u32>,
pub CHDATIN1R: RWRegister<u32>,
pub CHCFG2R1: RWRegister<u32>,
pub CHCFG2R2: RWRegister<u32>,
pub AWSCD2R: RWRegister<u32>,
pub CHWDAT2R: RWRegister<u32>,
pub CHDATIN2R: RWRegister<u32>,
pub CHCFG3R1: RWRegister<u32>,
pub CHCFG3R2: RWRegister<u32>,
pub AWSCD3R: RWRegister<u32>,
pub CHWDAT3R: RWRegister<u32>,
pub CHDATIN3R: RWRegister<u32>,
pub CHCFG4R1: RWRegister<u32>,
pub CHCFG4R2: RWRegister<u32>,
pub AWSCD4R: RWRegister<u32>,
pub CHWDAT4R: RWRegister<u32>,
pub CHDATIN4R: RWRegister<u32>,
pub CHCFG5R1: RWRegister<u32>,
pub CHCFG5R2: RWRegister<u32>,
pub AWSCD5R: RWRegister<u32>,
pub CHWDAT5R: RWRegister<u32>,
pub CHDATIN5R: RWRegister<u32>,
pub CHCFG6R1: RWRegister<u32>,
pub CHCFG6R2: RWRegister<u32>,
pub AWSCD6R: RWRegister<u32>,
pub CHWDAT6R: RWRegister<u32>,
pub CHDATIN6R: RWRegister<u32>,
pub CHCFG7R1: RWRegister<u32>,
pub CHCFG7R2: RWRegister<u32>,
pub AWSCD7R: RWRegister<u32>,
pub CHWDAT7R: RWRegister<u32>,
pub CHDATIN7R: RWRegister<u32>,
pub DFSDM0_CR1: RWRegister<u32>,
pub DFSDM0_CR2: RWRegister<u32>,
pub DFSDM0_ISR: RORegister<u32>,
pub DFSDM0_ICR: RWRegister<u32>,
pub DFSDM0_JCHGR: RWRegister<u32>,
pub DFSDM0_FCR: RWRegister<u32>,
pub DFSDM0_JDATAR: RORegister<u32>,
pub DFSDM0_RDATAR: RORegister<u32>,
pub DFSDM0_AWHTR: RWRegister<u32>,
pub DFSDM0_AWLTR: RWRegister<u32>,
pub DFSDM0_AWSR: RORegister<u32>,
pub DFSDM0_AWCFR: RWRegister<u32>,
pub DFSDM0_EXMAX: RORegister<u32>,
pub DFSDM0_EXMIN: RORegister<u32>,
pub DFSDM0_CNVTIMR: RORegister<u32>,
pub DFSDM1_CR1: RWRegister<u32>,
pub DFSDM1_CR2: RWRegister<u32>,
pub DFSDM1_ISR: RORegister<u32>,
pub DFSDM1_ICR: RWRegister<u32>,
pub DFSDM1_JCHGR: RWRegister<u32>,
pub DFSDM1_FCR: RWRegister<u32>,
pub DFSDM1_JDATAR: RORegister<u32>,
pub DFSDM1_RDATAR: RORegister<u32>,
pub DFSDM1_AWHTR: RWRegister<u32>,
pub DFSDM1_AWLTR: RWRegister<u32>,
pub DFSDM1_AWSR: RORegister<u32>,
pub DFSDM1_AWCFR: RWRegister<u32>,
pub DFSDM1_EXMAX: RORegister<u32>,
pub DFSDM1_EXMIN: RORegister<u32>,
pub DFSDM1_CNVTIMR: RORegister<u32>,
pub DFSDM2_CR1: RWRegister<u32>,
pub DFSDM2_CR2: RWRegister<u32>,
pub DFSDM2_ISR: RORegister<u32>,
pub DFSDM2_ICR: RWRegister<u32>,
pub DFSDM2_JCHGR: RWRegister<u32>,
pub DFSDM2_FCR: RWRegister<u32>,
pub DFSDM2_JDATAR: RORegister<u32>,
pub DFSDM2_RDATAR: RORegister<u32>,
pub DFSDM2_AWHTR: RWRegister<u32>,
pub DFSDM2_AWLTR: RWRegister<u32>,
pub DFSDM2_AWSR: RORegister<u32>,
pub DFSDM2_AWCFR: RWRegister<u32>,
pub DFSDM2_EXMAX: RORegister<u32>,
pub DFSDM2_EXMIN: RORegister<u32>,
pub DFSDM2_CNVTIMR: RORegister<u32>,
pub DFSDM3_CR1: RWRegister<u32>,
pub DFSDM3_CR2: RWRegister<u32>,
pub DFSDM3_ISR: RORegister<u32>,
pub DFSDM3_ICR: RWRegister<u32>,
pub DFSDM3_JCHGR: RWRegister<u32>,
pub DFSDM3_FCR: RWRegister<u32>,
pub DFSDM3_JDATAR: RORegister<u32>,
pub DFSDM3_RDATAR: RORegister<u32>,
pub DFSDM3_AWHTR: RWRegister<u32>,
pub DFSDM3_AWLTR: RWRegister<u32>,
pub DFSDM3_AWSR: RORegister<u32>,
pub DFSDM3_AWCFR: RWRegister<u32>,
pub DFSDM3_EXMAX: RORegister<u32>,
pub DFSDM3_EXMIN: RORegister<u32>,
pub DFSDM3_CNVTIMR: RORegister<u32>,
// some fields omitted
}
Fields
CHCFG0R1: RWRegister<u32>
channel configuration y register
CHCFG0R2: RWRegister<u32>
channel configuration y register
AWSCD0R: RWRegister<u32>
analog watchdog and short-circuit detector register
CHWDAT0R: RWRegister<u32>
channel watchdog filter data register
CHDATIN0R: RWRegister<u32>
channel data input register
CHCFG1R1: RWRegister<u32>
CHCFG1R1
CHCFG1R2: RWRegister<u32>
CHCFG1R2
AWSCD1R: RWRegister<u32>
AWSCD1R
CHWDAT1R: RWRegister<u32>
CHWDAT1R
CHDATIN1R: RWRegister<u32>
CHDATIN1R
CHCFG2R1: RWRegister<u32>
CHCFG2R1
CHCFG2R2: RWRegister<u32>
CHCFG2R2
AWSCD2R: RWRegister<u32>
AWSCD2R
CHWDAT2R: RWRegister<u32>
CHWDAT2R
CHDATIN2R: RWRegister<u32>
CHDATIN2R
CHCFG3R1: RWRegister<u32>
CHCFG3R1
CHCFG3R2: RWRegister<u32>
CHCFG3R2
AWSCD3R: RWRegister<u32>
AWSCD3R
CHWDAT3R: RWRegister<u32>
CHWDAT3R
CHDATIN3R: RWRegister<u32>
CHDATIN3R
CHCFG4R1: RWRegister<u32>
CHCFG4R1
CHCFG4R2: RWRegister<u32>
CHCFG4R2
AWSCD4R: RWRegister<u32>
AWSCD4R
CHWDAT4R: RWRegister<u32>
CHWDAT4R
CHDATIN4R: RWRegister<u32>
CHDATIN4R
CHCFG5R1: RWRegister<u32>
CHCFG5R1
CHCFG5R2: RWRegister<u32>
CHCFG5R2
AWSCD5R: RWRegister<u32>
AWSCD5R
CHWDAT5R: RWRegister<u32>
CHWDAT5R
CHDATIN5R: RWRegister<u32>
CHDATIN5R
CHCFG6R1: RWRegister<u32>
CHCFG6R1
CHCFG6R2: RWRegister<u32>
CHCFG6R2
AWSCD6R: RWRegister<u32>
AWSCD6R
CHWDAT6R: RWRegister<u32>
CHWDAT6R
CHDATIN6R: RWRegister<u32>
CHDATIN6R
CHCFG7R1: RWRegister<u32>
CHCFG7R1
CHCFG7R2: RWRegister<u32>
CHCFG7R2
AWSCD7R: RWRegister<u32>
AWSCD7R
CHWDAT7R: RWRegister<u32>
CHWDAT7R
CHDATIN7R: RWRegister<u32>
CHDATIN7R
DFSDM0_CR1: RWRegister<u32>
control register 1
DFSDM0_CR2: RWRegister<u32>
control register 2
DFSDM0_ISR: RORegister<u32>
interrupt and status register
DFSDM0_ICR: RWRegister<u32>
interrupt flag clear register
DFSDM0_JCHGR: RWRegister<u32>
injected channel group selection register
DFSDM0_FCR: RWRegister<u32>
filter control register
DFSDM0_JDATAR: RORegister<u32>
data register for injected group
DFSDM0_RDATAR: RORegister<u32>
data register for the regular channel
DFSDM0_AWHTR: RWRegister<u32>
analog watchdog high threshold register
DFSDM0_AWLTR: RWRegister<u32>
analog watchdog low threshold register
DFSDM0_AWSR: RORegister<u32>
analog watchdog status register
DFSDM0_AWCFR: RWRegister<u32>
analog watchdog clear flag register
DFSDM0_EXMAX: RORegister<u32>
Extremes detector maximum register
DFSDM0_EXMIN: RORegister<u32>
Extremes detector minimum register
DFSDM0_CNVTIMR: RORegister<u32>
conversion timer register
DFSDM1_CR1: RWRegister<u32>
control register 1
DFSDM1_CR2: RWRegister<u32>
control register 2
DFSDM1_ISR: RORegister<u32>
interrupt and status register
DFSDM1_ICR: RWRegister<u32>
interrupt flag clear register
DFSDM1_JCHGR: RWRegister<u32>
injected channel group selection register
DFSDM1_FCR: RWRegister<u32>
filter control register
DFSDM1_JDATAR: RORegister<u32>
data register for injected group
DFSDM1_RDATAR: RORegister<u32>
data register for the regular channel
DFSDM1_AWHTR: RWRegister<u32>
analog watchdog high threshold register
DFSDM1_AWLTR: RWRegister<u32>
analog watchdog low threshold register
DFSDM1_AWSR: RORegister<u32>
analog watchdog status register
DFSDM1_AWCFR: RWRegister<u32>
analog watchdog clear flag register
DFSDM1_EXMAX: RORegister<u32>
Extremes detector maximum register
DFSDM1_EXMIN: RORegister<u32>
Extremes detector minimum register
DFSDM1_CNVTIMR: RORegister<u32>
conversion timer register
DFSDM2_CR1: RWRegister<u32>
control register 1
DFSDM2_CR2: RWRegister<u32>
control register 2
DFSDM2_ISR: RORegister<u32>
interrupt and status register
DFSDM2_ICR: RWRegister<u32>
interrupt flag clear register
DFSDM2_JCHGR: RWRegister<u32>
injected channel group selection register
DFSDM2_FCR: RWRegister<u32>
filter control register
DFSDM2_JDATAR: RORegister<u32>
data register for injected group
DFSDM2_RDATAR: RORegister<u32>
data register for the regular channel
DFSDM2_AWHTR: RWRegister<u32>
analog watchdog high threshold register
DFSDM2_AWLTR: RWRegister<u32>
analog watchdog low threshold register
DFSDM2_AWSR: RORegister<u32>
analog watchdog status register
DFSDM2_AWCFR: RWRegister<u32>
analog watchdog clear flag register
DFSDM2_EXMAX: RORegister<u32>
Extremes detector maximum register
DFSDM2_EXMIN: RORegister<u32>
Extremes detector minimum register
DFSDM2_CNVTIMR: RORegister<u32>
conversion timer register
DFSDM3_CR1: RWRegister<u32>
control register 1
DFSDM3_CR2: RWRegister<u32>
control register 2
DFSDM3_ISR: RORegister<u32>
interrupt and status register
DFSDM3_ICR: RWRegister<u32>
interrupt flag clear register
DFSDM3_JCHGR: RWRegister<u32>
injected channel group selection register
DFSDM3_FCR: RWRegister<u32>
filter control register
DFSDM3_JDATAR: RORegister<u32>
data register for injected group
DFSDM3_RDATAR: RORegister<u32>
data register for the regular channel
DFSDM3_AWHTR: RWRegister<u32>
analog watchdog high threshold register
DFSDM3_AWLTR: RWRegister<u32>
analog watchdog low threshold register
DFSDM3_AWSR: RORegister<u32>
analog watchdog status register
DFSDM3_AWCFR: RWRegister<u32>
analog watchdog clear flag register
DFSDM3_EXMAX: RORegister<u32>
Extremes detector maximum register
DFSDM3_EXMIN: RORegister<u32>
Extremes detector minimum register
DFSDM3_CNVTIMR: RORegister<u32>
conversion timer register